From a789761de3053d25f03787ac40897dbea14ee368 Mon Sep 17 00:00:00 2001 From: Benjamin Welton Date: Mon, 9 Feb 2026 00:42:00 +0800 Subject: [PATCH 01/71] amd/amdkfd: Add kfd_ioctl_profiler to contain profiler kernel driver changes kfd_ioctl_profiler takes a similar approach to that of kfd_ioctl_dbg_trap (which contains debugger related IOCTL services) where kfd_ioctl_profiler will contain all profiler related IOCTL services. The IOCTL is designed to be expanded as needed to support additional profiler functionality. The current functionality of the IOCTL is to allow for profilers which need PMC counters from GPU devices to both signal to other profilers that may be on the system that the device has active PMC profiling taking place on it (multiple PMC profilers on the same device can result in corrupted counter data) and to setup the device to allow for the collection of SQ PMC data on all queues on the device. For PMC data for the SQ block (such as SQ_WAVES) to be available to a profiler, mmPERFCOUNT_ENABLE must be set on the queues. When profiling a single process, the profiler can inject PM4 packets into each queue to turn on PERFCOUNT_ENABLE. When profiling system wide, the profiler does not have this option and must have a way to turn on profiling for queues in which it cannot inject packets into directly. Accomplishing this requires a few steps: 1. Checking if the user has the necessary permissions to profile system wide on the device. This check uses the same check that linux perf uses to determine if a user has the necessary permissions to profile at this scope (primarily if the process has CAP_SYS_PERFMON or is root). 2. Locking the device for profiling. This is done by setting a lock bit on the device struct and storing the process that locked the device. 3. Iterating all queues on the device and issuing an MQD Update to enable perfcounting on the queues. 4. Actions to cleanup if the process exits or releases the lock. The IOCTL also contains a link to the existing PC Sampling IOCTL as well. This is per a suggestion that we should potentially remove the PC Sampling IOCTL to have it be a part of the profiler IOCTL. This is a future change. In addition, we do expect to expand the profiler IOCTL to include additional profiler functionality in the future (which necessitates the use of a version number). v2: sqaush in proper IOCTL number Proposed userpace support: https://github.com/ROCm/rocm-systems/commit/40abc95a6463a61bb318a67efd6d9cc3e5ee8839 Signed-off-by: Benjamin Welton Signed-off-by: Perry Yuan Acked-by: Kent Russell Reviewed-by: Yifan Zhang Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 82 +++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 + .../drm/amd/amdkfd/kfd_device_queue_manager.c | 25 ++++++ .../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 + .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 16 +++- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 14 +++- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 8 +- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 15 +++- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 11 +++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 7 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 11 +++ include/uapi/linux/kfd_ioctl.h | 28 ++++++- 12 files changed, 214 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index dd27d7ba2ee2..d18ec3671fda 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -21,6 +21,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #include #include @@ -3216,6 +3217,84 @@ static int kfd_ioctl_create_process(struct file *filep, struct kfd_process *p, v return 0; } +static inline uint32_t profile_lock_device(struct kfd_process *p, + uint32_t gpu_id, uint32_t op) +{ + struct kfd_process_device *pdd; + struct kfd_dev *kfd; + int status = -EINVAL; + + if (!p) + return -EINVAL; + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, gpu_id); + mutex_unlock(&p->mutex); + + if (!pdd || !pdd->dev || !pdd->dev->kfd) + return -EINVAL; + + kfd = pdd->dev->kfd; + + mutex_lock(&kfd->profiler_lock); + if (op == 1) { + if (!kfd->profiler_process) { + kfd->profiler_process = p; + status = 0; + } else if (kfd->profiler_process == p) { + status = -EALREADY; + } else { + status = -EBUSY; + } + } else if (op == 0 && kfd->profiler_process == p) { + kfd->profiler_process = NULL; + status = 0; + } + mutex_unlock(&kfd->profiler_lock); + + return status; +} + +static inline int kfd_profiler_pmc(struct kfd_process *p, + struct kfd_ioctl_pmc_settings *args) +{ + struct kfd_process_device *pdd; + struct device_queue_manager *dqm; + int status; + + /* Check if we have the correct permissions. */ + if (!perfmon_capable()) + return -EPERM; + + /* Lock/Unlock the device based on the parameter given in OP */ + status = profile_lock_device(p, args->gpu_id, args->lock); + if (status != 0) + return status; + + /* Enable/disable perfcount if requested */ + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + dqm = pdd->dev->dqm; + mutex_unlock(&p->mutex); + + dqm->ops.set_perfcount(dqm, args->perfcount_enable); + return status; +} + +static int kfd_ioctl_profiler(struct file *filep, struct kfd_process *p, void *data) +{ + struct kfd_ioctl_profiler_args *args = data; + + switch (args->op) { + case KFD_IOC_PROFILER_VERSION: + args->version = KFD_IOC_PROFILER_VERSION_NUM; + return 0; + case KFD_IOC_PROFILER_PMC: + return kfd_profiler_pmc(p, &args->pmc); + } + return -EINVAL; +} + #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ .validate = NULL, .cmd_drv = 0, .name = #ioctl} @@ -3342,6 +3421,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_PROCESS, kfd_ioctl_create_process, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_PROFILER, + kfd_ioctl_profiler, 0), }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index b7f8f7ff8198..d649d8603e28 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -936,6 +936,9 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, svm_range_set_max_pages(kfd->adev); + kfd->profiler_process = NULL; + mutex_init(&kfd->profiler_lock); + kfd->init_complete = true; dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, kfd->adev->pdev->device); @@ -971,6 +974,7 @@ void kgd2kfd_device_exit(struct kfd_dev *kfd) ida_destroy(&kfd->doorbell_ida); kfd_gtt_sa_fini(kfd); amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); + mutex_destroy(&kfd->profiler_lock); } kfree(kfd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index a9ac575537e5..c64a1e19fa3f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -324,6 +324,29 @@ static int remove_queue_mes_on_reset_option(struct device_queue_manager *dqm, st return r; } +static void set_perfcount(struct device_queue_manager *dqm, int enable) +{ + struct device_process_node *cur; + struct qcm_process_device *qpd; + struct queue *q; + struct mqd_update_info minfo = { 0 }; + + if (!dqm) + return; + + minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : + UPDATE_FLAG_PERFCOUNT_DISABLE); + dqm_lock(dqm); + list_for_each_entry(cur, &dqm->queues, list) { + qpd = cur->qpd; + list_for_each_entry(q, &qpd->queues_list, list) { + pqm_update_mqd(qpd->pqm, q->properties.queue_id, + &minfo); + } + } + dqm_unlock(dqm); +} + static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, struct qcm_process_device *qpd) { @@ -3113,6 +3136,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.reset_queues = reset_queues_cpsch; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; + dqm->ops.set_perfcount = set_perfcount; break; case KFD_SCHED_POLICY_NO_HWS: /* initialize dqm for no cp scheduling */ @@ -3133,6 +3157,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.get_wave_state = get_wave_state; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; + dqm->ops.set_perfcount = set_perfcount; break; default: dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index a0323501c6b9..e0b6a47e7722 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -199,6 +199,8 @@ struct device_queue_manager_ops { const struct queue *q, void *mqd, void *ctl_stack); + void (*set_perfcount)(struct device_queue_manager *dqm, + int enable); }; struct device_queue_manager_asic_ops { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 77fb41e2486a..8e8ec266ca46 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -123,10 +123,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, */ m->cp_hqd_hq_scheduler0 = 1 << 14; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -141,6 +140,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -220,6 +225,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } + update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index a1e3cf2384dd..7568e7ed5244 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -163,10 +163,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -181,6 +180,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -258,6 +262,12 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, } if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index b3e122d7876e..8c815f129614 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -138,10 +138,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -156,6 +155,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index e8f97de9d6e4..56a7679ca98d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -227,10 +227,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - if (q->tba_addr) { + if (q->tba_addr) m->compute_pgm_rsrc2 |= (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); - } if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { m->cp_hqd_persistent_state |= @@ -245,6 +244,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -327,6 +331,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } + if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 431a20323146..c86779af323b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -148,6 +148,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -230,6 +235,12 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_ctx_save_control = atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 9fe5c66d8013..903386e0740b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -383,6 +383,11 @@ struct kfd_dev { int kfd_dev_lock; atomic_t kfd_processes_count; + + /* Lock for profiler process */ + struct mutex profiler_lock; + /* Process currently holding the lock */ + struct kfd_process *profiler_process; }; enum kfd_mempool { @@ -556,6 +561,8 @@ enum mqd_update_flag { UPDATE_FLAG_DBG_WA_ENABLE = 1, UPDATE_FLAG_DBG_WA_DISABLE = 2, UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ + UPDATE_FLAG_PERFCOUNT_ENABLE = 5, + UPDATE_FLAG_PERFCOUNT_DISABLE = 6, }; struct mqd_update_info { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 9228e4a949ed..1a8cb512dfe3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1106,6 +1106,16 @@ static void kfd_process_free_outstanding_kfd_bos(struct kfd_process *p) kfd_process_device_free_bos(p->pdds[i]); } +static void kfd_process_profiler_release(struct kfd_process *p, struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->dev->kfd->profiler_lock); + if (pdd->dev->kfd->profiler_process == p) { + pdd->qpd.dqm->ops.set_perfcount(pdd->qpd.dqm, 0); + pdd->dev->kfd->profiler_process = NULL; + } + mutex_unlock(&pdd->dev->kfd->profiler_lock); +} + static void kfd_process_destroy_pdds(struct kfd_process *p) { int i; @@ -1117,6 +1127,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pr_debug("Releasing pdd (topology id %d, for pid %d)\n", pdd->dev->id, p->lead_thread->pid); + kfd_process_profiler_release(p, pdd); kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index e72359370857..cc3ed0765c83 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1558,6 +1558,29 @@ struct kfd_ioctl_dbg_trap_args { }; }; +#define KFD_IOC_PROFILER_VERSION_NUM 1 +enum kfd_profiler_ops { + KFD_IOC_PROFILER_PMC = 0, + KFD_IOC_PROFILER_VERSION = 2, +}; + +/** + * Enables/Disables GPU Specific profiler settings + */ +struct kfd_ioctl_pmc_settings { + __u32 gpu_id; /* This is the user_gpu_id */ + __u32 lock; /* Lock GPU for Profiling */ + __u32 perfcount_enable; /* Force Perfcount Enable for queues on GPU */ +}; + +struct kfd_ioctl_profiler_args { + __u32 op; /* kfd_profiler_op */ + union { + struct kfd_ioctl_pmc_settings pmc; + __u32 version; /* KFD_IOC_PROFILER_VERSION_NUM */ + }; +}; + #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) @@ -1681,7 +1704,10 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_CREATE_PROCESS \ AMDKFD_IO(0x27) +#define AMDKFD_IOC_PROFILER \ + AMDKFD_IOWR(0x28, struct kfd_ioctl_profiler_args) + #define AMDKFD_COMMAND_START 0x01 -#define AMDKFD_COMMAND_END 0x28 +#define AMDKFD_COMMAND_END 0x29 #endif From e486360db8df9d032bfff44b629d25a803a1d21c Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 9 Feb 2026 00:42:01 +0800 Subject: [PATCH 02/71] drm/amdgpu: add new performance monitor PSP interfaces Introduce new psp interfaces and structures for performance monitoring hardware control. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 21 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 17 +++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 7e94ec11c57e..73e7e919c851 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -358,6 +358,27 @@ struct spirom_bo { }; #endif +enum psp_ptl_cmd { + PSP_PTL_PERF_MON_QUERY = 0xA0000000, + PSP_PTL_PERF_MON_SET = 0xA0000001, +}; + +enum psp_ptl_format_type { + GFX_FTYPE_I8 = 0x00000000, + GFX_FTYPE_F16 = 0x00000001, + GFX_FTYPE_BF16 = 0x00000002, + GFX_FTYPE_F32 = 0x00000003, + GFX_FTYPE_F64 = 0x00000004, + GFX_FTYPE_INVALID = 0xFFFFFFFF, +}; + +struct psp_ptl_perf_req { + enum psp_ptl_cmd req; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + struct psp_context { struct amdgpu_device *adev; struct psp_ring km_ring; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index e8f768638fd5..ac34bac3c839 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -107,6 +107,7 @@ enum psp_gfx_cmd_id GFX_CMD_ID_CONFIG_SQ_PERFMON = 0x00000046, /* Config CGTT_SQ_CLK_CTRL */ /* Dynamic memory partitioninig (NPS mode change)*/ GFX_CMD_ID_FB_NPS_MODE = 0x00000048, /* Configure memory partitioning mode */ + GFX_CMD_ID_PERF_HW = 0x0000004C, /* performance monitor */ GFX_CMD_ID_FB_FW_RESERV_ADDR = 0x00000050, /* Query FW reservation addr */ GFX_CMD_ID_FB_FW_RESERV_EXT_ADDR = 0x00000051, /* Query FW reservation extended addr */ }; @@ -373,6 +374,13 @@ struct psp_gfx_cmd_fb_memory_part { uint32_t resvd; }; +struct psp_gfx_cmd_req_perf_hw { + uint32_t req; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + /* All GFX ring buffer commands. */ union psp_gfx_commands { @@ -389,6 +397,7 @@ union psp_gfx_commands struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part; struct psp_gfx_cmd_config_sq_perfmon config_sq_perfmon; struct psp_gfx_cmd_fb_memory_part cmd_memory_part; + struct psp_gfx_cmd_req_perf_hw cmd_req_perf_hw; }; struct psp_gfx_uresp_reserved @@ -415,12 +424,20 @@ struct psp_gfx_uresp_fw_reserve_info { uint32_t reserve_size; }; +struct psp_gfx_uresp_perf_hw { + uint32_t resp; + uint32_t ptl_state; + uint32_t pref_format1; + uint32_t pref_format2; +}; + /* Union of command-specific responses for GPCOM ring. */ union psp_gfx_uresp { struct psp_gfx_uresp_reserved reserved; struct psp_gfx_uresp_bootcfg boot_cfg; struct psp_gfx_uresp_fwar_db_info fwar_db_info; struct psp_gfx_uresp_fw_reserve_info fw_reserve_info; + struct psp_gfx_uresp_perf_hw perf_hw_info; }; /* Structure of GFX Response buffer. From 8ce9c73104e34f1fbb8d7f50468e4a62905331f2 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 9 Feb 2026 00:42:02 +0800 Subject: [PATCH 03/71] drm/amdgpu: add psp interfaces for peak tops limiter driver Introduce a Peak Tops Limiter (PTL) driver that dynamically caps engine frequency to ensure delivered TOPS never exceeds a defined TOPS_limit. This initial implementation provides core data structures and kernel-space interfaces (set/get, enable/disable) to manage PTL state. PTL performs a firmware handshake to initialize its state and update predefined format types. It supports updating these format types at runtime while user-space tools automatically switch PTL state, and also allows explicitly switching PTL state via newly added commands. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 111 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 + drivers/gpu/drm/amd/include/amdgpu_ptl.h | 50 ++++++++ .../gpu/drm/amd/include/kgd_kfd_interface.h | 1 + 7 files changed, 168 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/include/amdgpu_ptl.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index cdbab7f8cee8..4fee011c2e26 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -38,6 +38,8 @@ #include "amdgpu_vm.h" #include "amdgpu_xcp.h" #include "kfd_topology.h" +#include "amdgpu_ptl.h" + extern uint64_t amdgpu_amdkfd_total_mem_size; enum TLB_FLUSH_TYPE { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index d293444d026f..d91bf647757f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3731,6 +3731,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->virt.vf_errors.lock); hash_init(adev->mn_hash); mutex_init(&adev->psp.mutex); + mutex_init(&adev->psp.ptl.mutex); mutex_init(&adev->notifier_lock); mutex_init(&adev->pm.stable_pstate_ctx_lock); mutex_init(&adev->benchmark_mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 4a64e39fa9cd..0734ddaf6388 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -682,6 +682,8 @@ static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) return "SPATIAL_PARTITION"; case GFX_CMD_ID_FB_NPS_MODE: return "NPS_MODE_CHANGE"; + case GFX_CMD_ID_PERF_HW: + return "PERF MONITORING HW"; default: return "UNKNOWN CMD"; } @@ -1201,6 +1203,115 @@ int psp_memory_partition(struct psp_context *psp, int mode) return ret; } +static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, + uint32_t *ptl_fmt) +{ + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4)) + return -EINVAL; + + switch (fmt) { + case AMDGPU_PTL_FMT_I8: + *ptl_fmt = GFX_FTYPE_I8; + break; + case AMDGPU_PTL_FMT_F16: + *ptl_fmt = GFX_FTYPE_F16; + break; + case AMDGPU_PTL_FMT_BF16: + *ptl_fmt = GFX_FTYPE_BF16; + break; + case AMDGPU_PTL_FMT_F32: + *ptl_fmt = GFX_FTYPE_F32; + break; + case AMDGPU_PTL_FMT_F64: + *ptl_fmt = GFX_FTYPE_F64; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, + uint32_t *ptl_state, uint32_t *fmt1, uint32_t *fmt2) +{ + struct psp_gfx_cmd_resp *cmd; + struct amdgpu_ptl *ptl = &psp->ptl; + int ret; + + cmd = acquire_psp_cmd_buf(psp); + + cmd->cmd_id = GFX_CMD_ID_PERF_HW; + cmd->cmd.cmd_req_perf_hw.req = req_code; + cmd->cmd.cmd_req_perf_hw.ptl_state = *ptl_state; + cmd->cmd.cmd_req_perf_hw.pref_format1 = *fmt1; + cmd->cmd.cmd_req_perf_hw.pref_format2 = *fmt2; + + ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); + if (ret) + goto out; + + /* Parse response */ + switch (req_code) { + case PSP_PTL_PERF_MON_QUERY: + *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; + *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; + *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; + break; + case PSP_PTL_PERF_MON_SET: + /* Update cached state only on success */ + ptl->enabled = *ptl_state; + ptl->fmt1 = *fmt1; + ptl->fmt2 = *fmt2; + break; + } + +out: + release_psp_cmd_buf(psp); + return ret; +} + +int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, + uint32_t *ptl_state, + enum amdgpu_ptl_fmt *fmt1, + enum amdgpu_ptl_fmt *fmt2) +{ + uint32_t ptl_fmt1, ptl_fmt2; + struct psp_context *psp; + struct amdgpu_ptl *ptl; + + if (!adev || !ptl_state || !fmt1 || !fmt2) + return -EINVAL; + + if (amdgpu_sriov_vf(adev)) + return 0; + + psp = &adev->psp; + ptl = &psp->ptl; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || + psp->sos.fw_version < 0x0036081a) + return -EOPNOTSUPP; + + /* Verify formats */ + if (psp_ptl_fmt_verify(psp, *fmt1, &ptl_fmt1) || + psp_ptl_fmt_verify(psp, *fmt2, &ptl_fmt2)) + return -EINVAL; + + /* + * Add check to skip if state and formats are identical to current ones + */ + if (req_code == PSP_PTL_PERF_MON_SET && + ptl->enabled == *ptl_state && + ptl->fmt1 == ptl_fmt1 && + ptl->fmt2 == ptl_fmt2) + return 0; + + return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); +} + int psp_spatial_partition(struct psp_context *psp, int mode) { struct psp_gfx_cmd_resp *cmd; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 73e7e919c851..979650182431 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -31,6 +31,7 @@ #include "ta_ras_if.h" #include "ta_rap_if.h" #include "ta_secureDisplay_if.h" +#include "amdgpu_ptl.h" #define PSP_FENCE_BUFFER_SIZE 0x1000 #define PSP_CMD_BUFFER_SIZE 0x1000 @@ -469,6 +470,7 @@ struct psp_context { #if defined(CONFIG_DEBUG_FS) struct spirom_bo *spirom_dump_trip; #endif + struct amdgpu_ptl ptl; }; struct amdgpu_psp_funcs { @@ -652,5 +654,4 @@ void amdgpu_psp_debugfs_init(struct amdgpu_device *adev); int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type); - #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index d18ec3671fda..fc00d0418684 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -45,6 +45,7 @@ #include "kfd_smi_events.h" #include "amdgpu_dma_buf.h" #include "kfd_debug.h" +#include "amdgpu_ptl.h" static long kfd_ioctl(struct file *, unsigned int, unsigned long); static int kfd_open(struct inode *, struct file *); diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h new file mode 100644 index 000000000000..17e803f4caf8 --- /dev/null +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -0,0 +1,50 @@ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __AMDGPU_PTL_H__ +#define __AMDGPU_PTL_H__ + +enum amdgpu_ptl_fmt { + AMDGPU_PTL_FMT_I8 = 0, + AMDGPU_PTL_FMT_F16 = 1, + AMDGPU_PTL_FMT_BF16 = 2, + AMDGPU_PTL_FMT_F32 = 3, + AMDGPU_PTL_FMT_F64 = 4, + AMDGPU_PTL_FMT_F8 = 5, + AMDGPU_PTL_FMT_VECTOR = 6, + AMDGPU_PTL_FMT_INVALID = 7, +}; + +struct amdgpu_ptl { + enum amdgpu_ptl_fmt fmt1; + enum amdgpu_ptl_fmt fmt2; + bool enabled; + bool hw_supported; + struct mutex mutex; +}; + +int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, + u32 *ptl_state, + enum amdgpu_ptl_fmt *fmt1, + enum amdgpu_ptl_fmt *fmt2); + +#endif /* __AMDGPU_PTL_H__ */ diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 9aba8596faa7..6df5afb242ae 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -33,6 +33,7 @@ #include #include "amdgpu_irq.h" #include "amdgpu_gfx.h" +#include "amdgpu_ptl.h" struct pci_dev; struct amdgpu_device; From f9f9fe3a7efba665e1c17fb5186d616c4f0a350f Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 9 Feb 2026 00:42:03 +0800 Subject: [PATCH 04/71] drm/amdgpu: add PTL enable/query gfx control support for GC 9.4.4 Introduce hardware detection, runtime state tracking and a kgd->ptl_ctrl() callback to enable/disable/query PTL via the PSP performance-monitor interface (commands 0xA0000000/1). The driver now exposes PTL capability to KFD and keeps the software state in sync with the hardware. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 34 +++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index d0b8fb931720..467a3dbe1bfa 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2374,11 +2374,43 @@ static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) return r; } +static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool enable) +{ + struct amdgpu_ptl *ptl = &adev->psp.ptl; + uint32_t ptl_state = enable ? 1 : 0; + uint32_t fmt1, fmt2; + int r; + + if (!adev->psp.funcs) + return -EOPNOTSUPP; + + if (!ptl->hw_supported) { + fmt1 = GFX_FTYPE_I8; + fmt2 = GFX_FTYPE_BF16; + } else { + fmt1 = ptl->fmt1; + fmt2 = ptl->fmt2; + } + + /* initialize PTL with default formats: GFX_FTYPE_I8 & GFX_FTYPE_BF16 */ + r = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, + &fmt1, &fmt2); + if (r) + return r; + + ptl->hw_supported = true; + + return 0; +} + static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; int i, num_xcc; + if (adev->psp.ptl.hw_supported) + gfx_v9_4_3_perf_monitor_ptl_init(adev, false); + amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); @@ -2553,6 +2585,8 @@ static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) adev->gfx.ras->enable_watchdog_timer) adev->gfx.ras->enable_watchdog_timer(adev); + gfx_v9_4_3_perf_monitor_ptl_init(adev, true); + return 0; } From c2396ee6143a364b013588af2e60759f449f2b60 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 9 Feb 2026 00:42:04 +0800 Subject: [PATCH 05/71] drm/amdkfd: add kgd control interface for ptl Add kgd->ptl_ctrl() callback so KFD can query/enable/disable PTL state through the PSP performance monitor interface. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 13 ++++++++++++- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 5 +++++ 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index f35947be3763..6ed399163547 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -520,6 +520,16 @@ static uint32_t kgd_gfx_v9_4_3_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return is_active ? doorbell_off >> 2 : 0; } +static uint32_t kgd_v9_4_3_ptl_ctrl(struct amdgpu_device *adev, + uint32_t cmd, + uint32_t *ptl_state, + enum amdgpu_ptl_fmt *fmt1, + enum amdgpu_ptl_fmt *fmt2) +{ + return amdgpu_ptl_perf_monitor_ctrl(adev, cmd, + ptl_state, fmt1, fmt2); +} + const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_4_3_set_pasid_vmid_mapping, @@ -555,5 +565,6 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .clear_address_watch = kgd_gfx_v9_4_3_clear_address_watch, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, - .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell, + .ptl_ctrl = kgd_v9_4_3_ptl_ctrl }; diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 6df5afb242ae..44e225e097d0 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -334,6 +334,11 @@ struct kfd2kgd_calls { uint32_t inst, unsigned int utimeout); uint32_t (*hqd_sdma_get_doorbell)(struct amdgpu_device *adev, int engine, int queue); + uint32_t (*ptl_ctrl)(struct amdgpu_device *adev, + uint32_t cmd, + uint32_t *ptl_state, + enum amdgpu_ptl_fmt *fmt1, + enum amdgpu_ptl_fmt *fmt2); }; #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ From aa86e750d0ff79c179772b9d3a95375c02a7d191 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 9 Feb 2026 00:42:05 +0800 Subject: [PATCH 06/71] Documentation/amdgpu: Add documentation for Peak Tops Limiter (PTL) sysfs interface The PTL (Peak Tops Limiter) feature exposes per-GPU sysfs files under /sys/class/drm/cardX/device/ptl/ to allow users to enable or disable PTL, configure preferred data formats, and query supported formats. The usage of these sysfs files is not always obvious, so add documentation to describe their purpose and provide concrete usage examples. V3 changes: * format show will display preferred formats instead of N/A (Alex) Signed-off-by: Perry Yuan Suggested-by: Alex Deucher Reviewed-by: Yifan Zhang Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- Documentation/gpu/amdgpu/index.rst | 1 + Documentation/gpu/amdgpu/ptl.rst | 94 ++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/gpu/amdgpu/ptl.rst diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst index 8732084186a4..b2ab182236ef 100644 --- a/Documentation/gpu/amdgpu/index.rst +++ b/Documentation/gpu/amdgpu/index.rst @@ -23,3 +23,4 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures. debugfs process-isolation amdgpu-glossary + ptl diff --git a/Documentation/gpu/amdgpu/ptl.rst b/Documentation/gpu/amdgpu/ptl.rst new file mode 100644 index 000000000000..c7f16dea7954 --- /dev/null +++ b/Documentation/gpu/amdgpu/ptl.rst @@ -0,0 +1,94 @@ +======================================= +Peak Tops Limiter (PTL) sysfs Interface +======================================= + +Overview +-------- +The Peak Tops Limiter (PTL) sysfs interface enables users to control and +configure the PTL feature for each GPU individually. All PTL-related +sysfs files are located under `/sys/class/drm/cardX/device/ptl/`, where +`X` is the GPU index. Through these files, users can enable or disable +PTL, set preferred data formats, and query supported formats for each GPU. + +PTL sysfs files +---------------- +The following files are available under `/sys/class/drm/cardX/device/ptl/`: + +- `ptl_enable` +- `ptl_format` +- `ptl_supported_formats` + +PTL Enable/Disable +------------------ +File: `ptl_enable` +Type: Read/Write (rw) + +Read: Returns the current PTL status as a string: `enabled` if PTL +is active, or `disabled` if inactive. + +Write: + +- Write `1` or `enabled` to enable PTL +- Write `0` or `disabled` to disable PTL + +Examples:: + + # Query PTL status + cat /sys/class/drm/card1/device/ptl/ptl_enable + # Output: enabled + + # Enable PTL + sudo bash -c "echo 1 > /sys/class/drm/card1/device/ptl/ptl_enable" + + # Disable PTL + sudo bash -c "echo 0 > /sys/class/drm/card1/device/ptl/ptl_enable" + +PTL Format (Preferred Data Formats) +----------------------------------- +File: `ptl_format` +Type: Read/Write (rw) + +Read: Returns the two preferred formats, e.g. `I8,F32`. + +Write: Accepts two formats separated by a comma, e.g. `I8,F32`. + +- Both formats must be supported and different. +- If an invalid format is provided (not supported, or both formats are the + same), the driver will return "write error: Invalid argument". + +Examples:: + + # Query PTL formats + cat /sys/class/drm/card1/device/ptl/ptl_format + # Output: I8,F32 + + # Set PTL formats + sudo bash -c "echo I8,F32 > /sys/class/drm/card1/device/ptl/ptl_format" + +Supported Formats +----------------- +File: `ptl_supported_formats` +Type: Read-only (r) + +Read: Returns a comma-separated list of supported formats, e.g. +`I8,F16,BF16,F32,F64`. + +Example:: + + # Check supported formats + cat /sys/class/drm/card1/device/ptl/ptl_supported_formats + # Output: I8,F16,BF16,F32,F64 + +Behavioral Notes +---------------- +- PTL formats can only be set when PTL is enabled. +- If PTL is disabled, `ptl_format` returns `N/A`. +- Only two formats can be set at a time, and they must be from the supported set and different.. +- All commands support per-GPU targeting. +- Root permission is required to enable/disable PTL or change formats. +- If the hardware does not support PTL, the PTL sysfs directory will not + be created. + +Implementation +-------------- +The PTL sysfs nodes are implemented in `drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c`. From d51a0439358d4eacd8beb39df619998d8340d232 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 9 Feb 2026 00:42:06 +0800 Subject: [PATCH 07/71] drm/amdgpu: add sysfs for Peak Tops Limiter (PTL) Add per-GPU sysfs files under /sys/class/drm/cardX/device/ptl to control the Peak Tops Limiter (PTL) feature. Exposes ptl_enable (enable/disable PTL), ptl_format (set/query preferred formats), and ptl_supported_formats (list supported formats) Example usage ------------- Query PTL status: `cat /sys/class/drm/card1/device/ptl/ptl_enable` Enable PTL: `sudo bash -c "echo 1 > /sys/class/drm/card1/device/ptl/ptl_enable"` Disable PTL: `sudo bash -c "echo 0 > /sys/class/drm/card1/device/ptl/ptl_enable"` Set PTL preferred formats: `sudo bash -c "echo I8,F32 > /sys/class/drm/card1/device/ptl/ptl_format"` Query supported formats: `cat /sys/class/drm/card1/device/ptl/ptl_supported_formats` v3 changes: * move N/A to previous format in format show(Alex) * fix format check for format store(Alex) * drop the ptl declarations into amdgpu_ptl.h(Alex) v2 changes: * add usage commands in commit info (Alex) * move amdgpu_ptl_fmt into kgd_kfd_interface.h (Alex) Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 194 +++++++++++++++++++++ drivers/gpu/drm/amd/include/amdgpu_ptl.h | 4 + 3 files changed, 200 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index d91bf647757f..34f933350ccf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3647,6 +3647,7 @@ static int amdgpu_device_sys_interface_init(struct amdgpu_device *adev) amdgpu_reg_state_sysfs_init(adev); amdgpu_xcp_sysfs_init(adev); amdgpu_uma_sysfs_init(adev); + amdgpu_ptl_sysfs_init(adev); return r; } @@ -3663,6 +3664,7 @@ static void amdgpu_device_sys_interface_fini(struct amdgpu_device *adev) amdgpu_reg_state_sysfs_fini(adev); amdgpu_xcp_sysfs_fini(adev); amdgpu_uma_sysfs_fini(adev); + amdgpu_ptl_sysfs_fini(adev); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 0734ddaf6388..82c96f578a82 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -52,6 +52,15 @@ static int psp_load_smu_fw(struct psp_context *psp); static int psp_rap_terminate(struct psp_context *psp); static int psp_securedisplay_terminate(struct psp_context *psp); +static const char * const amdgpu_ptl_fmt_str[] = { + [AMDGPU_PTL_FMT_I8] = "I8", + [AMDGPU_PTL_FMT_F16] = "F16", + [AMDGPU_PTL_FMT_BF16] = "BF16", + [AMDGPU_PTL_FMT_F32] = "F32", + [AMDGPU_PTL_FMT_F64] = "F64", + [AMDGPU_PTL_FMT_INVALID] = "INVALID", +}; + static int psp_ring_init(struct psp_context *psp, enum psp_ring_type ring_type) { @@ -1312,6 +1321,166 @@ int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); } +static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) +{ + int i; + + for (i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { + if (!strcmp(str, amdgpu_ptl_fmt_str[i])) + return (enum amdgpu_ptl_fmt)i; + } + + return AMDGPU_PTL_FMT_INVALID; +} + +static ssize_t ptl_supported_formats_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t len = 0; + + for (int i = 0; i < AMDGPU_PTL_FMT_INVALID; ++i) { + const char *fmt = amdgpu_ptl_fmt_str[i]; + + len += sysfs_emit_at(buf, len, "%s%s", + fmt ? fmt : "UNKNOWN", + (i < AMDGPU_PTL_FMT_INVALID - 1) ? "," : "\n"); + } + + return len; +} + +static ssize_t ptl_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct amdgpu_ptl *ptl = &adev->psp.ptl; + uint32_t ptl_state, fmt1, fmt2; + int ret; + bool enable; + + mutex_lock(&ptl->mutex); + if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { + enable = true; + } else if (sysfs_streq(buf, "disabled") || sysfs_streq(buf, "0")) { + enable = false; + } else { + mutex_unlock(&ptl->mutex); + return -EINVAL; + } + + fmt1 = ptl->fmt1; + fmt2 = ptl->fmt2; + ptl_state = enable ? 1 : 0; + + ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); + if (ret) { + dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); + mutex_unlock(&ptl->mutex); + return ret; + } + + mutex_unlock(&ptl->mutex); + return count; +} + +static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct amdgpu_ptl *ptl = &adev->psp.ptl; + + return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled"); +} + +static ssize_t ptl_format_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + char fmt1_str[8], fmt2_str[8]; + enum amdgpu_ptl_fmt fmt1_enum, fmt2_enum; + struct amdgpu_ptl *ptl = &adev->psp.ptl; + uint32_t ptl_state, fmt1, fmt2; + int ret; + + /* Only allow format update when PTL is enabled */ + if (!ptl->enabled) + return -EPERM; + + mutex_lock(&ptl->mutex); + /* Parse input, expecting "FMT1,FMT2" */ + if (sscanf(buf, "%7[^,],%7s", fmt1_str, fmt2_str) != 2) { + mutex_unlock(&ptl->mutex); + return -EINVAL; + } + + fmt1_enum = str_to_ptl_fmt(fmt1_str); + fmt2_enum = str_to_ptl_fmt(fmt2_str); + + if (fmt1_enum >= AMDGPU_PTL_FMT_INVALID || + fmt2_enum >= AMDGPU_PTL_FMT_INVALID || + fmt1_enum == fmt2_enum) { + mutex_unlock(&ptl->mutex); + return -EINVAL; + } + + ptl_state = ptl->enabled; + fmt1 = fmt1_enum; + fmt2 = fmt2_enum; + ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); + if (ret) { + dev_err(adev->dev, "Failed to update PTL err = %d\n", ret); + mutex_unlock(&ptl->mutex); + return ret; + } + mutex_unlock(&ptl->mutex); + + return count; +} + +static ssize_t ptl_format_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct psp_context *psp = &adev->psp; + + return sysfs_emit(buf, "%s,%s\n", + amdgpu_ptl_fmt_str[psp->ptl.fmt1], + amdgpu_ptl_fmt_str[psp->ptl.fmt2]); +} + +static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *attr, int idx) +{ + struct device *dev = kobj_to_dev(kobj); + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + + /* Only show PTL sysfs files if PTL hardware is supported */ + if (!adev->psp.ptl.hw_supported) + return 0; + + return attr->mode; +} + +int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) +{ + if (!adev->psp.ptl.hw_supported) + return 0; + + return sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); +} + +void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) +{ + if (!adev->psp.ptl.hw_supported) + return; + + sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); +} + int psp_spatial_partition(struct psp_context *psp, int mode) { struct psp_gfx_cmd_resp *cmd; @@ -4318,6 +4487,31 @@ void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size static DEVICE_ATTR(usbc_pd_fw, 0644, psp_usbc_pd_fw_sysfs_read, psp_usbc_pd_fw_sysfs_write); +/** + * DOC: PTL sysfs attributes + * These sysfs files under /sys/class/drm/cardX/device/ptl allow users to enable or disable + * the Peak Tops Limiter (PTL), configure preferred PTL data formats, and query supported + * formats for each GPU. + */ +static DEVICE_ATTR(ptl_enable, 0644, + ptl_enable_show, ptl_enable_store); +static DEVICE_ATTR(ptl_format, 0644, + ptl_format_show, ptl_format_store); +static DEVICE_ATTR(ptl_supported_formats, 0444, + ptl_supported_formats_show, NULL); + +static struct attribute *ptl_attrs[] = { + &dev_attr_ptl_enable.attr, + &dev_attr_ptl_format.attr, + &dev_attr_ptl_supported_formats.attr, + NULL, +}; + +const struct attribute_group amdgpu_ptl_attr_group = { + .name = "ptl", + .attrs = ptl_attrs, + .is_visible = amdgpu_ptl_is_visible, +}; int is_psp_fw_valid(struct psp_bin_desc bin) { diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h index 17e803f4caf8..ffed443a14ae 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_ptl.h +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -47,4 +47,8 @@ int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, enum amdgpu_ptl_fmt *fmt1, enum amdgpu_ptl_fmt *fmt2); +int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev); +void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev); + +extern const struct attribute_group amdgpu_ptl_attr_group; #endif /* __AMDGPU_PTL_H__ */ From dd61e27535a6f5cfb32a847b282d2e3d5aebf46f Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 9 Feb 2026 00:42:07 +0800 Subject: [PATCH 08/71] drm/amdkfd: Add PTL control IOCTL Option and unify refcount logic Introduce a new IOCTL option to allow userspace explicit control over the Peak Tops Limiter (PTL) state for profiling Link: https://github.com/ROCm/rocm-systems/tree/develop/projects/rocprofiler-sdk Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 102 +++++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 8 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 + drivers/gpu/drm/amd/include/amdgpu_ptl.h | 2 + include/uapi/linux/kfd_ioctl.h | 7 ++ 6 files changed, 125 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 467a3dbe1bfa..aab6a4de54fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2400,6 +2400,8 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool ena ptl->hw_supported = true; + atomic_set(&ptl->disable_ref, 0); + return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index fc00d0418684..883de31df04d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1774,6 +1774,104 @@ static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) } #endif +static int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) +{ + struct amdgpu_device *adev = pdd->dev->adev; + struct amdgpu_ptl *ptl = &adev->psp.ptl; + enum amdgpu_ptl_fmt pref_format1 = ptl->fmt1; + enum amdgpu_ptl_fmt pref_format2 = ptl->fmt2; + uint32_t ptl_state = enable ? 1 : 0; + int ret; + + if (!ptl->hw_supported) + return -EOPNOTSUPP; + + if (!pdd->dev->kfd2kgd || !pdd->dev->kfd2kgd->ptl_ctrl) + return -EOPNOTSUPP; + + ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, + &ptl_state, + &pref_format1, + &pref_format2); + return ret; +} + +int kfd_ptl_disable_request(struct kfd_process_device *pdd, + struct kfd_process *p) +{ + struct amdgpu_device *adev = pdd->dev->adev; + struct amdgpu_ptl *ptl = &adev->psp.ptl; + int ret = 0; + + mutex_lock(&ptl->mutex); + + if (pdd->ptl_disable_req) + goto out; + + if (atomic_inc_return(&ptl->disable_ref) == 1) { + ret = kfd_ptl_control(pdd, false); + if (ret) { + atomic_dec(&ptl->disable_ref); + dev_warn(pdd->dev->adev->dev, + "failed to disable PTL\n"); + goto out; + } + } + pdd->ptl_disable_req = true; + +out: + mutex_unlock(&ptl->mutex); + return ret; +} + +int kfd_ptl_disable_release(struct kfd_process_device *pdd, + struct kfd_process *p) +{ + struct amdgpu_device *adev = pdd->dev->adev; + struct amdgpu_ptl *ptl = &adev->psp.ptl; + int ret = 0; + + mutex_lock(&ptl->mutex); + + if (!pdd->ptl_disable_req) + goto out; + + if (atomic_dec_return(&ptl->disable_ref) == 0) { + ret = kfd_ptl_control(pdd, true); + if (ret) { + atomic_inc(&ptl->disable_ref); + dev_warn(adev->dev, "Failed to enable PTL on release: %d\n", ret); + goto out; + } + } + pdd->ptl_disable_req = false; + +out: + mutex_unlock(&ptl->mutex); + return ret; +} + +static int kfd_profiler_ptl_control(struct kfd_process *p, + struct kfd_ioctl_ptl_control *args) +{ + struct kfd_process_device *pdd; + int ret; + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + mutex_unlock(&p->mutex); + + if (!pdd || !pdd->dev || !pdd->dev->kfd) + return -EINVAL; + + if (args->enable == 0) + ret = kfd_ptl_disable_request(pdd, p); + else + ret = kfd_ptl_disable_release(pdd, p); + + return ret; +} + static int criu_checkpoint_process(struct kfd_process *p, uint8_t __user *user_priv_data, uint64_t *priv_offset) @@ -3242,6 +3340,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, if (!kfd->profiler_process) { kfd->profiler_process = p; status = 0; + kfd_ptl_disable_request(pdd, p); } else if (kfd->profiler_process == p) { status = -EALREADY; } else { @@ -3250,6 +3349,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, } else if (op == 0 && kfd->profiler_process == p) { kfd->profiler_process = NULL; status = 0; + kfd_ptl_disable_release(pdd, p); } mutex_unlock(&kfd->profiler_lock); @@ -3292,6 +3392,8 @@ static int kfd_ioctl_profiler(struct file *filep, struct kfd_process *p, void *d return 0; case KFD_IOC_PROFILER_PMC: return kfd_profiler_pmc(p, &args->pmc); + case KFD_IOC_PROFILER_PTL_CONTROL: + return kfd_profiler_ptl_control(p, &args->ptl); } return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 903386e0740b..482bcfa10f82 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -872,6 +872,8 @@ struct kfd_process_device { bool has_reset_queue; u32 pasid; + /* Indicates this process has requested PTL stay disabled */ + bool ptl_disable_req; }; #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd) @@ -1603,6 +1605,12 @@ static inline bool kfd_is_first_node(struct kfd_node *node) return (node == node->kfd->nodes[0]); } +/* PTL support */ +int kfd_ptl_disable_request(struct kfd_process_device *pdd, + struct kfd_process *p); +int kfd_ptl_disable_release(struct kfd_process_device *pdd, + struct kfd_process *p); + /* Debugfs */ #if defined(CONFIG_DEBUG_FS) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 1a8cb512dfe3..368283d53077 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1128,6 +1128,10 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pr_debug("Releasing pdd (topology id %d, for pid %d)\n", pdd->dev->id, p->lead_thread->pid); kfd_process_profiler_release(p, pdd); + + if (pdd->ptl_disable_req) + kfd_ptl_disable_release(pdd, p); + kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h index ffed443a14ae..9e63a9a9680a 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_ptl.h +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -39,6 +39,8 @@ struct amdgpu_ptl { enum amdgpu_ptl_fmt fmt2; bool enabled; bool hw_supported; + /* PTL disable reference counting */ + atomic_t disable_ref; struct mutex mutex; }; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index cc3ed0765c83..1a94d512df35 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1562,6 +1562,7 @@ struct kfd_ioctl_dbg_trap_args { enum kfd_profiler_ops { KFD_IOC_PROFILER_PMC = 0, KFD_IOC_PROFILER_VERSION = 2, + KFD_IOC_PROFILER_PTL_CONTROL = 3, }; /** @@ -1573,10 +1574,16 @@ struct kfd_ioctl_pmc_settings { __u32 perfcount_enable; /* Force Perfcount Enable for queues on GPU */ }; +struct kfd_ioctl_ptl_control { + __u32 gpu_id; /* user_gpu_id */ + __u32 enable; /* set 1 to enable PTL, set 0 to disable PTL */ +}; + struct kfd_ioctl_profiler_args { __u32 op; /* kfd_profiler_op */ union { struct kfd_ioctl_pmc_settings pmc; + struct kfd_ioctl_ptl_control ptl; __u32 version; /* KFD_IOC_PROFILER_VERSION_NUM */ }; }; From 022f071db5eb4434824e52790542e648c9bcd77d Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 9 Feb 2026 00:42:08 +0800 Subject: [PATCH 09/71] drm/amdkfd: suspend scheduler during PTL re-enabling Stop the scheduler before releasing the PTL disable request to ensure the GPU is quiescent during the PTL state transition. This prevents potential queue preemption failures and GPU resets caused by modifying PTL state while waves are executing v1->v2: only stop/start the scheduler when the PTL state actually needs to transition(Yifan) Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 30 ++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 883de31df04d..bada73b48899 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1789,10 +1789,17 @@ static int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) if (!pdd->dev->kfd2kgd || !pdd->dev->kfd2kgd->ptl_ctrl) return -EOPNOTSUPP; + if (adev->kfd.init_complete) + amdgpu_amdkfd_stop_sched(adev, pdd->dev->node_id); + ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &pref_format1, &pref_format2); + + if (adev->kfd.init_complete) + amdgpu_amdkfd_start_sched(adev, pdd->dev->node_id); + return ret; } @@ -3322,6 +3329,7 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, struct kfd_process_device *pdd; struct kfd_dev *kfd; int status = -EINVAL; + struct amdgpu_ptl *ptl; if (!p) return -EINVAL; @@ -3334,13 +3342,22 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, return -EINVAL; kfd = pdd->dev->kfd; + ptl = &pdd->dev->adev->psp.ptl; mutex_lock(&kfd->profiler_lock); if (op == 1) { if (!kfd->profiler_process) { kfd->profiler_process = p; status = 0; - kfd_ptl_disable_request(pdd, p); + mutex_unlock(&kfd->profiler_lock); + if (ptl->hw_supported) { + status = kfd_ptl_disable_request(pdd, p); + if (status != 0) + dev_err(kfd_device, + "Failed to lock device %d for profiling, error %d\n", + gpu_id, status); + } + return status; } else if (kfd->profiler_process == p) { status = -EALREADY; } else { @@ -3349,7 +3366,16 @@ static inline uint32_t profile_lock_device(struct kfd_process *p, } else if (op == 0 && kfd->profiler_process == p) { kfd->profiler_process = NULL; status = 0; - kfd_ptl_disable_release(pdd, p); + mutex_unlock(&kfd->profiler_lock); + + if (ptl->hw_supported) { + status = kfd_ptl_disable_release(pdd, p); + if (status) + dev_err(kfd_device, + "Failed to unlock device %d for profiling, error %d\n", + gpu_id, status); + } + return status; } mutex_unlock(&kfd->profiler_lock); From 950688d2417085f30feb6ec48c85eeda53841ea2 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 9 Feb 2026 00:42:09 +0800 Subject: [PATCH 10/71] drm/amdgpu: Track PTL disable requests by source Use a bitmap to track PTL disable requests from sysfs and profiler. PTL is only re-enabled once all sources have released their disable requests, avoiding premature enablement. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 26 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 3 +++ drivers/gpu/drm/amd/include/amdgpu_ptl.h | 6 ++++++ 4 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 82c96f578a82..78a9ce0eb60e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1318,6 +1318,21 @@ int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, ptl->fmt2 == ptl_fmt2) return 0; + /* If enabling PTL, check disable bitmap */ + if (req_code == PSP_PTL_PERF_MON_SET && *ptl_state == 1) { + if (!bitmap_empty(ptl->disable_bitmap, + AMDGPU_PTL_DISABLE_MAX)) { + dev_dbg(adev->dev, + "PTL enable blocked: SYSFS=%d, PROFILER=%d (ref=%d)\n", + test_bit(AMDGPU_PTL_DISABLE_SYSFS, + ptl->disable_bitmap), + test_bit(AMDGPU_PTL_DISABLE_PROFILER, + ptl->disable_bitmap), + atomic_read(&ptl->disable_ref)); + return 0; + } + } + return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); } @@ -1359,6 +1374,7 @@ static ssize_t ptl_enable_store(struct device *dev, uint32_t ptl_state, fmt1, fmt2; int ret; bool enable; + bool bit_changed = false; mutex_lock(&ptl->mutex); if (sysfs_streq(buf, "enabled") || sysfs_streq(buf, "1")) { @@ -1374,14 +1390,24 @@ static ssize_t ptl_enable_store(struct device *dev, fmt2 = ptl->fmt2; ptl_state = enable ? 1 : 0; + if (enable) + bit_changed = test_and_clear_bit(AMDGPU_PTL_DISABLE_SYSFS, + ptl->disable_bitmap); + ret = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); if (ret) { dev_err(adev->dev, "Failed to set PTL err = %d\n", ret); + if (enable && bit_changed) + set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); mutex_unlock(&ptl->mutex); return ret; } + if (!enable) + set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); + mutex_unlock(&ptl->mutex); + return count; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 979650182431..575823f26849 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -31,6 +31,7 @@ #include "ta_ras_if.h" #include "ta_rap_if.h" #include "ta_secureDisplay_if.h" +#include #include "amdgpu_ptl.h" #define PSP_FENCE_BUFFER_SIZE 0x1000 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index bada73b48899..5bea583732cb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1824,6 +1824,7 @@ int kfd_ptl_disable_request(struct kfd_process_device *pdd, goto out; } } + set_bit(AMDGPU_PTL_DISABLE_PROFILER, ptl->disable_bitmap); pdd->ptl_disable_req = true; out: @@ -1844,9 +1845,11 @@ int kfd_ptl_disable_release(struct kfd_process_device *pdd, goto out; if (atomic_dec_return(&ptl->disable_ref) == 0) { + clear_bit(AMDGPU_PTL_DISABLE_PROFILER, ptl->disable_bitmap); ret = kfd_ptl_control(pdd, true); if (ret) { atomic_inc(&ptl->disable_ref); + set_bit(AMDGPU_PTL_DISABLE_PROFILER, ptl->disable_bitmap); dev_warn(adev->dev, "Failed to enable PTL on release: %d\n", ret); goto out; } diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h index 9e63a9a9680a..568b6944e1ad 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_ptl.h +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -34,6 +34,11 @@ enum amdgpu_ptl_fmt { AMDGPU_PTL_FMT_INVALID = 7, }; +enum amdgpu_ptl_disable_source { + AMDGPU_PTL_DISABLE_SYSFS = 0, + AMDGPU_PTL_DISABLE_PROFILER, + AMDGPU_PTL_DISABLE_MAX, +}; struct amdgpu_ptl { enum amdgpu_ptl_fmt fmt1; enum amdgpu_ptl_fmt fmt2; @@ -42,6 +47,7 @@ struct amdgpu_ptl { /* PTL disable reference counting */ atomic_t disable_ref; struct mutex mutex; + DECLARE_BITMAP(disable_bitmap, AMDGPU_PTL_DISABLE_MAX); }; int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, From b6dc8f753670e3833150482c1b7640b1fd3b30a3 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 9 Feb 2026 00:42:10 +0800 Subject: [PATCH 11/71] drm/amdgpu: add amdgpu.ptl module parameter for PTL control Add a new kernel module parameter 'amdgpu.ptl' to allow users to enable or disable PTL feature at driver loading time. Parameter values: *) 0 or -1: disable PTL (default) *) 1: enable PTL *) 2: permanently disable PTL Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 13 +++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 12 ++++++++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 28 +++++++++++++++++++++++- drivers/gpu/drm/amd/include/amdgpu_ptl.h | 1 + 5 files changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 25b80d4b097f..80b18bbd7f3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -267,6 +267,7 @@ extern int amdgpu_rebar; extern int amdgpu_wbrf; extern int amdgpu_user_queue; +extern int amdgpu_ptl; extern uint amdgpu_hdmi_hpd_debounce_delay_ms; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 60debd543e44..99688391e70b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -246,6 +246,7 @@ int amdgpu_umsch_mm_fwlog; int amdgpu_rebar = -1; /* auto */ int amdgpu_user_queue = -1; uint amdgpu_hdmi_hpd_debounce_delay_ms; +int amdgpu_ptl = -1; /* auto */ DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, "DRM_UT_CORE", @@ -1112,6 +1113,18 @@ module_param_named(user_queue, amdgpu_user_queue, int, 0444); MODULE_PARM_DESC(hdmi_hpd_debounce_delay_ms, "HDMI HPD disconnect debounce delay in milliseconds (0 to disable (by default), 1500 is common)"); module_param_named(hdmi_hpd_debounce_delay_ms, amdgpu_hdmi_hpd_debounce_delay_ms, uint, 0644); +/** + * DOC: ptl (int) + * Enable PTL feature at boot time. Possible values: + * + * - -1 = auto (ASIC specific default) + * - 0 = disable PTL (default) + * - 1 = enable PTL + * - 2 = permanently disable PTL (cannot be re-enabled at runtime) + */ +MODULE_PARM_DESC(ptl, "Enable PTL (-1 = auto, 0 = disable (default), 1 = enable, 2 = permanently disable)"); +module_param_named(ptl, amdgpu_ptl, int, 0444); + /* These devices are not supported by amdgpu. * They are supported by the mach64, r128, radeon drivers */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 78a9ce0eb60e..9c588323e9b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1300,6 +1300,9 @@ int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, psp = &adev->psp; ptl = &psp->ptl; + if (ptl->permanently_disabled && *ptl_state == 1) + return 0; + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 4) || psp->sos.fw_version < 0x0036081a) return -EOPNOTSUPP; @@ -1386,6 +1389,12 @@ static ssize_t ptl_enable_store(struct device *dev, return -EINVAL; } + /* Block enable when permanently disabled */ + if (ptl->permanently_disabled) { + mutex_unlock(&ptl->mutex); + return -EPERM; + } + fmt1 = ptl->fmt1; fmt2 = ptl->fmt2; ptl_state = enable ? 1 : 0; @@ -1417,6 +1426,9 @@ static ssize_t ptl_enable_show(struct device *dev, struct device_attribute *attr struct amdgpu_device *adev = drm_to_adev(ddev); struct amdgpu_ptl *ptl = &adev->psp.ptl; + if (ptl->permanently_disabled) + return sysfs_emit(buf, "permanently disabled\n"); + return sysfs_emit(buf, "%s\n", ptl->enabled ? "enabled" : "disabled"); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index aab6a4de54fa..b59e944f7df0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2405,6 +2405,32 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool ena return 0; } +static int gfx_v9_4_3_ptl_hw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ptl *ptl = &adev->psp.ptl; + bool enable; + + switch (amdgpu_ptl) { + case 1: + enable = true; + break; + case 2: + /* Permanently disabled - cannot be re-enabled */ + enable = false; + ptl->permanently_disabled = true; + break; + case -1: + case 0: + default: + enable = false; + break; + } + + gfx_v9_4_3_perf_monitor_ptl_init(adev, enable ? 1 : 0); + + return 0; +} + static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -2587,7 +2613,7 @@ static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) adev->gfx.ras->enable_watchdog_timer) adev->gfx.ras->enable_watchdog_timer(adev); - gfx_v9_4_3_perf_monitor_ptl_init(adev, true); + gfx_v9_4_3_ptl_hw_init(adev); return 0; } diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h index 568b6944e1ad..dc74119d91c8 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_ptl.h +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -44,6 +44,7 @@ struct amdgpu_ptl { enum amdgpu_ptl_fmt fmt2; bool enabled; bool hw_supported; + bool permanently_disabled; /* PTL disable reference counting */ atomic_t disable_ref; struct mutex mutex; From d31098cb31ef6052ae1ac51e7e78bfcbe7ac90ea Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 9 Feb 2026 00:42:11 +0800 Subject: [PATCH 12/71] drm/amdgpu: add new data types F8 and Vector for PTL Add F8 and VECTOR to amdgpu_ptl_fmt and PSP format mapping. Update PTL format strings and GFX format enum to keep PSP/KFD in sync. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 ++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 9c588323e9b9..580e68f02bbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -58,6 +58,8 @@ static const char * const amdgpu_ptl_fmt_str[] = { [AMDGPU_PTL_FMT_BF16] = "BF16", [AMDGPU_PTL_FMT_F32] = "F32", [AMDGPU_PTL_FMT_F64] = "F64", + [AMDGPU_PTL_FMT_F8] = "F8", + [AMDGPU_PTL_FMT_VECTOR] = "VECTOR", [AMDGPU_PTL_FMT_INVALID] = "INVALID", }; @@ -1236,6 +1238,12 @@ static int psp_ptl_fmt_verify(struct psp_context *psp, enum amdgpu_ptl_fmt fmt, case AMDGPU_PTL_FMT_F64: *ptl_fmt = GFX_FTYPE_F64; break; + case AMDGPU_PTL_FMT_F8: + *ptl_fmt = GFX_FTYPE_F8; + break; + case AMDGPU_PTL_FMT_VECTOR: + *ptl_fmt = GFX_FTYPE_VECTOR; + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 575823f26849..4197179a7701 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -371,6 +371,8 @@ enum psp_ptl_format_type { GFX_FTYPE_BF16 = 0x00000002, GFX_FTYPE_F32 = 0x00000003, GFX_FTYPE_F64 = 0x00000004, + GFX_FTYPE_F8 = 0x00000005, + GFX_FTYPE_VECTOR = 0x00000006, GFX_FTYPE_INVALID = 0xFFFFFFFF, }; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index b59e944f7df0..ed087e915296 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2385,8 +2385,8 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool ena return -EOPNOTSUPP; if (!ptl->hw_supported) { - fmt1 = GFX_FTYPE_I8; - fmt2 = GFX_FTYPE_BF16; + fmt1 = GFX_FTYPE_VECTOR; + fmt2 = GFX_FTYPE_F8; } else { fmt1 = ptl->fmt1; fmt2 = ptl->fmt2; From 82cfe59ba4679647c776367dd6914c6310c1888e Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 9 Feb 2026 00:42:12 +0800 Subject: [PATCH 13/71] drm/amdgpu: Wait for GFX idle before PTL state transition Ensure GFX engine is idle before switching PTL state to prevent register access violations and CP hang. This addresses the race condition where in-flight GPU commands could conflict with PTL state changes. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 5bea583732cb..a719399bcdd5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1792,6 +1792,11 @@ static int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) if (adev->kfd.init_complete) amdgpu_amdkfd_stop_sched(adev, pdd->dev->node_id); + /* Wait for GFX to be idle before PTL operation */ + ret = amdgpu_device_ip_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GFX); + if (ret) + return -ETIMEDOUT; + ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &pref_format1, From c13ff096437c6d470edf754c78e0cb83d24505fa Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 10 Feb 2026 13:50:36 +0800 Subject: [PATCH 14/71] drm/amdgpu: check PSP response status in psp_ptl_invoke Add an explicit check on cmd->resp.status after psp_cmd_submit_buf() returns to ensure PTL state is only updated on actual success. Signed-off-by: Perry Yuan Reviewed-by: Lijo Lazar Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 580e68f02bbe..ad76074d54aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1270,6 +1270,18 @@ static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, if (ret) goto out; + /* + * Check response status explicitly to avoid + * updating cached PTL state with invalid data. + */ + if (cmd->resp.status) { + dev_err(psp->adev->dev, + "PTL command 0x%x failed, PSP response status: 0x%X\n", + req_code, cmd->resp.status); + ret = -EIO; + goto out; + } + /* Parse response */ switch (req_code) { case PSP_PTL_PERF_MON_QUERY: From caefb4bc93e45ec4702bc6cfec8b74b34c978e13 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 23 Feb 2026 23:20:50 +0800 Subject: [PATCH 15/71] drm/amdgpu: add SPI idle check for GC 9.4.4 in gfx_v9_4_3_is_idle() GC 9.4.4 uses SPI busy status for idle detection instead of GRBM GUI_ACTIVE. Add version check to use SPI_BUSY for 9.4.4 while keeping GRBM_STATUS GUI_ACTIVE check for other GC versions. v2: move this check into amdgpu_ptl_perf_monitor_ctrl(Lijo) Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 16 ++++++++++++++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 15 ++++++++++++--- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 ----- 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index ad76074d54aa..5f8f0026483b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1276,8 +1276,9 @@ static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, */ if (cmd->resp.status) { dev_err(psp->adev->dev, - "PTL command 0x%x failed, PSP response status: 0x%X\n", - req_code, cmd->resp.status); + "PTL command 0x%x failed, PSP response status: 0x%X fw resp=0x%X\n", + req_code, cmd->resp.status, + cmd->resp.uresp.perf_hw_info.resp); ret = -EIO; goto out; } @@ -1310,6 +1311,7 @@ int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, uint32_t ptl_fmt1, ptl_fmt2; struct psp_context *psp; struct amdgpu_ptl *ptl; + int ret; if (!adev || !ptl_state || !fmt1 || !fmt2) return -EINVAL; @@ -1356,6 +1358,16 @@ int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, } } + /* Wait for GFX engine idle before PTL state transition */ + if (req_code == PSP_PTL_PERF_MON_SET) { + ret = amdgpu_device_ip_wait_for_idle(adev, + AMD_IP_BLOCK_TYPE_GFX); + if (ret) { + dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); + return ret; + } + } + return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index ed087e915296..5781a3934b6e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2465,12 +2465,21 @@ static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; int i, num_xcc; + u32 gc_ip_version; num_xcc = NUM_XCC(adev->gfx.xcc_mask); + gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); + for (i = 0; i < num_xcc; i++) { - if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), - GRBM_STATUS, GUI_ACTIVE)) - return false; + if (gc_ip_version == IP_VERSION(9, 4, 4)) { + if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), + GRBM_STATUS, SPI_BUSY)) + return false; + } else { + if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), + GRBM_STATUS, GUI_ACTIVE)) + return false; + } } return true; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index a719399bcdd5..5bea583732cb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1792,11 +1792,6 @@ static int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) if (adev->kfd.init_complete) amdgpu_amdkfd_stop_sched(adev, pdd->dev->node_id); - /* Wait for GFX to be idle before PTL operation */ - ret = amdgpu_device_ip_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GFX); - if (ret) - return -ETIMEDOUT; - ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &pref_format1, From 1da21802df3a98d54159bba1d1b04d59f030b92a Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Thu, 26 Feb 2026 17:50:33 +0800 Subject: [PATCH 16/71] drm/amdgpu: Move KFD sched stop/start into PTL control path Move amdgpu_amdkfd_stop/start_sched calls from kfd_ptl_control() into amdgpu_ptl_perf_monitor_ctrl() so all PTL callers (KFD ioctl, sysfs, GFX init) get consistent scheduling management. Add amdgpu_amdkfd_stop/start_sched_all() wrappers to stop and restart KFD scheduling on all nodes without assuming node ID ordering. v3: * call start/stop for PTL Set Only v2: * move the stop/start sched function to amdgpu_ptl_perf_monitor_ctrl(Lijo) * add wrapper amdgpu_amdkfd_stop_sched_all and amdgpu_amdkfd_start_sched_all (Lijo) Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 12 ++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 10 ++++++++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 ------ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 16 ++++++++++++++++ 4 files changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 4fee011c2e26..2bf6a31c194d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -436,8 +436,10 @@ int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd); void kgd2kfd_unlock_kfd(struct kfd_dev *kfd); int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id); int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd); +int amdgpu_amdkfd_start_sched_all(struct amdgpu_device *adev); int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id); int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd); +int amdgpu_amdkfd_stop_sched_all(struct amdgpu_device *adev); bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, bool retry_fault); @@ -534,6 +536,11 @@ static inline int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd) return 0; } +static inline int amdgpu_amdkfd_start_sched_all(struct amdgpu_device *adev) +{ + return 0; +} + static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) { return 0; @@ -544,6 +551,11 @@ static inline int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) return 0; } +static inline int amdgpu_amdkfd_stop_sched_all(struct amdgpu_device *adev) +{ + return 0; +} + static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) { return false; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 5f8f0026483b..a1db694063b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1358,17 +1358,23 @@ int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, } } - /* Wait for GFX engine idle before PTL state transition */ if (req_code == PSP_PTL_PERF_MON_SET) { + amdgpu_amdkfd_stop_sched_all(adev); + /* Wait for GFX engine idle before PTL state transition */ ret = amdgpu_device_ip_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GFX); if (ret) { + amdgpu_amdkfd_start_sched_all(adev); dev_err(adev->dev, "GFX not idle before PTL operation (%d)\n", ret); return ret; } + ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); + amdgpu_amdkfd_start_sched_all(adev); + } else { + ret = psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); } - return psp_ptl_invoke(psp, req_code, ptl_state, &ptl_fmt1, &ptl_fmt2); + return ret; } static enum amdgpu_ptl_fmt str_to_ptl_fmt(const char *str) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 5bea583732cb..04ae3cb3a65c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1789,17 +1789,11 @@ static int kfd_ptl_control(struct kfd_process_device *pdd, bool enable) if (!pdd->dev->kfd2kgd || !pdd->dev->kfd2kgd->ptl_ctrl) return -EOPNOTSUPP; - if (adev->kfd.init_complete) - amdgpu_amdkfd_stop_sched(adev, pdd->dev->node_id); - ret = pdd->dev->kfd2kgd->ptl_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &pref_format1, &pref_format2); - if (adev->kfd.init_complete) - amdgpu_amdkfd_start_sched(adev, pdd->dev->node_id); - return ret; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index d649d8603e28..c2c59781feee 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -1651,6 +1651,22 @@ int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) return 0; } +int amdgpu_amdkfd_stop_sched_all(struct amdgpu_device *adev) +{ + if (!adev->kfd.init_complete) + return 0; + + return kgd2kfd_stop_sched_all_nodes(adev->kfd.dev); +} + +int amdgpu_amdkfd_start_sched_all(struct amdgpu_device *adev) +{ + if (!adev->kfd.init_complete) + return 0; + + return kgd2kfd_start_sched_all_nodes(adev->kfd.dev); +} + bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) { struct kfd_node *node; From e16d0d16728179fb8eaad93c8a12825eb6746eca Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 3 Mar 2026 16:37:11 +0800 Subject: [PATCH 17/71] drm/amdgpu: create PTL sysfs after XGMI reset-on-init restore Create PTL sysfs in xgmi_reset_on_init restore path for MINIMAL_XGMI Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 22 +++++++++++++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 1 + drivers/gpu/drm/amd/include/amdgpu_ptl.h | 1 + 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index a1db694063b1..aec284c6b6d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1543,18 +1543,34 @@ static umode_t amdgpu_ptl_is_visible(struct kobject *kobj, struct attribute *att int amdgpu_ptl_sysfs_init(struct amdgpu_device *adev) { - if (!adev->psp.ptl.hw_supported) + struct amdgpu_ptl *ptl = &adev->psp.ptl; + int ret; + + if (!ptl->hw_supported) return 0; - return sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); + if (ptl->ptl_sysfs_created) + return 0; + + ret = sysfs_create_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); + if (!ret) + ptl->ptl_sysfs_created = true; + + return ret; } void amdgpu_ptl_sysfs_fini(struct amdgpu_device *adev) { - if (!adev->psp.ptl.hw_supported) + struct amdgpu_ptl *ptl = &adev->psp.ptl; + + if (!ptl->hw_supported) + return; + + if (!ptl->ptl_sysfs_created) return; sysfs_remove_group(&adev->dev->kobj, &amdgpu_ptl_attr_group); + ptl->ptl_sysfs_created = false; } int psp_spatial_partition(struct psp_context *psp, int mode) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index 1b982b803e6f..428c3cbc4a40 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c @@ -90,6 +90,7 @@ static int amdgpu_reset_xgmi_reset_on_init_restore_hwctxt( kgd2kfd_init_zone_device(tmp_adev); amdgpu_amdkfd_device_init(tmp_adev); amdgpu_amdkfd_drm_client_create(tmp_adev); + amdgpu_ptl_sysfs_init(tmp_adev); } } diff --git a/drivers/gpu/drm/amd/include/amdgpu_ptl.h b/drivers/gpu/drm/amd/include/amdgpu_ptl.h index dc74119d91c8..154b8da3bfa9 100644 --- a/drivers/gpu/drm/amd/include/amdgpu_ptl.h +++ b/drivers/gpu/drm/amd/include/amdgpu_ptl.h @@ -49,6 +49,7 @@ struct amdgpu_ptl { atomic_t disable_ref; struct mutex mutex; DECLARE_BITMAP(disable_bitmap, AMDGPU_PTL_DISABLE_MAX); + bool ptl_sysfs_created; }; int amdgpu_ptl_perf_monitor_ctrl(struct amdgpu_device *adev, u32 req_code, From d2b8d178e9b9b02d46d5c66119ab1b0a43a0115b Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 3 Mar 2026 16:39:35 +0800 Subject: [PATCH 18/71] drm/amdkfd: fix unhalt_cpsch warning during module unload Downgrade unhalt_cpsch warning to dev_dbg when sched is already stopped Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index c64a1e19fa3f..5043b74b56ae 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1934,10 +1934,11 @@ static int halt_cpsch(struct device_queue_manager *dqm) static int unhalt_cpsch(struct device_queue_manager *dqm) { int ret = 0; + struct amdgpu_device *adev = dqm->dev->adev; dqm_lock(dqm); if (!dqm->sched_running || !dqm->sched_halt) { - WARN_ONCE(!dqm->sched_halt, "Scheduling is not on halt.\n"); + dev_dbg(adev->dev, "Scheduling is not on halt.\n"); dqm_unlock(dqm); return 0; } From 3311f0db4d44804751ff635c4443b2330da17781 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 3 Mar 2026 16:42:45 +0800 Subject: [PATCH 19/71] drm/amdgpu: only set PTL SYSFS disable bit when PTL is disabled Only set the bit when PTL is actually being disabled (state=0) Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 5781a3934b6e..d0e7212519f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2392,7 +2392,7 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool ena fmt2 = ptl->fmt2; } - /* initialize PTL with default formats: GFX_FTYPE_I8 & GFX_FTYPE_BF16 */ + /* initialize PTL with default formats: GFX_FTYPE_VECTOR & GFX_FTYPE_F8 */ r = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, &fmt1, &fmt2); if (r) @@ -2401,6 +2401,13 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool ena ptl->hw_supported = true; atomic_set(&ptl->disable_ref, 0); + if (!enable) { + dev_dbg(adev->dev, + "PTL disabled (amdgpu.ptl=%d)\ + To enable, set amdgpu.ptl=1 via module param or kernel cmdline\n", + amdgpu_ptl); + set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); + } return 0; } From 599c994c28a8d94875d0a5fa8779fbff390db7d8 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Fri, 13 Mar 2026 16:31:07 +0800 Subject: [PATCH 20/71] drm/amdgpu/gfx9.4.3: skip PTL disable during GPU reset During RAS UE-triggered GPU reset, gfx_v9_4_3_hw_fini() attempts to send a PTL disable command to PSP. Since PSP is unresponsive at that point, this produces spurious error logs on all hive nodes: PTL command 0xa0000001 failed, PSP response status: 0xFFFFFFFF PTL initialization failed (-5) Skip the PTL disable command when GPU reset is in progress, as PTL will be properly re-initialized during post-reset recovery via gfx_v9_4_3_late_init(). Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index d0e7212519f9..f895c3ef56bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2443,7 +2443,7 @@ static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; int i, num_xcc; - if (adev->psp.ptl.hw_supported) + if (adev->psp.ptl.hw_supported && !amdgpu_in_reset(adev)) gfx_v9_4_3_perf_monitor_ptl_init(adev, false); amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); From 682142124e3848ec03904bf6bf7063e1cac197c4 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 10 Mar 2026 10:39:08 +0800 Subject: [PATCH 21/71] drm/amdgpu: fix ptl state isssue after GPU reset or suspend Fix this by skipping the sysfs disable mapping when the GPU is currently undergoing a reset or suspend flow. Additionally, add debug logging in psp_ptl_invoke() to better trace PTL state and format queries/updates cmd. Signed-off-by: Perry Yuan Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index aec284c6b6d7..d525443e31f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1289,12 +1289,16 @@ static int psp_ptl_invoke(struct psp_context *psp, u32 req_code, *ptl_state = cmd->resp.uresp.perf_hw_info.ptl_state; *fmt1 = cmd->resp.uresp.perf_hw_info.pref_format1; *fmt2 = cmd->resp.uresp.perf_hw_info.pref_format2; + dev_dbg(psp->adev->dev, "PTL query: state=%d, fmt1=%d, fmt2=%d\n", + *ptl_state, *fmt1, *fmt2); break; case PSP_PTL_PERF_MON_SET: /* Update cached state only on success */ ptl->enabled = *ptl_state; ptl->fmt1 = *fmt1; ptl->fmt2 = *fmt2; + dev_dbg(psp->adev->dev, "PTL set: state=%d, fmt1=%d, fmt2=%d\n", + *ptl_state, *fmt1, *fmt2); break; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index f895c3ef56bc..9f76e1af8a55 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2401,7 +2401,7 @@ static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool ena ptl->hw_supported = true; atomic_set(&ptl->disable_ref, 0); - if (!enable) { + if (!enable && !amdgpu_in_reset(adev) && !adev->in_suspend) { dev_dbg(adev->dev, "PTL disabled (amdgpu.ptl=%d)\ To enable, set amdgpu.ptl=1 via module param or kernel cmdline\n", From c62c076d2d64ead542c961cabed0f9467d7d6026 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 15 Apr 2026 10:34:03 +0800 Subject: [PATCH 22/71] drm/amdkfd: bump KFD ioctl minor version to 1.23 Bump `KFD_IOCTL_MINOR_VERSION` from 22 to 23 and document version 1.23 in `kfd_ioctl.h` so userspace can detect profiler ioctl support. Signed-off-by: Perry Yuan Suggested-by: Alex Deucher Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- include/uapi/linux/kfd_ioctl.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 1a94d512df35..9584b5aab727 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -48,9 +48,10 @@ * - 1.20 - Trap handler support for expert scheduling mode available * - 1.21 - Debugger support to subscribe to LDS out-of-address exceptions * - 1.22 - Add queue creation with metadata ring base address + * - 1.23 - Add profiler control ioctl to enable/disable profiler on a process */ #define KFD_IOCTL_MAJOR_VERSION 1 -#define KFD_IOCTL_MINOR_VERSION 22 +#define KFD_IOCTL_MINOR_VERSION 23 struct kfd_ioctl_get_version_args { __u32 major_version; /* from KFD */ From fcd5f065eab46993af43442fd77ee8d9eb9c5bdf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 20 Apr 2026 20:18:43 +0200 Subject: [PATCH 23/71] drm/amdgpu: remove deadlocks from amdgpu_userq_pre_reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The purpose of a GPU reset is to make sure that fence can be signaled again and the signal and resume workers can make progress again. So waiting for the resume worker or any fence in the GPU reset path is just utterly nonsense. Signed-off-by: Christian König Reviewed-by: Prike Liang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 26 +++++++++++------------ 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index de140a8ed135..692f7e3513df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -1504,23 +1504,21 @@ void amdgpu_userq_pre_reset(struct amdgpu_device *adev) { const struct amdgpu_userq_funcs *userq_funcs; struct amdgpu_usermode_queue *queue; - struct amdgpu_userq_mgr *uqm; unsigned long queue_id; + /* TODO: We probably need a new lock for the queue state */ xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { - uqm = queue->userq_mgr; - cancel_delayed_work_sync(&uqm->resume_work); - if (queue->state == AMDGPU_USERQ_STATE_MAPPED) { - amdgpu_userq_wait_for_last_fence(queue); - userq_funcs = adev->userq_funcs[queue->queue_type]; - userq_funcs->unmap(queue); - /* just mark all queues as hung at this point. - * if unmap succeeds, we could map again - * in amdgpu_userq_post_reset() if vram is not lost - */ - queue->state = AMDGPU_USERQ_STATE_HUNG; - amdgpu_userq_fence_driver_force_completion(queue); - } + if (queue->state != AMDGPU_USERQ_STATE_MAPPED) + continue; + + userq_funcs = adev->userq_funcs[queue->queue_type]; + userq_funcs->unmap(queue); + /* just mark all queues as hung at this point. + * if unmap succeeds, we could map again + * in amdgpu_userq_post_reset() if vram is not lost + */ + queue->state = AMDGPU_USERQ_STATE_HUNG; + amdgpu_userq_fence_driver_force_completion(queue); } } From e426674e908ec0ca600e4a41284cf267fd6b077b Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Mon, 27 Apr 2026 15:09:37 +0800 Subject: [PATCH 24/71] drm/amd/pm: add SMU multi-msgs helpers SMU15 driver messages can carry multiple input parameters and return values, but callers still have to build struct smu_msg_args directly. Add common SMU multi-msgs helpers in smu_cmn and reuse them in the single-parameter wrapper and the shared table transfer path. Keep smu_cmn_send_smc_msg() semantics unchanged for older callers. No functional change intended. Signed-off-by: Yang Wang Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 96 ++++++++++++++++++-------- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 22 ++++++ 2 files changed, 88 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 90c7127beabf..546e64e3ba9c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -127,6 +127,61 @@ int smu_cmn_wait_for_response(struct smu_context *smu) return smu_msg_wait_response(&smu->msg_ctl, 0); } +/** + * smu_cmn_send_smc_msg_with_params_ext - send an SMU message with 0..N args + * @smu: pointer to an SMU context + * @msg: message to send + * @params: optional input argument array + * @num_params: number of input arguments in @params + * @read_args: optional output argument array + * @num_read_args: number of output arguments to read back + * @flags: message flags (SMU_MSG_FLAG_*) + * @timeout: per-message timeout in us (0 = use default) + * + * This helper keeps the raw protocol semantics of struct smu_msg_args while + * hiding the per-call boilerplate. It is intended for true multi-parameter + * messages. Legacy wrappers such as smu_cmn_send_smc_msg() retain their + * existing single-zero-parameter behavior for compatibility. + * + * Return: 0 on success, -errno on failure. + */ +int smu_cmn_send_smc_msg_with_params_ext(struct smu_context *smu, + enum smu_message_type msg, + const uint32_t *params, + size_t num_params, + uint32_t *read_args, + size_t num_read_args, + uint32_t flags, + uint32_t timeout) +{ + struct smu_msg_ctl *ctl = &smu->msg_ctl; + struct smu_msg_args args = { + .msg = msg, + .num_args = num_params, + .num_out_args = num_read_args, + .flags = flags, + .timeout = timeout, + }; + int ret; + + if ((num_params && !params) || (num_read_args && !read_args)) + return -EINVAL; + + if (num_params > SMU_MSG_MAX_ARGS || num_read_args > SMU_MSG_MAX_ARGS) + return -EINVAL; + + if (num_params) + memcpy(args.args, params, num_params * sizeof(*params)); + + ret = ctl->ops->send_msg(ctl, &args); + + if (num_read_args) + memcpy(read_args, args.out_args, + num_read_args * sizeof(*read_args)); + + return ret; +} + /** * smu_cmn_send_smc_msg_with_param -- send a message with parameter * @smu: pointer to an SMU context @@ -164,23 +219,9 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, uint32_t param, uint32_t *read_arg) { - struct smu_msg_ctl *ctl = &smu->msg_ctl; - struct smu_msg_args args = { - .msg = msg, - .args[0] = param, - .num_args = 1, - .num_out_args = read_arg ? 1 : 0, - .flags = 0, - .timeout = 0, - }; - int ret; - - ret = ctl->ops->send_msg(ctl, &args); - - if (read_arg) - *read_arg = args.out_args[0]; - - return ret; + return smu_cmn_send_smc_msg_with_params(smu, msg, + ¶m, 1, + read_arg, read_arg ? 1 : 0); } int smu_cmn_send_smc_msg(struct smu_context *smu, @@ -1071,13 +1112,12 @@ int smu_cmn_update_table_read_arg(struct smu_context *smu, struct amdgpu_device *adev = smu->adev; struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *table = &smu_table->driver_table; - struct smu_msg_ctl *ctl = &smu->msg_ctl; - struct smu_msg_args args; int table_id = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_TABLE, table_index); uint32_t table_size; int ret = 0; + uint32_t param; if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0) return -EINVAL; @@ -1093,18 +1133,14 @@ int smu_cmn_update_table_read_arg(struct smu_context *smu, amdgpu_hdp_flush(adev, NULL); } - args.msg = drv2smu ? SMU_MSG_TransferTableDram2Smu : SMU_MSG_TransferTableSmu2Dram; - args.args[0] = ((argument & 0xFFFF) << 16) | (table_id & 0xffff); - args.num_args = 1; - args.out_args[0] = 0; - args.num_out_args = read_arg ? 1 : 0; - args.flags = read_arg ? SMU_MSG_FLAG_FORCE_READ_ARG : 0; - args.timeout = 0; + param = ((argument & 0xFFFF) << 16) | (table_id & 0xffff); - ret = ctl->ops->send_msg(ctl, &args); - - if (read_arg) - *read_arg = args.out_args[0]; + ret = smu_cmn_send_smc_msg_with_params_ext( + smu, + drv2smu ? SMU_MSG_TransferTableDram2Smu : + SMU_MSG_TransferTableSmu2Dram, + ¶m, 1, read_arg, read_arg ? 1 : 0, + read_arg ? SMU_MSG_FLAG_FORCE_READ_ARG : 0, 0); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h index c6ac0e876aea..0e119965ce13 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h @@ -118,6 +118,28 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, uint32_t param, uint32_t *read_arg); +int smu_cmn_send_smc_msg_with_params_ext(struct smu_context *smu, + enum smu_message_type msg, + const uint32_t *params, + size_t num_params, + uint32_t *read_args, + size_t num_read_args, + uint32_t flags, + uint32_t timeout); + +static inline int smu_cmn_send_smc_msg_with_params(struct smu_context *smu, + enum smu_message_type msg, + const uint32_t *params, + size_t num_params, + uint32_t *read_args, + size_t num_read_args) +{ + return smu_cmn_send_smc_msg_with_params_ext(smu, msg, + params, num_params, + read_args, num_read_args, + 0, 0); +} + int smu_cmn_send_smc_msg(struct smu_context *smu, enum smu_message_type msg, uint32_t *read_arg); From 359cf7b42f87acc1ddd6b974fabe0ed6722f97ff Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Mon, 27 Apr 2026 15:09:37 +0800 Subject: [PATCH 25/71] drm/amd/pm: use the SMU multi-msgs helper in smu_v15_0 Convert the SMU15 table address messages to smu_cmn_send_smc_msg_with_params() so they use the common SMU multi-msgs helper instead of open-coding struct smu_msg_args. No functional change intended. Signed-off-by: Yang Wang Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c | 45 +++++++++---------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c index c3cb36813806..cc3a265700a5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -589,52 +589,47 @@ int smu_v15_0_notify_memory_pool_location(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *memory_pool = &smu_table->memory_pool; - struct smu_msg_args args = { - .msg = SMU_MSG_DramLogSetDramAddr, - .num_args = 3, - .num_out_args = 0, - }; + uint32_t params[3]; if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) return 0; /* SMU_MSG_DramLogSetDramAddr: ARG0=low, ARG1=high, ARG2=size */ - args.args[0] = lower_32_bits(memory_pool->mc_address); - args.args[1] = upper_32_bits(memory_pool->mc_address); - args.args[2] = (u32)memory_pool->size; + params[0] = lower_32_bits(memory_pool->mc_address); + params[1] = upper_32_bits(memory_pool->mc_address); + params[2] = (u32)memory_pool->size; - return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); + return smu_cmn_send_smc_msg_with_params(smu, + SMU_MSG_DramLogSetDramAddr, + params, ARRAY_SIZE(params), + NULL, 0); } int smu_v15_0_set_driver_table_location(struct smu_context *smu) { struct smu_table *driver_table = &smu->smu_table.driver_table; - struct smu_msg_args args = { - .msg = SMU_MSG_SetDriverDramAddr, - .num_args = 2, - .num_out_args = 0, + const uint32_t params[] = { + lower_32_bits(driver_table->mc_address), + upper_32_bits(driver_table->mc_address), }; - args.args[0] = lower_32_bits(driver_table->mc_address); - args.args[1] = upper_32_bits(driver_table->mc_address); - - return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); + return smu_cmn_send_smc_msg_with_params(smu, SMU_MSG_SetDriverDramAddr, + params, ARRAY_SIZE(params), + NULL, 0); } int smu_v15_0_set_tool_table_location(struct smu_context *smu) { struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; - struct smu_msg_args args = { - .msg = SMU_MSG_SetToolsDramAddr, - .num_args = 2, - .num_out_args = 0, + const uint32_t params[] = { + lower_32_bits(tool_table->mc_address), + upper_32_bits(tool_table->mc_address), }; /* SMU_MSG_SetToolsDramAddr: ARG0=low, ARG1=high */ - args.args[0] = lower_32_bits(tool_table->mc_address); - args.args[1] = upper_32_bits(tool_table->mc_address); - - return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); + return smu_cmn_send_smc_msg_with_params(smu, SMU_MSG_SetToolsDramAddr, + params, ARRAY_SIZE(params), + NULL, 0); } int smu_v15_0_set_allowed_mask(struct smu_context *smu) From 1609eb0f81a609d350169839128cecf298c84e7a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 16 Apr 2026 15:32:11 +0200 Subject: [PATCH 26/71] drm/amdgpu: rework amdgpu_userq_signal_ioctl v3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This one was fortunately not looking so bad as the wait ioctl path, but there were still a few things which could be fixed/improved: 1. Allocating with GFP_ATOMIC was quite unnecessary, we can do that before taking the userq_lock. 2. Use a new mutex as protection for the fence_drv_xa so that we can do memory allocations while holding it. 3. Starting the reset timer is unnecessary when the fence is already signaled when we create it. 4. Cleanup error handling, avoid trying to free the queue when we don't even got one. v2: fix incorrect usage of xa_find, destroy the new mutex on error v3: cleanup ref ordering Signed-off-by: Christian König Reviewed-by: Sunil Khatri Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 12 + .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 228 ++++++++---------- 3 files changed, 120 insertions(+), 122 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 692f7e3513df..2d4f159f3362 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -800,6 +800,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) } queue->doorbell_index = index; + mutex_init(&queue->fence_drv_lock); xa_init_flags(&queue->fence_drv_xa, XA_FLAGS_ALLOC); r = amdgpu_userq_fence_driver_alloc(adev, &queue->fence_drv); if (r) { @@ -873,6 +874,7 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) amdgpu_bo_reserve(fpriv->vm.root.bo, true); amdgpu_userq_buffer_vas_list_cleanup(adev, queue); amdgpu_bo_unreserve(fpriv->vm.root.bo); + mutex_destroy(&queue->fence_drv_lock); free_queue: kfree(queue); err_pm_runtime: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 8b8f345b60b6..843ea8ecc5d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -66,6 +66,18 @@ struct amdgpu_usermode_queue { struct amdgpu_userq_obj db_obj; struct amdgpu_userq_obj fw_obj; struct amdgpu_userq_obj wptr_obj; + + /** + * @fence_drv_lock: Protecting @fence_drv_xa. + */ + struct mutex fence_drv_lock; + + /** + * @fence_drv_xa: + * + * References to the external fence drivers returned by wait_ioctl. + * Dropped on the next signaled dma_fence or queue destruction. + */ struct xarray fence_drv_xa; struct amdgpu_userq_fence_driver *fence_drv; struct dma_fence *last_fence; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index e2d5f04296e1..c9dbf03c4eea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -121,6 +121,7 @@ amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq) userq->last_fence = NULL; amdgpu_userq_walk_and_drop_fence_drv(&userq->fence_drv_xa); xa_destroy(&userq->fence_drv_xa); + mutex_destroy(&userq->fence_drv_lock); /* Drop the queue's ownership reference to fence_drv explicitly */ amdgpu_userq_fence_driver_put(userq->fence_drv); } @@ -209,80 +210,84 @@ void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv) kref_put(&fence_drv->refcount, amdgpu_userq_fence_driver_destroy); } -static int amdgpu_userq_fence_alloc(struct amdgpu_userq_fence **userq_fence) +static int amdgpu_userq_fence_alloc(struct amdgpu_usermode_queue *userq, + struct amdgpu_userq_fence **pfence) { - *userq_fence = kmalloc(sizeof(**userq_fence), GFP_KERNEL); - return *userq_fence ? 0 : -ENOMEM; + struct amdgpu_userq_fence_driver *fence_drv = userq->fence_drv; + struct amdgpu_userq_fence *userq_fence; + void *entry; + + userq_fence = kmalloc(sizeof(*userq_fence), GFP_KERNEL); + if (!userq_fence) + return -ENOMEM; + + /* + * Get the next unused entry, since we fill from the start this can be + * used as size to allocate the array. + */ + mutex_lock(&userq->fence_drv_lock); + XA_STATE(xas, &userq->fence_drv_xa, 0); + + rcu_read_lock(); + do { + entry = xas_find_marked(&xas, ULONG_MAX, XA_FREE_MARK); + } while (xas_retry(&xas, entry)); + rcu_read_unlock(); + + userq_fence->fence_drv_array = kvmalloc_array(xas.xa_index, + sizeof(fence_drv), + GFP_KERNEL); + if (!userq_fence->fence_drv_array) { + mutex_unlock(&userq->fence_drv_lock); + kfree(userq_fence); + return -ENOMEM; + } + + userq_fence->fence_drv_array_count = xas.xa_index; + xa_extract(&userq->fence_drv_xa, (void **)userq_fence->fence_drv_array, + 0, ULONG_MAX, xas.xa_index, XA_PRESENT); + xa_destroy(&userq->fence_drv_xa); + + mutex_unlock(&userq->fence_drv_lock); + + amdgpu_userq_fence_driver_get(fence_drv); + userq_fence->fence_drv = fence_drv; + + *pfence = userq_fence; + return 0; } -static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq, - struct amdgpu_userq_fence *userq_fence, - u64 seq, struct dma_fence **f) +static void amdgpu_userq_fence_init(struct amdgpu_usermode_queue *userq, + struct amdgpu_userq_fence *fence, + u64 seq) { - struct amdgpu_userq_fence_driver *fence_drv; - struct dma_fence *fence; + struct amdgpu_userq_fence_driver *fence_drv = userq->fence_drv; unsigned long flags; bool signaled = false; - fence_drv = userq->fence_drv; - if (!fence_drv) - return -EINVAL; - - spin_lock_init(&userq_fence->lock); - INIT_LIST_HEAD(&userq_fence->link); - fence = &userq_fence->base; - userq_fence->fence_drv = fence_drv; - - dma_fence_init64(fence, &amdgpu_userq_fence_ops, &userq_fence->lock, + spin_lock_init(&fence->lock); + dma_fence_init64(&fence->base, &amdgpu_userq_fence_ops, &fence->lock, fence_drv->context, seq); - amdgpu_userq_fence_driver_get(fence_drv); - dma_fence_get(fence); + /* Make sure the fence is visible to the hang detect worker */ + dma_fence_put(userq->last_fence); + userq->last_fence = dma_fence_get(&fence->base); - if (!xa_empty(&userq->fence_drv_xa)) { - struct amdgpu_userq_fence_driver *stored_fence_drv; - unsigned long index, count = 0; - int i = 0; - - xa_lock(&userq->fence_drv_xa); - xa_for_each(&userq->fence_drv_xa, index, stored_fence_drv) - count++; - - userq_fence->fence_drv_array = - kvmalloc_objs(struct amdgpu_userq_fence_driver *, count, - GFP_ATOMIC); - - if (userq_fence->fence_drv_array) { - xa_for_each(&userq->fence_drv_xa, index, stored_fence_drv) { - userq_fence->fence_drv_array[i] = stored_fence_drv; - __xa_erase(&userq->fence_drv_xa, index); - i++; - } - } - - userq_fence->fence_drv_array_count = i; - xa_unlock(&userq->fence_drv_xa); - } else { - userq_fence->fence_drv_array = NULL; - userq_fence->fence_drv_array_count = 0; - } - - /* Check if hardware has already processed the job */ + /* Check if hardware has already processed the fence */ spin_lock_irqsave(&fence_drv->fence_list_lock, flags); - if (!dma_fence_is_signaled(fence)) { - list_add_tail(&userq_fence->link, &fence_drv->fences); + if (!dma_fence_is_signaled(&fence->base)) { + dma_fence_get(&fence->base); + list_add_tail(&fence->link, &fence_drv->fences); } else { + INIT_LIST_HEAD(&fence->link); signaled = true; - dma_fence_put(fence); } spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); if (signaled) - amdgpu_userq_fence_put_fence_drv_array(userq_fence); - - *f = fence; - - return 0; + amdgpu_userq_fence_put_fence_drv_array(fence); + else + amdgpu_userq_start_hang_detect_work(userq); } static const char *amdgpu_userq_fence_get_driver_name(struct dma_fence *f) @@ -403,11 +408,6 @@ static int amdgpu_userq_fence_read_wptr(struct amdgpu_device *adev, return r; } -static void amdgpu_userq_fence_cleanup(struct dma_fence *fence) -{ - dma_fence_put(fence); -} - static void amdgpu_userq_fence_driver_set_error(struct amdgpu_userq_fence *fence, int error) @@ -451,13 +451,14 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, const unsigned int num_read_bo_handles = args->num_bo_read_handles; struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; + struct drm_gem_object **gobj_write, **gobj_read; u32 *syncobj_handles, num_syncobj_handles; - struct amdgpu_userq_fence *userq_fence; - struct amdgpu_usermode_queue *queue = NULL; - struct drm_syncobj **syncobj = NULL; - struct dma_fence *fence; + struct amdgpu_usermode_queue *queue; + struct amdgpu_userq_fence *fence; + struct drm_syncobj **syncobj; struct drm_exec exec; + void __user *ptr; int r, i, entry; u64 wptr; @@ -469,13 +470,14 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, return -EINVAL; num_syncobj_handles = args->num_syncobj_handles; - syncobj_handles = memdup_array_user(u64_to_user_ptr(args->syncobj_handles), - num_syncobj_handles, sizeof(u32)); + ptr = u64_to_user_ptr(args->syncobj_handles); + syncobj_handles = memdup_array_user(ptr, num_syncobj_handles, + sizeof(u32)); if (IS_ERR(syncobj_handles)) return PTR_ERR(syncobj_handles); - /* Array of pointers to the looked up syncobjs */ - syncobj = kmalloc_array(num_syncobj_handles, sizeof(*syncobj), GFP_KERNEL); + syncobj = kmalloc_array(num_syncobj_handles, sizeof(*syncobj), + GFP_KERNEL); if (!syncobj) { r = -ENOMEM; goto free_syncobj_handles; @@ -489,21 +491,17 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, } } - r = drm_gem_objects_lookup(filp, - u64_to_user_ptr(args->bo_read_handles), - num_read_bo_handles, - &gobj_read); + ptr = u64_to_user_ptr(args->bo_read_handles); + r = drm_gem_objects_lookup(filp, ptr, num_read_bo_handles, &gobj_read); if (r) goto free_syncobj; - r = drm_gem_objects_lookup(filp, - u64_to_user_ptr(args->bo_write_handles), - num_write_bo_handles, + ptr = u64_to_user_ptr(args->bo_write_handles); + r = drm_gem_objects_lookup(filp, ptr, num_write_bo_handles, &gobj_write); if (r) goto put_gobj_read; - /* Retrieve the user queue */ queue = amdgpu_userq_get(userq_mgr, args->queue_id); if (!queue) { r = -ENOENT; @@ -512,73 +510,61 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, r = amdgpu_userq_fence_read_wptr(adev, queue, &wptr); if (r) - goto put_gobj_write; + goto put_queue; - r = amdgpu_userq_fence_alloc(&userq_fence); + r = amdgpu_userq_fence_alloc(queue, &fence); if (r) - goto put_gobj_write; + goto put_queue; /* We are here means UQ is active, make sure the eviction fence is valid */ amdgpu_userq_ensure_ev_fence(&fpriv->userq_mgr, &fpriv->evf_mgr); - /* Create a new fence */ - r = amdgpu_userq_fence_create(queue, userq_fence, wptr, &fence); - if (r) { - mutex_unlock(&userq_mgr->userq_mutex); - kfree(userq_fence); - goto put_gobj_write; - } + /* Create the new fence */ + amdgpu_userq_fence_init(queue, fence, wptr); - dma_fence_put(queue->last_fence); - queue->last_fence = dma_fence_get(fence); - amdgpu_userq_start_hang_detect_work(queue); mutex_unlock(&userq_mgr->userq_mutex); + /* + * This needs to come after the fence is created since + * amdgpu_userq_ensure_ev_fence() can't be called while holding the resv + * locks. + */ drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, (num_read_bo_handles + num_write_bo_handles)); - /* Lock all BOs with retry handling */ drm_exec_until_all_locked(&exec) { - r = drm_exec_prepare_array(&exec, gobj_read, num_read_bo_handles, 1); + r = drm_exec_prepare_array(&exec, gobj_read, + num_read_bo_handles, 1); drm_exec_retry_on_contention(&exec); - if (r) { - amdgpu_userq_fence_cleanup(fence); + if (r) goto exec_fini; - } - r = drm_exec_prepare_array(&exec, gobj_write, num_write_bo_handles, 1); + r = drm_exec_prepare_array(&exec, gobj_write, + num_write_bo_handles, 1); drm_exec_retry_on_contention(&exec); - if (r) { - amdgpu_userq_fence_cleanup(fence); + if (r) goto exec_fini; - } } - for (i = 0; i < num_read_bo_handles; i++) { - if (!gobj_read || !gobj_read[i]->resv) - continue; - - dma_resv_add_fence(gobj_read[i]->resv, fence, + /* And publish the new fence in the BOs and syncobj */ + for (i = 0; i < num_read_bo_handles; i++) + dma_resv_add_fence(gobj_read[i]->resv, &fence->base, DMA_RESV_USAGE_READ); - } - for (i = 0; i < num_write_bo_handles; i++) { - if (!gobj_write || !gobj_write[i]->resv) - continue; - - dma_resv_add_fence(gobj_write[i]->resv, fence, + for (i = 0; i < num_write_bo_handles; i++) + dma_resv_add_fence(gobj_write[i]->resv, &fence->base, DMA_RESV_USAGE_WRITE); - } - /* Add the created fence to syncobj/BO's */ for (i = 0; i < num_syncobj_handles; i++) - drm_syncobj_replace_fence(syncobj[i], fence); - - /* drop the reference acquired in fence creation function */ - dma_fence_put(fence); + drm_syncobj_replace_fence(syncobj[i], &fence->base); exec_fini: + /* drop the reference acquired in fence creation function */ + dma_fence_put(&fence->base); + drm_exec_fini(&exec); +put_queue: + amdgpu_userq_put(queue); put_gobj_write: for (i = 0; i < num_write_bo_handles; i++) drm_gem_object_put(gobj_write[i]); @@ -589,15 +575,11 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, kvfree(gobj_read); free_syncobj: while (entry-- > 0) - if (syncobj[entry]) - drm_syncobj_put(syncobj[entry]); + drm_syncobj_put(syncobj[entry]); kfree(syncobj); free_syncobj_handles: kfree(syncobj_handles); - if (queue) - amdgpu_userq_put(queue); - return r; } @@ -872,8 +854,10 @@ amdgpu_userq_wait_return_fence_info(struct drm_file *filp, * Otherwise, we would gather those references until we don't * have any more space left and crash. */ + mutex_lock(&waitq->fence_drv_lock); r = xa_alloc(&waitq->fence_drv_xa, &index, fence_drv, xa_limit_32b, GFP_KERNEL); + mutex_unlock(&waitq->fence_drv_lock); if (r) goto put_waitq; From 71bea36b54ccfb14cbc90f94267af6369af4e702 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 20 Apr 2026 15:13:57 +0200 Subject: [PATCH 27/71] drm/amdgpu: remove almost all calls to amdgpu_userq_detect_and_reset_queues MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Well the reset handling seems broken on multiple levels. As first step of fixing this remove most calls to the hang detection. That function should only be called after we run into a timeout! And *NOT* as random check spread over the code in multiple places. Signed-off-by: Christian König Reviewed-by: Sunil Khatri Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 38 +++++++++-------------- 1 file changed, 14 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 2d4f159f3362..ba03d2a42e1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -345,23 +345,18 @@ static int amdgpu_userq_preempt_helper(struct amdgpu_usermode_queue *queue) struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *userq_funcs = adev->userq_funcs[queue->queue_type]; - bool found_hung_queue = false; - int r = 0; + int r; if (queue->state == AMDGPU_USERQ_STATE_MAPPED) { r = userq_funcs->preempt(queue); if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; - found_hung_queue = true; + return r; } else { queue->state = AMDGPU_USERQ_STATE_PREEMPTED; } } - - if (found_hung_queue) - amdgpu_userq_detect_and_reset_queues(uq_mgr); - - return r; + return 0; } static int amdgpu_userq_restore_helper(struct amdgpu_usermode_queue *queue) @@ -390,24 +385,21 @@ static int amdgpu_userq_unmap_helper(struct amdgpu_usermode_queue *queue) struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *userq_funcs = adev->userq_funcs[queue->queue_type]; - bool found_hung_queue = false; - int r = 0; + int r; if ((queue->state == AMDGPU_USERQ_STATE_MAPPED) || - (queue->state == AMDGPU_USERQ_STATE_PREEMPTED)) { + (queue->state == AMDGPU_USERQ_STATE_PREEMPTED)) { + r = userq_funcs->unmap(queue); if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; - found_hung_queue = true; + return r; } else { queue->state = AMDGPU_USERQ_STATE_UNMAPPED; } } - if (found_hung_queue) - amdgpu_userq_detect_and_reset_queues(uq_mgr); - - return r; + return 0; } static int amdgpu_userq_map_helper(struct amdgpu_usermode_queue *queue) @@ -416,19 +408,19 @@ static int amdgpu_userq_map_helper(struct amdgpu_usermode_queue *queue) struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *userq_funcs = adev->userq_funcs[queue->queue_type]; - int r = 0; + int r; if (queue->state == AMDGPU_USERQ_STATE_UNMAPPED) { r = userq_funcs->map(queue); if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; - amdgpu_userq_detect_and_reset_queues(uq_mgr); + return r; } else { queue->state = AMDGPU_USERQ_STATE_MAPPED; } } - return r; + return 0; } static void amdgpu_userq_wait_for_last_fence(struct amdgpu_usermode_queue *queue) @@ -654,7 +646,6 @@ amdgpu_userq_destroy(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_que #if defined(CONFIG_DEBUG_FS) debugfs_remove_recursive(queue->debugfs_queue); #endif - amdgpu_userq_detect_and_reset_queues(uq_mgr); r = amdgpu_userq_unmap_helper(queue); atomic_dec(&uq_mgr->userq_count[queue->queue_type]); amdgpu_userq_cleanup(queue); @@ -1264,7 +1255,6 @@ amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr) unsigned long queue_id; int ret = 0, r; - amdgpu_userq_detect_and_reset_queues(uq_mgr); /* Try to unmap all the queues in this process ctx */ xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { r = amdgpu_userq_preempt_helper(queue); @@ -1272,9 +1262,11 @@ amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr) ret = r; } - if (ret) + if (ret) { drm_file_err(uq_mgr->file, "Couldn't unmap all the queues, eviction failed ret=%d\n", ret); + amdgpu_userq_detect_and_reset_queues(uq_mgr); + } return ret; } @@ -1374,7 +1366,6 @@ int amdgpu_userq_suspend(struct amdgpu_device *adev) uqm = queue->userq_mgr; cancel_delayed_work_sync(&uqm->resume_work); guard(mutex)(&uqm->userq_mutex); - amdgpu_userq_detect_and_reset_queues(uqm); if (adev->in_s0ix) r = amdgpu_userq_preempt_helper(queue); else @@ -1433,7 +1424,6 @@ int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, if (((queue->queue_type == AMDGPU_HW_IP_GFX) || (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && (queue->xcp_id == idx)) { - amdgpu_userq_detect_and_reset_queues(uqm); r = amdgpu_userq_preempt_helper(queue); if (r) ret = r; From 1b62077f045ac6ffde7c97005c6659569ac5c1ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Mon, 20 Apr 2026 16:08:35 +0200 Subject: [PATCH 28/71] drm/amdgpu: fix userq hang detection and reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix lock inversions pointed out by Prike and Sunil. The hang detection timeout *CAN'T* grab locks under which we wait for fences, especially not the userq_mutex lock. Then instead of this completely broken handling with the hang_detect_fence just cancel the work when fences are processed and re-start if necessary. Signed-off-by: Christian König Reviewed-by: Sunil Khatri Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 65 ++++++++----------- drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 1 - .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 17 +++-- .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.h | 2 +- 4 files changed, 40 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index ba03d2a42e1e..70d74f04d2dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -106,9 +106,6 @@ amdgpu_userq_detect_and_reset_queues(struct amdgpu_userq_mgr *uq_mgr) int r = 0; int i; - /* Warning if current process mutex is not held */ - WARN_ON(!mutex_is_locked(&uq_mgr->userq_mutex)); - if (unlikely(adev->debug_disable_gpu_ring_reset)) { dev_err(adev->dev, "userq reset disabled by debug mask\n"); return 0; @@ -127,9 +124,11 @@ amdgpu_userq_detect_and_reset_queues(struct amdgpu_userq_mgr *uq_mgr) */ for (i = 0; i < num_queue_types; i++) { int ring_type = queue_types[i]; - const struct amdgpu_userq_funcs *funcs = adev->userq_funcs[ring_type]; + const struct amdgpu_userq_funcs *funcs = + adev->userq_funcs[ring_type]; - if (!amdgpu_userq_is_reset_type_supported(adev, ring_type, AMDGPU_RESET_TYPE_PER_QUEUE)) + if (!amdgpu_userq_is_reset_type_supported(adev, ring_type, + AMDGPU_RESET_TYPE_PER_QUEUE)) continue; if (atomic_read(&uq_mgr->userq_count[ring_type]) > 0 && @@ -150,38 +149,22 @@ amdgpu_userq_detect_and_reset_queues(struct amdgpu_userq_mgr *uq_mgr) static void amdgpu_userq_hang_detect_work(struct work_struct *work) { - struct amdgpu_usermode_queue *queue = container_of(work, - struct amdgpu_usermode_queue, - hang_detect_work.work); - struct dma_fence *fence; - struct amdgpu_userq_mgr *uq_mgr; + struct amdgpu_usermode_queue *queue = + container_of(work, struct amdgpu_usermode_queue, + hang_detect_work.work); - if (!queue->userq_mgr) - return; - - uq_mgr = queue->userq_mgr; - fence = READ_ONCE(queue->hang_detect_fence); - /* Fence already signaled – no action needed */ - if (!fence || dma_fence_is_signaled(fence)) - return; - - mutex_lock(&uq_mgr->userq_mutex); - amdgpu_userq_detect_and_reset_queues(uq_mgr); - mutex_unlock(&uq_mgr->userq_mutex); + amdgpu_userq_detect_and_reset_queues(queue->userq_mgr); } /* * Start hang detection for a user queue fence. A delayed work will be scheduled - * to check if the fence is still pending after the timeout period. -*/ + * to reset the queues when the fence doesn't signal in time. + */ void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue) { struct amdgpu_device *adev; unsigned long timeout_ms; - if (!queue || !queue->userq_mgr || !queue->userq_mgr->adev) - return; - adev = queue->userq_mgr->adev; /* Determine timeout based on queue type */ switch (queue->queue_type) { @@ -199,8 +182,6 @@ void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue) break; } - /* Store the fence to monitor and schedule hang detection */ - WRITE_ONCE(queue->hang_detect_fence, queue->last_fence); schedule_delayed_work(&queue->hang_detect_work, msecs_to_jiffies(timeout_ms)); } @@ -210,18 +191,24 @@ void amdgpu_userq_process_fence_irq(struct amdgpu_device *adev, u32 doorbell) struct xarray *xa = &adev->userq_doorbell_xa; struct amdgpu_usermode_queue *queue; unsigned long flags; + int r; xa_lock_irqsave(xa, flags); queue = xa_load(xa, doorbell); - if (queue) - amdgpu_userq_fence_driver_process(queue->fence_drv); - xa_unlock_irqrestore(xa, flags); -} + if (queue) { + r = amdgpu_userq_fence_driver_process(queue->fence_drv); + /* + * We are in interrupt context here, this *can't* wait for + * reset work to finish. + */ + if (r >= 0) + cancel_delayed_work(&queue->hang_detect_work); -static void amdgpu_userq_init_hang_detect_work(struct amdgpu_usermode_queue *queue) -{ - INIT_DELAYED_WORK(&queue->hang_detect_work, amdgpu_userq_hang_detect_work); - queue->hang_detect_fence = NULL; + /* Restart the timer when there are still fences pending */ + if (r == 1) + amdgpu_userq_start_hang_detect_work(queue); + } + xa_unlock_irqrestore(xa, flags); } static int amdgpu_userq_buffer_va_list_add(struct amdgpu_usermode_queue *queue, @@ -640,7 +627,6 @@ amdgpu_userq_destroy(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_que amdgpu_bo_unreserve(vm->root.bo); mutex_lock(&uq_mgr->userq_mutex); - queue->hang_detect_fence = NULL; amdgpu_userq_wait_for_last_fence(queue); #if defined(CONFIG_DEBUG_FS) @@ -847,7 +833,8 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) up_read(&adev->reset_domain->sem); amdgpu_debugfs_userq_init(filp, queue, qid); - amdgpu_userq_init_hang_detect_work(queue); + INIT_DELAYED_WORK(&queue->hang_detect_work, + amdgpu_userq_hang_detect_work); args->out.queue_id = qid; atomic_inc(&uq_mgr->userq_count[queue->queue_type]); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index 843ea8ecc5d7..85f460e7c31b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -85,7 +85,6 @@ struct amdgpu_usermode_queue { int priority; struct dentry *debugfs_queue; struct delayed_work hang_detect_work; - struct dma_fence *hang_detect_fence; struct kref refcount; struct list_head userq_va_list; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index c9dbf03c4eea..53a8944bab05 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -135,7 +135,14 @@ amdgpu_userq_fence_put_fence_drv_array(struct amdgpu_userq_fence *userq_fence) userq_fence->fence_drv_array_count = 0; } -void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv) +/* + * Returns: + * -ENOENT when no fences were processes + * 1 when more fences are pending + * 0 when no fences are pending any more + */ +int +amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv) { struct amdgpu_userq_fence *userq_fence, *tmp; LIST_HEAD(to_be_signaled); @@ -143,9 +150,6 @@ void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_d unsigned long flags; u64 rptr; - if (!fence_drv) - return; - spin_lock_irqsave(&fence_drv->fence_list_lock, flags); rptr = amdgpu_userq_fence_read(fence_drv); @@ -158,6 +162,9 @@ void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_d &userq_fence->link); spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); + if (list_empty(&to_be_signaled)) + return -ENOENT; + list_for_each_entry_safe(userq_fence, tmp, &to_be_signaled, link) { fence = &userq_fence->base; list_del_init(&userq_fence->link); @@ -169,6 +176,8 @@ void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_d dma_fence_put(fence); } + /* That doesn't need to be accurate so no locking */ + return list_empty(&fence_drv->fences) ? 0 : 1; } void amdgpu_userq_fence_driver_destroy(struct kref *ref) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h index d355a0eecc07..0bd51616cef1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h @@ -63,7 +63,7 @@ void amdgpu_userq_fence_driver_put(struct amdgpu_userq_fence_driver *fence_drv); int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, struct amdgpu_userq_fence_driver **fence_drv_req); void amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq); -void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv); +int amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_drv); void amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq); void amdgpu_userq_fence_driver_destroy(struct kref *ref); int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, From cc826326f6e52c594c8334d418507e49b2d5d288 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Mon, 27 Apr 2026 15:09:37 +0800 Subject: [PATCH 29/71] drm/amd/pm: use the SMU multi-msgs helper in smu_v15_0_0 Convert the SMU15.0.0 table transfer path and enabled-feature query to smu_cmn_send_smc_msg_with_params() so both paths use the common SMU multi-msgs helper. No functional change intended. Signed-off-by: Yang Wang Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c | 38 ++++++++----------- 1 file changed, 15 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c index 8d092c347076..fb1145691410 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -248,7 +248,7 @@ static int smu_v15_0_0_update_table(struct smu_context *smu, uint64_t address; uint32_t table_size; int ret; - struct smu_msg_ctl *ctl = &smu->msg_ctl; + uint32_t params[3]; if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0) return -EINVAL; @@ -265,20 +265,15 @@ static int smu_v15_0_0_update_table(struct smu_context *smu, } address = table->mc_address; + params[0] = table_id; + params[1] = (uint32_t)lower_32_bits(address); + params[2] = (uint32_t)upper_32_bits(address); - struct smu_msg_args args = { - .msg = drv2smu ? - SMU_MSG_TransferTableDram2Smu : - SMU_MSG_TransferTableSmu2Dram, - .num_args = 3, - .num_out_args = 0, - }; - - args.args[0] = table_id; - args.args[1] = (uint32_t)lower_32_bits(address); - args.args[2] = (uint32_t)upper_32_bits(address); - - ret = ctl->ops->send_msg(ctl, &args); + ret = smu_cmn_send_smc_msg_with_params(smu, + drv2smu ? SMU_MSG_TransferTableDram2Smu : + SMU_MSG_TransferTableSmu2Dram, + params, ARRAY_SIZE(params), + NULL, 0); if (ret) return ret; @@ -535,22 +530,19 @@ static int smu_v15_0_0_read_sensor(struct smu_context *smu, static int smu_v15_0_0_get_enabled_mask(struct smu_context *smu, struct smu_feature_bits *feature_mask) { + uint32_t out[2]; int ret; - struct smu_msg_ctl *ctl = &smu->msg_ctl; if (!feature_mask) return -EINVAL; - struct smu_msg_args args = { - .msg = SMU_MSG_GetEnabledSmuFeatures, - .num_args = 0, - .num_out_args = 2, - }; - - ret = ctl->ops->send_msg(ctl, &args); + ret = smu_cmn_send_smc_msg_with_params(smu, + SMU_MSG_GetEnabledSmuFeatures, + NULL, 0, out, + ARRAY_SIZE(out)); if (!ret) - smu_feature_bits_from_arr32(feature_mask, args.out_args, + smu_feature_bits_from_arr32(feature_mask, out, SMU_FEATURE_NUM_DEFAULT); return ret; From a7060a4a5d07c5f4a65e73761975e5c87de738c0 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Mon, 27 Apr 2026 15:09:38 +0800 Subject: [PATCH 30/71] drm/amd/pm: use the SMU multi-msgs helper in smu_v15_0_8 Convert the SMU15.0.8 enabled-feature query to smu_cmn_send_smc_msg_with_params() so it uses the common SMU multi-msgs helper. No functional change intended. Signed-off-by: Yang Wang Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index 977590377021..2105a1d7bb34 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -1313,23 +1313,21 @@ static int smu_v15_0_8_system_features_control(struct smu_context *smu, static int smu_v15_0_8_get_enabled_mask(struct smu_context *smu, struct smu_feature_bits *feature_mask) { - struct smu_msg_args args = { - .msg = SMU_MSG_GetEnabledSmuFeatures, - .num_args = 0, - .num_out_args = 2, - }; + uint32_t out[2]; int ret; if (!feature_mask) return -EINVAL; - ret = smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); + ret = smu_cmn_send_smc_msg_with_params(smu, + SMU_MSG_GetEnabledSmuFeatures, + NULL, 0, + out, ARRAY_SIZE(out)); if (ret) return ret; - smu_feature_bits_from_arr32(feature_mask, args.out_args, - SMU_FEATURE_NUM_DEFAULT); + smu_feature_bits_from_arr32(feature_mask, out, SMU_FEATURE_NUM_DEFAULT); return 0; } From 5da1e1dfd15727918aab2c1a79c019f179991e80 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Thu, 7 May 2026 16:09:51 +0800 Subject: [PATCH 31/71] drm/amdgpu: fix error return code in mes_v12_1_map_test_bo The function mes_v12_1_map_test_bo incorrectly returned 0 unconditionallyon error path, which would hide the real error code and mislead upperlayers about the failure status. Fix it by returning the correct error code 'r' instead of 0. Fixes: 44e5195fa3d4 ("drm/amdgpu/mes_v12_1: add mes self test"); Signed-off-by: Yang Wang Reviewed-by: Asad Kamal Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index 1931562ea6b3..4217b3fea0f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -2063,7 +2063,7 @@ static int mes_v12_1_map_test_bo(struct amdgpu_device *adev, error: amdgpu_sync_free(&sync); - return 0; + return r; } static int mes_v12_1_test_ring(struct amdgpu_device *adev, int xcc_id, From 4be20905baed4a422427acf4c4fc6e437984049c Mon Sep 17 00:00:00 2001 From: ChunTao Tso Date: Wed, 18 Mar 2026 14:12:18 +0800 Subject: [PATCH 32/71] drm/amd/display: Fix refresh rate round up case [Why & How] fix refresh rate round up case Reviewed-by: Robin Chen Signed-off-by: ChunTao Tso Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/modules/power/power_helpers.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c index f8b763db9b8c..f55c15199fb4 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -993,8 +993,8 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link, void set_replay_frame_skip_number(struct dc_link *link, enum replay_coasting_vtotal_type type, - uint32_t coasting_vtotal_refresh_rate_mhz, - uint32_t flicker_free_refresh_rate_mhz, + uint32_t coasting_vtotal_refresh_rate_uhz, + uint32_t flicker_free_refresh_rate_uhz, bool is_defer) { uint32_t *frame_skip_number_array = NULL; @@ -1006,7 +1006,7 @@ void set_replay_frame_skip_number(struct dc_link *link, if (false == link->replay_settings.config.frame_skip_supported) return; - if (flicker_free_refresh_rate_mhz == 0 || coasting_vtotal_refresh_rate_mhz == 0) + if (flicker_free_refresh_rate_uhz == 0 || coasting_vtotal_refresh_rate_uhz == 0) return; if (is_defer) @@ -1017,7 +1017,7 @@ void set_replay_frame_skip_number(struct dc_link *link, if (frame_skip_number_array == NULL) return; - frame_skip_number = coasting_vtotal_refresh_rate_mhz / flicker_free_refresh_rate_mhz; + frame_skip_number = (coasting_vtotal_refresh_rate_uhz + 500000) / flicker_free_refresh_rate_uhz; if (frame_skip_number >= 1) frame_skip_number_array[type] = frame_skip_number - 1; From 70840d70000e3a1d6d9c54e6f5ea29fd9328774b Mon Sep 17 00:00:00 2001 From: Ray Wu Date: Thu, 23 Apr 2026 15:06:12 +0800 Subject: [PATCH 33/71] drm/amd/display: Fix white screen on boot with OLED panel [Why] During mode change, replay_event_general_ui may remain set on the old stream while replay_event_hw_programming is set. This can re-enable Replay too early before hardware programming is complete. [How] Clear replay_event_general_ui in the mode-change path when setting replay_event_hw_programming to keep Replay blocked until programming finishes, avoiding white screen on OLED panels after boot. Reviewed-by: Sunpeng Li Signed-off-by: Ray Wu Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d590f0df6abd..efb1ae1f66a0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10090,8 +10090,6 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm, amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false, psr_event_hw_programming, false); - amdgpu_dm_replay_set_event(dm, acrtc_state->stream, true, - replay_event_general_ui, true); amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false, replay_event_hw_programming, false); } @@ -10620,6 +10618,8 @@ static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_commit *state, psr_event_hw_programming, true); amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true, replay_event_hw_programming, true); + amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, false, + replay_event_general_ui, false); } } @@ -10673,6 +10673,18 @@ static void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_commit *state, mod_power_notify_mode_change(dm->power_module, dm_new_crtc_state->stream, false); + + /* + * Block PSR / Replay on the new stream until display settles post-modeset. + * These events will be cleared by amdgpu_dm_enable_self_refresh() once + * allow_sr_entry becomes true. + */ + amdgpu_dm_psr_set_event(dm, dm_new_crtc_state->stream, true, + psr_event_hw_programming, true); + + amdgpu_dm_replay_set_event(dm, dm_new_crtc_state->stream, true, + replay_event_hw_programming | replay_event_general_ui, + true); } } From 5eb2fdafeb6f4a442643b77a21a4c9e70586a146 Mon Sep 17 00:00:00 2001 From: Tom Chung Date: Tue, 28 Apr 2026 16:41:12 +0800 Subject: [PATCH 34/71] drm/amd/display: Fix CRC open failure during active rendering [Why] Opening the CRC data file during active rendering can fail with -EINVAL. The wait for commit->hw_done returns remaining jiffies on success, but the CRC path was treating that as an error. [How] Handle wait_for_completion_interruptible_timeout() correctly: positive return as success, 0 as timeout, and negative as error. Reviewed-by: Ray Wu Signed-off-by: Tom Chung Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 4155984201c6..5adbb0f6a0c8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -613,8 +613,13 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) */ ret = wait_for_completion_interruptible_timeout( &commit->hw_done, 10 * HZ); - if (ret) + if (ret < 0) goto cleanup; + + if (ret == 0) { + ret = -ETIMEDOUT; + goto cleanup; + } } enable = amdgpu_dm_is_valid_crc_source(source); From 55a79e4889bd62a7138d7bc3b9d70e1cfda2574b Mon Sep 17 00:00:00 2001 From: Gaghik Khachatrian Date: Sat, 25 Apr 2026 14:07:05 -0400 Subject: [PATCH 35/71] drm/amd/display: Fix signed/unsigned comparison mismatches [Why] Address signed/unsigned comparison warnings in DC paths to keep builds warning-clean and improve type safety at comparison boundaries. Most warnings came from signed loop/index temporaries compared against unsigned counters (for example pipe_count, num_states, and resource-cap counters), plus a small number of mixed signed/unsigned checks in writeback and clock-related assertions. [How] Aligned iterator and temporary variable types with the semantic type of the compared bounds. Used unsigned indices for loops bounded by unsigned counters, and retained signed types where values are semantically signed (for example arithmetic with sentinel or signed intermediate values). Where mixed signed/unsigned comparisons are intentional, applied explicit boundary casts or split assertions (for example non-negative signed-cap checks before unsigned comparisons) instead of broad type changes. No functional behavior changes are intended; this is a warning-resolution and type-alignment cleanup. Reviewed-by: Dillon Varone Signed-off-by: Gaghik Khachatrian Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +- .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 2 +- .../amd/display/dc/dml/dcn301/dcn301_fpu.c | 2 +- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 8 ++- .../dc/resource/dce100/dce100_resource.c | 10 +-- .../dc/resource/dce110/dce110_resource.c | 8 +-- .../dc/resource/dce112/dce112_resource.c | 4 +- .../dc/resource/dce120/dce120_resource.c | 6 +- .../dc/resource/dce80/dce80_resource.c | 8 +-- .../dc/resource/dcn10/dcn10_resource.c | 15 ++--- .../dc/resource/dcn20/dcn20_resource.c | 60 +++++++++--------- .../dc/resource/dcn21/dcn21_resource.c | 26 ++++---- .../dc/resource/dcn30/dcn30_resource.c | 63 ++++++++++--------- .../dc/resource/dcn301/dcn301_resource.c | 31 ++++----- .../dc/resource/dcn302/dcn302_resource.c | 22 +++---- .../dc/resource/dcn303/dcn303_resource.c | 22 +++---- .../dc/resource/dcn31/dcn31_resource.c | 30 ++++----- .../dc/resource/dcn314/dcn314_resource.c | 26 ++++---- .../dc/resource/dcn315/dcn315_resource.c | 37 +++++------ .../dc/resource/dcn316/dcn316_resource.c | 29 ++++----- .../dc/resource/dcn32/dcn32_resource.c | 25 ++++---- .../resource/dcn32/dcn32_resource_helpers.c | 6 +- .../dc/resource/dcn321/dcn321_resource.c | 22 +++---- .../dc/resource/dcn35/dcn35_resource.c | 26 ++++---- .../dc/resource/dcn351/dcn351_resource.c | 26 ++++---- .../dc/resource/dcn36/dcn36_resource.c | 26 ++++---- .../dc/resource/dcn401/dcn401_resource.c | 32 +++++----- .../dc/resource/dcn42/dcn42_resource.c | 40 ++++++------ 28 files changed, 317 insertions(+), 301 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 92190ea451e8..4cd9da65f309 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3844,7 +3844,7 @@ static void program_cursor_attributes_sequence( struct pipe_ctx *pipe_to_program = NULL; bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); - for (k = 0; k < dc->res_pool->pipe_count; k++) { + for (k = 0; k < (int)dc->res_pool->pipe_count; k++) { struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k]; if (tmp_pipe->stream != stream) @@ -3892,7 +3892,7 @@ static void program_cursor_position_sequence( struct pipe_ctx *pipe_to_program = NULL; bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc); - for (k = 0; k < dc->res_pool->pipe_count; k++) { + for (k = 0; k < (int)dc->res_pool->pipe_count; k++) { struct pipe_ctx *tmp_pipe = &context->res_ctx.pipe_ctx[k]; if (tmp_pipe->stream != stream || @@ -4082,7 +4082,7 @@ static void commit_planes_do_stream_update_sequence(struct dc *dc, *num_steps = 0; // Initialize to 0 // Stream updates - for (j = 0; j < dc->res_pool->pipe_count; j++) { + for (j = 0; j < (int)dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && pipe_ctx->stream == stream) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index fac5a50fefb2..71710d96ffe3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -2217,7 +2217,7 @@ static void calculate_wm_set_for_vlevel(int vlevel, { double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; - ASSERT(vlevel < dml->soc.num_states); + ASSERT(vlevel < (int)dml->soc.num_states); /* only pipe 0 is read for voltage and dcf/soc clocks */ pipes[0].clks_cfg.voltage = vlevel; pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c index 81ef95f51d05..c4b73acd7140 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c @@ -298,7 +298,7 @@ static void calculate_wm_set_for_vlevel(int vlevel, { double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; - ASSERT(vlevel < dml->soc.num_states); + ASSERT(vlevel < (int)dml->soc.num_states); /* only pipe 0 is read for voltage and dcf/soc clocks */ pipes[0].clks_cfg.voltage = vlevel; pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index a2c8d4b21ac3..3c70d685ba65 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -262,7 +262,7 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx, struct dc *dc = pipe_ctx->stream->ctx->dc; struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; bool result = false; - int acquired_rmu = 0; + uint32_t acquired_rmu = 0; int mpcc_id_projected = 0; const struct pwl_params *shaper_lut = NULL; @@ -439,7 +439,7 @@ static void dcn30_set_writeback( ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); ASSERT(wb_info->wb_enabled); ASSERT(wb_info->mpcc_inst >= 0); - ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); + ASSERT(wb_info->mpcc_inst < (int)dc->res_pool->mpcc_count); mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; mcif_buf_params = &wb_info->mcif_buf_params; @@ -593,7 +593,9 @@ void dcn30_program_all_writeback_pipes_in_tree( } ASSERT(stream_status); - ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); + // Assert non-negative signed capacity first. + ASSERT(dc->res_pool->res_cap->num_dwb >= 0); + ASSERT(stream->num_wb_info <= (unsigned int)dc->res_pool->res_cap->num_dwb); /* For each writeback pipe */ for (i_wb = 0; i_wb < stream->num_wb_info; i_wb++) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index caafebe92129..b92d4f378d60 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -804,7 +804,7 @@ static void dce100_resource_destruct(struct dce110_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -869,7 +869,7 @@ enum dc_status dce100_validate_bandwidth( enum dc_validate_mode validate_mode) { (void)validate_mode; - int i; + unsigned int i; bool at_least_one_pipe = false; struct dc_stream_state *stream = NULL; const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000); @@ -978,7 +978,7 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link( const struct resource_pool *pool, struct dc_stream_state *stream) { - int i; + unsigned int i; int j = -1; struct dc_link *link = stream->link; enum engine_id preferred_engine = link->link_enc->preferred_engine; @@ -995,7 +995,7 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link( /* Store first available for MST second display * in daisy chain use case */ - j = i; + j = (int)i; if (pool->stream_enc[i]->id == preferred_engine) return pool->stream_enc[i]; } @@ -1175,7 +1175,7 @@ static bool dce100_resource_construct( } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce100_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c index 8a0b4ef2977d..19252b25bce0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c @@ -839,7 +839,7 @@ static void dce110_resource_destruct(struct dce110_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1213,7 +1213,7 @@ struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link( const struct resource_pool *pool, struct dc_stream_state *stream) { - int i; + unsigned int i; int j = -1; struct dc_link *link = stream->link; @@ -1223,7 +1223,7 @@ struct stream_encoder *dce110_find_first_free_match_stream_enc_for_link( /* Store first available for MST second display * in daisy chain use case */ - j = i; + j = (int)i; if (pool->stream_enc[i]->id == link->link_enc->preferred_engine) return pool->stream_enc[i]; @@ -1492,7 +1492,7 @@ static bool dce110_resource_construct( } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce110_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c index 458b14e4cb97..1deba53363e5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c @@ -804,7 +804,7 @@ static void dce112_resource_destruct(struct dce110_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1382,7 +1382,7 @@ static bool dce112_resource_construct( } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce112_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c index 56bbf9dc1691..38d3b87529b0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c @@ -626,7 +626,7 @@ static void dce120_resource_destruct(struct dce110_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -927,7 +927,7 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc) struct dm_pp_clock_levels_with_latency eng_clks = {0}; struct dm_pp_clock_levels_with_latency mem_clks = {0}; struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; - int i; + unsigned int i; unsigned int clk; unsigned int latency; /*original logic in dal3*/ @@ -1227,7 +1227,7 @@ static bool dce120_resource_construct( j++; } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce120_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index 6c00497e9a01..26820d35478a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -854,7 +854,7 @@ static void dce80_resource_destruct(struct dce110_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1058,7 +1058,7 @@ static bool dce80_construct( } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce80_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1258,7 +1258,7 @@ static bool dce81_construct( } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce80_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1456,7 +1456,7 @@ static bool dce83_construct( } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dce80_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index 943635c4fbb8..db1b6a1b92e8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -976,7 +976,7 @@ static void dcn10_resource_destruct(struct dcn10_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); kfree(pool->base.hw_i2cs[i]); @@ -1181,7 +1181,8 @@ static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_st { if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && caps->max_video_width != 0 - && plane_state->src_rect.width > caps->max_video_width) + && plane_state->src_rect.width > 0 + && (unsigned int)plane_state->src_rect.width > caps->max_video_width) return DC_FAIL_SURFACE_VALIDATE; return DC_OK; @@ -1266,7 +1267,7 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( const struct resource_pool *pool, struct dc_stream_state *stream) { - int i; + unsigned int i; int j = -1; struct dc_link *link = stream->link; @@ -1278,7 +1279,7 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( */ if (pool->stream_enc[i]->id != ENGINE_ID_VIRTUAL) - j = i; + j = (int)i; if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id == link->link_enc->preferred_engine) @@ -1340,7 +1341,7 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx) static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) { - int i; + unsigned int i; if (clks->num_levels == 0) return false; @@ -1358,7 +1359,7 @@ static bool dcn10_resource_construct( struct dc *dc, struct dcn10_resource_pool *pool) { - int i; + unsigned int i; int j; struct dc_context *ctx = dc->ctx; uint32_t pipe_fuses = read_pipe_fuses(ctx); @@ -1653,7 +1654,7 @@ static bool dcn10_resource_construct( j++; } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dcn10_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index 4bc7777be60e..95abc4c38eae 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -1120,7 +1120,7 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1156,7 +1156,7 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1169,19 +1169,19 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1415,7 +1415,7 @@ enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_stream_state *dc_stream) { enum dc_status result = DC_OK; - int i; + unsigned int i; /* Get a DSC if required and available */ for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -1636,7 +1636,8 @@ void dcn20_set_mcif_arb_params( { enum mmhubbub_wbif_mode wbif_mode; struct mcif_arb_params *wb_arb_params; - int i, j, dwb_pipe; + int j, dwb_pipe; + unsigned int i; /* Writeback MCIF_WB arbitration parameters */ dwb_pipe = 0; @@ -1680,7 +1681,7 @@ void dcn20_set_mcif_arb_params( bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) { - int i; + unsigned int i; /* Validate DSC config, dsc count validation is already done */ for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -1797,7 +1798,7 @@ void dcn20_merge_pipes_for_validate( struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; /* merge previously split odm pipes since mode support needs to make the decision */ for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -1864,7 +1865,8 @@ int dcn20_validate_apply_pipe_split_flags( int *split, bool *merge) { - int i, pipe_idx, vlevel_split; + unsigned int i; + int pipe_idx, vlevel_split; int plane_count = 0; bool force_split = false; bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID; @@ -1897,7 +1899,7 @@ int dcn20_validate_apply_pipe_split_flags( (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) ++plane_count; } - if (plane_count > dc->res_pool->pipe_count / 2) + if ((unsigned int)plane_count > dc->res_pool->pipe_count / 2) avoid_split = true; /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */ @@ -1923,12 +1925,12 @@ int dcn20_validate_apply_pipe_split_flags( if (!context->res_ctx.pipe_ctx[i].stream) continue; - for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) + for (vlevel_split = vlevel; (unsigned int)vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && v->ModeSupport[vlevel][0]) break; /* Impossible to not split this pipe */ - if (vlevel > context->bw_ctx.dml.soc.num_states) + if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) vlevel = vlevel_split; else max_mpc_comb = 0; @@ -2064,7 +2066,8 @@ bool dcn20_fast_validate_bw( bool out = false; int split[MAX_PIPES] = { 0 }; bool merge[MAX_PIPES] = { false }; - int pipe_cnt, i, pipe_idx, vlevel; + int pipe_cnt, pipe_idx, vlevel; + unsigned int i; ASSERT(pipes); if (!pipes) @@ -2083,7 +2086,7 @@ bool dcn20_fast_validate_bw( vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); - if (vlevel > context->bw_ctx.dml.soc.num_states) + if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) goto validate_fail; vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); @@ -2289,7 +2292,7 @@ static const struct resource_funcs dcn20_res_pool_funcs = { bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -2311,7 +2314,7 @@ bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; ASSERT(pipe_count > 0); @@ -2569,7 +2572,7 @@ static bool dcn20_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; (unsigned int)i < pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2617,12 +2620,12 @@ static bool dcn20_resource_construct( if (!dc->debug.disable_pplib_wm_range) { struct pp_smu_wm_range_sets ranges = {0}; - int i = 0; + int j = 0; ranges.num_reader_wm_sets = 0; if (loaded_bb->num_states == 1) { - ranges.reader_wm_sets[0].wm_inst = (uint8_t)i; + ranges.reader_wm_sets[0].wm_inst = (uint8_t)j; ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; @@ -2630,15 +2633,14 @@ static bool dcn20_resource_construct( ranges.num_reader_wm_sets = 1; } else if (loaded_bb->num_states > 1) { - for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { - ranges.reader_wm_sets[i].wm_inst = (uint8_t)i; - ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; - ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; + for (j = 0; j < 4 && (unsigned int)j < loaded_bb->num_states; j++) { + ranges.reader_wm_sets[j].wm_inst = (uint8_t)j; + ranges.reader_wm_sets[j].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; + ranges.reader_wm_sets[j].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; DC_FP_START(); - dcn20_fpu_set_wm_ranges(i, &ranges, loaded_bb); + dcn20_fpu_set_wm_ranges(j, &ranges, loaded_bb); DC_FP_END(); - - ranges.num_reader_wm_sets = i + 1; + ranges.num_reader_wm_sets = j + 1; } ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; @@ -2664,7 +2666,7 @@ static bool dcn20_resource_construct( goto create_fail; /* mem input -> ipp -> dpp -> opp -> TG */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; (unsigned int)i < pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn20_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2792,7 +2794,7 @@ static bool dcn20_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; (unsigned int)i < dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 2; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 9001423da4f8..b653f951e104 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -684,7 +684,7 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -719,7 +719,7 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) dal_irq_service_destroy(&pool->base.irqs); } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -732,19 +732,19 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -804,7 +804,8 @@ bool dcn21_fast_validate_bw(struct dc *dc, bool out = false; int split[MAX_PIPES] = { 0 }; bool merge[MAX_PIPES] = { false }; - int pipe_cnt, i, pipe_idx, vlevel; + int pipe_cnt, pipe_idx, vlevel; + unsigned int i; ASSERT(pipes); if (!pipes) @@ -829,7 +830,7 @@ bool dcn21_fast_validate_bw(struct dc *dc, dm_allow_self_refresh_and_mclk_switch; vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); - if (vlevel > context->bw_ctx.dml.soc.num_states) { + if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) { if (allow_self_refresh_only) { /* @@ -842,7 +843,7 @@ bool dcn21_fast_validate_bw(struct dc *dc, context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = dm_allow_self_refresh; vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); - if (vlevel > context->bw_ctx.dml.soc.num_states) + if ((unsigned int)vlevel > context->bw_ctx.dml.soc.num_states) goto validate_fail; } else { goto validate_fail; @@ -1427,7 +1428,8 @@ static bool dcn21_resource_construct( struct dc *dc, struct dcn21_resource_pool *pool) { - int i, j; + unsigned int i; + int j; struct dc_context *ctx = dc->ctx; struct irq_service_init_data init_data; uint32_t pipe_fuses = read_pipe_fuses(ctx); @@ -1659,7 +1661,7 @@ static bool dcn21_resource_construct( j++; } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dcn21_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1703,11 +1705,11 @@ static bool dcn21_resource_construct( goto create_fail; } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn21_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { BREAK_TO_DEBUGGER(); - dm_error("DC: failed to create display stream compressor %d!\n", i); + dm_error("DC: failed to create display stream compressor %u!\n", i); goto create_fail; } } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 7ba02a453f2e..4a7f2c5d34e6 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -1111,7 +1111,7 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1147,7 +1147,7 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1160,19 +1160,19 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1195,7 +1195,7 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1250,7 +1250,7 @@ static struct hubp *dcn30_hubp_create( static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1274,7 +1274,7 @@ static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1355,7 +1355,8 @@ int dcn30_populate_dml_pipes_from_context( display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + int pipe_cnt; + unsigned int i; struct resource_context *res_ctx = &context->res_ctx; DC_FP_START(); @@ -1413,7 +1414,8 @@ void dcn30_set_mcif_arb_params( enum mmhubbub_wbif_mode wbif_mode; struct display_mode_lib *dml = &context->bw_ctx.dml; struct mcif_arb_params *wb_arb_params; - int i, j, dwb_pipe; + int j, dwb_pipe; + unsigned int i; /* Writeback MCIF_WB arbitration parameters */ dwb_pipe = 0; @@ -1669,7 +1671,8 @@ noinline bool dcn30_internal_validate_bw( int split[MAX_PIPES] = { 0 }; bool merge[MAX_PIPES] = { false }; bool newly_split[MAX_PIPES] = { false }; - int pipe_cnt, i, pipe_idx, vlevel = 0; + unsigned int i; + int pipe_cnt, pipe_idx, vlevel = 0; struct vba_vars_st *vba = &context->bw_ctx.dml.vba; ASSERT(pipes); @@ -1701,7 +1704,7 @@ noinline bool dcn30_internal_validate_bw( dm_allow_self_refresh_and_mclk_switch; vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); /* This may adjust vlevel and maxMpcComb */ - if (vlevel < context->bw_ctx.dml.soc.num_states) + if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states) vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); } if (allow_self_refresh_only && @@ -1719,7 +1722,7 @@ noinline bool dcn30_internal_validate_bw( dm_allow_self_refresh; vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); - if (vlevel < context->bw_ctx.dml.soc.num_states) { + if ((unsigned int)vlevel < context->bw_ctx.dml.soc.num_states) { memset(split, 0, sizeof(split)); memset(merge, 0, sizeof(merge)); vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge); @@ -2159,13 +2162,13 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params if (bw_params->clk_table.entries[0].memclk_mhz) { for (i = 0; i < MAX_NUM_DPM_LVL; i++) { - if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz) + if (bw_params->clk_table.entries[i].dcfclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; - if (bw_params->clk_table.entries[i].dispclk_mhz > dcn30_bb_max_clk.max_dispclk_mhz) + if (bw_params->clk_table.entries[i].dispclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dispclk_mhz) dcn30_bb_max_clk.max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; - if (bw_params->clk_table.entries[i].dppclk_mhz > dcn30_bb_max_clk.max_dppclk_mhz) + if (bw_params->clk_table.entries[i].dppclk_mhz > (unsigned int)dcn30_bb_max_clk.max_dppclk_mhz) dcn30_bb_max_clk.max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; - if (bw_params->clk_table.entries[i].phyclk_mhz > dcn30_bb_max_clk.max_phyclk_mhz) + if (bw_params->clk_table.entries[i].phyclk_mhz > (unsigned int)dcn30_bb_max_clk.max_phyclk_mhz) dcn30_bb_max_clk.max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; } @@ -2173,14 +2176,14 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params dcn30_fpu_update_max_clk(&dcn30_bb_max_clk); DC_FP_END(); - if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { + if ((unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz; num_dcfclk_sta_targets++; - } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { + } else if ((unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates for (i = 0; i < num_dcfclk_sta_targets; i++) { - if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) { + if (dcfclk_sta_targets[i] > (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) { dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz; break; } @@ -2232,7 +2235,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; } else { - if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { + if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) { dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; } else { @@ -2247,7 +2250,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params } while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && - optimal_dcfclk_for_uclk[j] <= dcn30_bb_max_clk.max_dcfclk_mhz) { + optimal_dcfclk_for_uclk[j] <= (unsigned int)dcn30_bb_max_clk.max_dcfclk_mhz) { dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; } @@ -2307,7 +2310,7 @@ static bool dcn30_resource_construct( struct dc *dc, struct dcn30_resource_pool *pool) { - int i; + unsigned int i; struct dc_context *ctx = dc->ctx; struct irq_service_init_data init_data; struct ddc_service_init_data ddc_init_data = {0}; @@ -2529,7 +2532,7 @@ static bool dcn30_resource_construct( } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { pool->base.opps[i] = dcn30_opp_create(ctx, i); if (pool->base.opps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2539,7 +2542,7 @@ static bool dcn30_resource_construct( } } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { pool->base.timing_generators[i] = dcn30_timing_generator_create( ctx, i); if (pool->base.timing_generators[i] == NULL) { @@ -2559,13 +2562,13 @@ static bool dcn30_resource_construct( } /* ABM */ - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { pool->base.multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); if (pool->base.multiple_abms[i] == NULL) { - dm_error("DC: failed to create abm for pipe %d!\n", i); + dm_error("DC: failed to create abm for pipe %u!\n", i); BREAK_TO_DEBUGGER(); goto create_fail; } @@ -2578,11 +2581,11 @@ static bool dcn30_resource_construct( goto create_fail; } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn30_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { BREAK_TO_DEBUGGER(); - dm_error("DC: failed to create display stream compressor %d!\n", i); + dm_error("DC: failed to create display stream compressor %u!\n", i); goto create_fail; } } @@ -2601,7 +2604,7 @@ static bool dcn30_resource_construct( } /* AUX and I2C */ - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dcn30_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index 05e59b6255f7..0ecd3a2fcebd 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1082,7 +1082,7 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1118,7 +1118,7 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1131,19 +1131,19 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1166,7 +1166,7 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1182,7 +1182,7 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1210,7 +1210,7 @@ static struct hubp *dcn301_hubp_create(struct dc_context *ctx, uint32_t inst) static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1234,7 +1234,7 @@ static bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *poo static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1444,7 +1444,8 @@ static bool dcn301_resource_construct( struct dc *dc, struct dcn301_resource_pool *pool) { - int i, j; + int j; + unsigned int i; struct dc_context *ctx = dc->ctx; struct irq_service_init_data init_data; uint32_t pipe_fuses = read_pipe_fuses(ctx); @@ -1676,13 +1677,13 @@ static bool dcn301_resource_construct( /* ABM (or ABMs for NV2x) */ /* TODO: */ - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { pool->base.multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask); if (pool->base.multiple_abms[i] == NULL) { - dm_error("DC: failed to create abm for pipe %d!\n", i); + dm_error("DC: failed to create abm for pipe %u!\n", i); BREAK_TO_DEBUGGER(); goto create_fail; } @@ -1696,11 +1697,11 @@ static bool dcn301_resource_construct( goto create_fail; } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn301_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { BREAK_TO_DEBUGGER(); - dm_error("DC: failed to create display stream compressor %d!\n", i); + dm_error("DC: failed to create display stream compressor %u!\n", i); goto create_fail; } } @@ -1719,7 +1720,7 @@ static bool dcn301_resource_construct( } /* AUX and I2C */ - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dcn301_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index 652b98aaa196..f7b3947a9091 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -738,7 +738,7 @@ static const struct dcn30_dwbc_mask dwbc30_mask = { static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -773,7 +773,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1036,7 +1036,7 @@ static void dcn302_resource_destruct(struct resource_pool *pool) } } - for (i = 0; i < pool->res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } @@ -1071,7 +1071,7 @@ static void dcn302_resource_destruct(struct resource_pool *pool) dal_irq_service_destroy(&pool->irqs); } - for (i = 0; i < pool->res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_ddc; i++) { if (pool->engines[i] != NULL) dce110_engine_destroy(&pool->engines[i]); if (pool->hw_i2cs[i] != NULL) { @@ -1084,19 +1084,19 @@ static void dcn302_resource_destruct(struct resource_pool *pool) } } - for (i = 0; i < pool->res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_opp; i++) { if (pool->opps[i] != NULL) pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); } - for (i = 0; i < pool->res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_timing_generator; i++) { if (pool->timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); pool->timing_generators[i] = NULL; } } - for (i = 0; i < pool->res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_dwb; i++) { if (pool->dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->dwbc[i])); pool->dwbc[i] = NULL; @@ -1120,7 +1120,7 @@ static void dcn302_resource_destruct(struct resource_pool *pool) if (pool->dp_clock_source != NULL) dcn20_clock_source_destroy(&pool->dp_clock_source); - for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_mpc_3dlut; i++) { if (pool->mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->mpc_lut[i]); pool->mpc_lut[i] = NULL; @@ -1371,7 +1371,7 @@ static bool dcn302_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->clk_src_count; i++) { + for (i = 0; i < (int)pool->clk_src_count; i++) { if (pool->clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -1416,7 +1416,7 @@ static bool dcn302_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->pipe_count; i++) { + for (i = 0; i < (int)pool->pipe_count; i++) { pool->hubps[i] = dcn302_hubp_create(ctx, i); if (pool->hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1526,7 +1526,7 @@ static bool dcn302_resource_construct( dc->caps.max_planes = pool->pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index b22e72a61393..429365f22622 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -699,7 +699,7 @@ static const struct dcn30_dwbc_mask dwbc30_mask = { static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -734,7 +734,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -980,7 +980,7 @@ static void dcn303_resource_destruct(struct resource_pool *pool) } } - for (i = 0; i < pool->res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } @@ -1015,7 +1015,7 @@ static void dcn303_resource_destruct(struct resource_pool *pool) dal_irq_service_destroy(&pool->irqs); } - for (i = 0; i < pool->res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_ddc; i++) { if (pool->engines[i] != NULL) dce110_engine_destroy(&pool->engines[i]); if (pool->hw_i2cs[i] != NULL) { @@ -1028,19 +1028,19 @@ static void dcn303_resource_destruct(struct resource_pool *pool) } } - for (i = 0; i < pool->res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_opp; i++) { if (pool->opps[i] != NULL) pool->opps[i]->funcs->opp_destroy(&pool->opps[i]); } - for (i = 0; i < pool->res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_timing_generator; i++) { if (pool->timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->timing_generators[i])); pool->timing_generators[i] = NULL; } } - for (i = 0; i < pool->res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_dwb; i++) { if (pool->dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->dwbc[i])); pool->dwbc[i] = NULL; @@ -1064,7 +1064,7 @@ static void dcn303_resource_destruct(struct resource_pool *pool) if (pool->dp_clock_source != NULL) dcn20_clock_source_destroy(&pool->dp_clock_source); - for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->res_cap->num_mpc_3dlut; i++) { if (pool->mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->mpc_lut[i]); pool->mpc_lut[i] = NULL; @@ -1303,7 +1303,7 @@ static bool dcn303_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->clk_src_count; i++) { + for (i = 0; i < (int)pool->clk_src_count; i++) { if (pool->clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -1348,7 +1348,7 @@ static bool dcn303_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->pipe_count; i++) { + for (i = 0; i < (int)pool->pipe_count; i++) { pool->hubps[i] = dcn303_hubp_create(ctx, i); if (pool->hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -1458,7 +1458,7 @@ static bool dcn303_resource_construct( dc->caps.max_planes = pool->pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index 573d2a680115..df3e35a6a0a5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -1146,7 +1146,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1412,7 +1412,7 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1446,7 +1446,7 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1459,19 +1459,19 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1494,7 +1494,7 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1510,7 +1510,7 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1546,7 +1546,7 @@ static struct hubp *dcn31_hubp_create( static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1570,7 +1570,7 @@ static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1651,7 +1651,7 @@ int dcn31x_populate_dml_pipes_from_context(struct dc *dc, enum dc_validate_mode validate_mode) { uint32_t pipe_cnt; - int i; + unsigned int i; dc_assert_fp_enabled(); @@ -1675,7 +1675,7 @@ int dcn31_populate_dml_pipes_from_context( display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + unsigned int i, pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = 0; bool upscaled = false; @@ -2076,7 +2076,7 @@ static bool dcn31_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2115,7 +2115,7 @@ static bool dcn31_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn31_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2252,7 +2252,7 @@ static bool dcn31_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index 7585151ffcde..74a14c0be20f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -1204,7 +1204,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1471,7 +1471,7 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1504,7 +1504,7 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) dal_irq_service_destroy(&pool->base.irqs); } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1517,19 +1517,19 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1552,7 +1552,7 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1568,7 +1568,7 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1604,7 +1604,7 @@ static struct hubp *dcn31_hubp_create( static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1628,7 +1628,7 @@ static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1996,7 +1996,7 @@ static bool dcn314_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2033,7 +2033,7 @@ static bool dcn314_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn31_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2163,7 +2163,7 @@ static bool dcn314_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 7f8e3304af31..30b2e73abd08 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -1145,7 +1145,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1413,7 +1413,7 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1447,7 +1447,7 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1460,19 +1460,19 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1495,7 +1495,7 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1511,7 +1511,7 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1547,7 +1547,7 @@ static struct hubp *dcn31_hubp_create( static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1571,7 +1571,7 @@ static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1666,7 +1666,7 @@ static int source_format_to_bpp (enum source_format_class SourcePixelFormat) static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context) { - int i; + unsigned int i; struct resource_context *res_ctx = &context->res_ctx; /* Only apply for dual stream scenarios with edp*/ @@ -1699,7 +1699,8 @@ static int dcn315_populate_dml_pipes_from_context( display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt, crb_idx, crb_pipes; + unsigned int i; + int pipe_cnt, crb_idx, crb_pipes; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = NULL; const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MIN_COMPBUF_SIZE_KB; @@ -1739,7 +1740,7 @@ static int dcn315_populate_dml_pipes_from_context( if (approx_det_segs_required_for_pstate <= 2 * DCN3_15_MAX_DET_SEGS) { bool split_required = approx_det_segs_required_for_pstate > DCN3_15_MAX_DET_SEGS; - split_required = split_required || timing->pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc); + split_required = split_required || (unsigned int)timing->pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc); split_required = split_required || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); /* Minimum 2 segments to allow mpc/odm combine if its used later */ @@ -1788,7 +1789,7 @@ static int dcn315_populate_dml_pipes_from_context( continue; } - bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) + bool split_required = (unsigned int)pipe->stream->timing.pix_clk_100hz >= (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc) || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120); if (remaining_det_segs > MIN_RESERVED_DET_SEGS && crb_pipes != 0) @@ -1825,7 +1826,7 @@ static int dcn315_populate_dml_pipes_from_context( (max_usable_det / DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB; } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120 - && pipe->stream->timing.pix_clk_100hz < dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { + && (unsigned int)pipe->stream->timing.pix_clk_100hz < (unsigned int)dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) { /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */ context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; pipes[0].pipe.src.unbounded_req_mode = true; @@ -2026,7 +2027,7 @@ static bool dcn315_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2065,7 +2066,7 @@ static bool dcn315_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn31_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2192,7 +2193,7 @@ static bool dcn315_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index a6dd1bb9da64..0a6dfb44e90d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -1138,7 +1138,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1408,7 +1408,7 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1442,7 +1442,7 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1455,19 +1455,19 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1490,7 +1490,7 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1506,7 +1506,7 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1539,7 +1539,7 @@ static struct hubp *dcn31_hubp_create( static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1563,7 +1563,7 @@ static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1644,7 +1644,8 @@ static int dcn316_populate_dml_pipes_from_context( display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + unsigned int i; + int pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = 0; const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_16_MIN_COMPBUF_SIZE_KB; @@ -1900,7 +1901,7 @@ static bool dcn316_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -1939,7 +1940,7 @@ static bool dcn316_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn31_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2058,7 +2059,7 @@ static bool dcn316_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index bf34fdf781dc..bc9523f55eb1 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -1419,7 +1419,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1449,7 +1449,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1462,19 +1462,19 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1497,7 +1497,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1513,7 +1513,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1539,7 +1539,7 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1567,7 +1567,7 @@ static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1902,7 +1902,8 @@ int dcn32_populate_dml_pipes_from_context( display_e2e_pipe_params_st *pipes, enum dc_validate_mode validate_mode) { - int i, pipe_cnt; + unsigned int i; + int pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = NULL; bool subvp_in_use = false; @@ -2376,7 +2377,7 @@ static bool dcn32_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2546,7 +2547,7 @@ static bool dcn32_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c index b2eac83ef02c..602a0e4e5dc0 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@ -382,7 +382,8 @@ void dcn32_determine_det_override(struct dc *dc, void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) { - int i, pipe_cnt; + unsigned int i; + int pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = 0; bool disable_unbounded_requesting = dc->debug.disable_z9_mpc || dc->debug.disable_unbounded_requesting; @@ -751,7 +752,8 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes) { - int i, pipe_cnt; + unsigned int i; + int pipe_cnt; struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *pipe = NULL; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index 5f5720a3953a..ede21363542a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -1400,7 +1400,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1429,7 +1429,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) dal_irq_service_destroy(&pool->base.irqs); } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1442,19 +1442,19 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1477,7 +1477,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1493,7 +1493,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1519,7 +1519,7 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1547,7 +1547,7 @@ static bool dcn321_dwbc_create(struct dc_context *ctx, struct resource_pool *poo static bool dcn321_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1875,7 +1875,7 @@ static bool dcn321_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2040,7 +2040,7 @@ static bool dcn321_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 82a5bdf38e8a..dcbfe18b484e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -1153,7 +1153,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1483,7 +1483,7 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1513,7 +1513,7 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1526,19 +1526,19 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1561,7 +1561,7 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1577,7 +1577,7 @@ static void dcn35_resource_destruct(struct dcn35_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1634,7 +1634,7 @@ static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx) static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1672,7 +1672,7 @@ static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -2037,7 +2037,7 @@ static bool dcn35_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2089,7 +2089,7 @@ static bool dcn35_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn35_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2221,7 +2221,7 @@ static bool dcn35_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index a4922df2f8d6..7a6e8e6f0ea6 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -1133,7 +1133,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1463,7 +1463,7 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1493,7 +1493,7 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1506,19 +1506,19 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1541,7 +1541,7 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1557,7 +1557,7 @@ static void dcn351_resource_destruct(struct dcn351_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1614,7 +1614,7 @@ static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx) static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1652,7 +1652,7 @@ static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -2009,7 +2009,7 @@ static bool dcn351_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2061,7 +2061,7 @@ static bool dcn351_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn35_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2193,7 +2193,7 @@ static bool dcn351_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index 5cc52914e32b..83f2fd660789 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -1140,7 +1140,7 @@ static struct link_encoder *dcn31_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if (((unsigned int)eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc_obj(struct dcn20_link_encoder); @@ -1470,7 +1470,7 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } @@ -1500,7 +1500,7 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1513,19 +1513,19 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1548,7 +1548,7 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1564,7 +1564,7 @@ static void dcn36_resource_destruct(struct dcn36_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1621,7 +1621,7 @@ static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx) static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1659,7 +1659,7 @@ static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -2007,7 +2007,7 @@ static bool dcn36_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2059,7 +2059,7 @@ static bool dcn36_resource_construct( } /* HUBPs, DPPs, OPPs and TGs */ - for (i = 0; i < pool->base.pipe_count; i++) { + for (i = 0; i < (int)pool->base.pipe_count; i++) { pool->base.hubps[i] = dcn35_hubp_create(ctx, i); if (pool->base.hubps[i] == NULL) { BREAK_TO_DEBUGGER(); @@ -2191,7 +2191,7 @@ static bool dcn36_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 22ce58250db3..e24d908bcf68 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1425,7 +1425,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn401_dsc_destroy(&pool->base.dscs[i]); } @@ -1455,7 +1455,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1468,19 +1468,19 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1503,7 +1503,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1519,7 +1519,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1545,7 +1545,7 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1575,7 +1575,7 @@ static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *poo static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1792,11 +1792,11 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) pixel_clk_params->dio_se_pix_per_cycle = 2; } else if (dc_is_dp_signal(stream->signal)) { /* round up to nearest power of 2, or max at 8 pixels per cycle */ - if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { pixel_clk_params->dio_se_pix_per_cycle = 8; - } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + } else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { pixel_clk_params->dio_se_pix_per_cycle = 4; - } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + } else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { pixel_clk_params->dio_se_pix_per_cycle = 2; } else { pixel_clk_params->dio_se_pix_per_cycle = 1; @@ -1806,10 +1806,10 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) int dcn401_get_power_profile(const struct dc_state *context) { - int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000; + unsigned int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000; int dpm_level = 0; - for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { + for (unsigned int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 || uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) break; @@ -2096,7 +2096,7 @@ static bool dcn401_resource_construct( CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); - for (i = 0; i < pool->base.clk_src_count; i++) { + for (i = 0; i < (int)pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] == NULL) { dm_error("DC: failed to create clock sources!\n"); BREAK_TO_DEBUGGER(); @@ -2258,7 +2258,7 @@ static bool dcn401_resource_construct( dc->caps.max_planes = pool->base.pipe_count; - for (i = 0; i < dc->caps.max_planes; ++i) + for (i = 0; i < (int)dc->caps.max_planes; ++i) dc->caps.planes[i] = plane_cap; dc->caps.max_odm_combine_factor = 4; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index c013a6483f5d..57c6e81280bc 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -1416,7 +1416,7 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn42_dsc_destroy(&pool->base.dscs[i]); } @@ -1445,7 +1445,7 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) dal_irq_service_destroy(&pool->base.irqs); } - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { if (pool->base.engines[i] != NULL) dce110_engine_destroy(&pool->base.engines[i]); if (pool->base.hw_i2cs[i] != NULL) { @@ -1458,19 +1458,19 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_opp; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { if (pool->base.opps[i] != NULL) pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.timing_generators[i] != NULL) { kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) { if (pool->base.dwbc[i] != NULL) { kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); pool->base.dwbc[i] = NULL; @@ -1493,7 +1493,7 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) } } - for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { if (pool->base.mpc_lut[i] != NULL) { dc_3dlut_func_release(pool->base.mpc_lut[i]); pool->base.mpc_lut[i] = NULL; @@ -1509,7 +1509,7 @@ static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) pool->base.dp_clock_source = NULL; } - for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { if (pool->base.multiple_abms[i] != NULL) dce_abm_destroy(&pool->base.multiple_abms[i]); } @@ -1580,11 +1580,11 @@ static void dcn42_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) pixel_clk_params->dio_se_pix_per_cycle = 2; } else if (dc_is_dp_signal(stream->signal)) { /* round up to nearest power of 2, or max at 8 pixels per cycle */ - if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { pixel_clk_params->dio_se_pix_per_cycle = 8; - } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { pixel_clk_params->dio_se_pix_per_cycle = 4; - } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { pixel_clk_params->dio_se_pix_per_cycle = 2; } else { pixel_clk_params->dio_se_pix_per_cycle = 1; @@ -1594,7 +1594,7 @@ static void dcn42_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) static bool dcn42_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { @@ -1631,7 +1631,7 @@ static void dcn42_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, static bool dcn42_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) { - int i; + unsigned int i; uint32_t pipe_count = pool->res_cap->num_dwb; for (i = 0; i < pipe_count; i++) { @@ -1753,7 +1753,7 @@ static struct link_encoder *dcn42_link_enc_create_minimal( { struct dcn20_link_encoder *enc20; - if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + if ((unsigned int)(eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) return NULL; enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); @@ -1831,7 +1831,7 @@ static bool dcn42_resource_construct( struct dc *dc, struct dcn42_resource_pool *pool) { - int i, j; + unsigned int i, j; struct dc_context *ctx = dc->ctx; struct irq_service_init_data init_data; uint32_t pipe_fuses; @@ -1867,7 +1867,7 @@ static bool dcn42_resource_construct( num_pipes = pool->base.res_cap->num_dpp; pipe_fuses = read_pipe_fuses(ctx); - for (i = 0; i < pool->base.res_cap->num_dpp; i++) + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dpp; i++) if (pipe_fuses & 1 << i) num_pipes--; @@ -2121,7 +2121,7 @@ static bool dcn42_resource_construct( } /* HUBPs, DPPs, OPPs, TGs, ABMs */ - for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { + for (i = 0, j = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { /* if pipe is disabled, skip instance of HW pipe, * i.e, skip ASIC register instance */ @@ -2165,7 +2165,7 @@ static bool dcn42_resource_construct( &abm_shift, &abm_mask); if (pool->base.multiple_abms[j] == NULL) { - dm_error("DC: failed to create abm for pipe %d!\n", i); + dm_error("DC: failed to create abm for pipe %u!\n", i); BREAK_TO_DEBUGGER(); goto create_fail; } @@ -2200,11 +2200,11 @@ static bool dcn42_resource_construct( } /* DSCs */ - for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn42_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { BREAK_TO_DEBUGGER(); - dm_error("DC: failed to create display stream compressor %d!\n", i); + dm_error("DC: failed to create display stream compressor %u!\n", i); goto create_fail; } } @@ -2224,7 +2224,7 @@ static bool dcn42_resource_construct( } /* AUX and I2C */ - for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { pool->base.engines[i] = dcn42_aux_engine_create(ctx, i); if (pool->base.engines[i] == NULL) { From 12b3bda41a9aa240b164e6cc882df49dce187ec9 Mon Sep 17 00:00:00 2001 From: Gaghik Khachatrian Date: Sun, 26 Apr 2026 16:22:34 -0400 Subject: [PATCH 36/71] drm/amd/display: Fix compiler warnings in dml2 [Why & How] In dml2_translation_helper.c, rename the inner loop index inside dml2_init_soc_states() for several project cases to avoid shadowing the outer function-scope index variable. In display_mode_core.c, replace shift-based power-of-two expressions used to compute dpte_row_height and dpte_row_height_linear with an equivalent floating-point power function, consistent with existing usage elsewhere in the file. Behavior for valid inputs is preserved in both cases. Reviewed-by: Dillon Varone Signed-off-by: Gaghik Khachatrian Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c index 16514f1e4ed9..241406e9e85a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c @@ -2626,18 +2626,18 @@ static dml_uint_t CalculateVMAndRowBytes( *PixelPTEBytesPerRow_one_row_per_frame = (dml_uint_t)((dml_float_t) *dpte_row_width_ub_one_row_per_frame / (dml_float_t) *PixelPTEReqWidth * *PTERequestSize); if (SurfaceTiling == dml_sw_linear) { - *dpte_row_height = (dml_uint_t)(dml_min(128, 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1))); + *dpte_row_height = (dml_uint_t)(dml_min(128, (dml_uint_t)dml_pow(2.0, (int)dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)))); dml_print("DML::%s: dpte_row_height term 1 = %u\n", __func__, PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch); dml_print("DML::%s: dpte_row_height term 2 = %f\n", __func__, dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch)); dml_print("DML::%s: dpte_row_height term 3 = %f\n", __func__, dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); - dml_print("DML::%s: dpte_row_height term 4 = %u\n", __func__, 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)); + dml_print("DML::%s: dpte_row_height term 4 = %u\n", __func__, (dml_uint_t)dml_pow(2.0, (int)dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1))); dml_print("DML::%s: dpte_row_height = %u\n", __func__, *dpte_row_height); *dpte_row_width_ub = (dml_uint_t)(dml_ceil(((dml_float_t) Pitch * (dml_float_t) *dpte_row_height - 1), (dml_float_t) *PixelPTEReqWidth) + *PixelPTEReqWidth); *PixelPTEBytesPerRow = (dml_uint_t)((dml_float_t) *dpte_row_width_ub / (dml_float_t) *PixelPTEReqWidth * *PTERequestSize); // VBA_DELTA, VBA doesn't have programming value for pte row height linear. - *dpte_row_height_linear = 1 << (dml_uint_t) dml_floor(dml_log2(PTEBufferSizeInRequests * PixelPTEReqWidth_linear / Pitch), 1); + *dpte_row_height_linear = (dml_uint_t)dml_pow(2.0, (int)dml_floor(dml_log2(PTEBufferSizeInRequests * PixelPTEReqWidth_linear / Pitch), 1)); if (*dpte_row_height_linear > 128) *dpte_row_height_linear = 128; From da11ed03e1c9f11e700cd59f18754715f27ae14d Mon Sep 17 00:00:00 2001 From: Gaghik Khachatrian Date: Sun, 26 Apr 2026 13:35:52 -0400 Subject: [PATCH 37/71] drm/amd/display: Fix multiple compiler warnings [Why] Unreachable Code; Copy Constructor Deleted; Local Declaration Hides Parameter; Local Declaration Hides Outer Scope; Uninitialized or Suspicious Memory Use. [How] - Removed or refactored unreachable code paths - Ensured proper copy constructors in C++ classes - Renamed local variables that shadowed function parameters - Renamed inner loop/block variables to avoid shadowing outer scope Fixed in 8 files across several FPU layers Also fixed in color_gamma and cs_funcs modules - Reordered guard conditions to validate pipe type before accessing stream - Ensures safe memory access patterns in DC DMUB service layer All changes maintain backward compatibility and preserve functional behavior. Reviewed-by: Dillon Varone Signed-off-by: Gaghik Khachatrian Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +++--- .../gpu/drm/amd/display/dc/core/dc_state.c | 6 ++-- .../gpu/drm/amd/display/dc/core/dc_stream.c | 4 +-- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 3 +- .../dc/dml/dcn21/display_mode_vba_21.c | 8 +++--- .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 4 +-- .../amd/display/dc/dml/dcn314/dcn314_fpu.c | 10 +++---- .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 13 +++++---- .../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 10 +++---- .../amd/display/dc/dml/dcn351/dcn351_fpu.c | 10 +++---- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 +-- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 3 ++ .../amd/display/modules/color/color_gamma.c | 28 +++++++++---------- 13 files changed, 57 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 4cd9da65f309..4dc76935f8aa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -4975,7 +4975,7 @@ static void commit_planes_for_stream(struct dc *dc, if (!pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe && should_update_pipe_for_stream(context, pipe_ctx, stream)) { - struct dc_stream_status *stream_status = NULL; + struct dc_stream_status *pipe_stream_status = NULL; if (!pipe_ctx->plane_state) continue; @@ -4984,12 +4984,12 @@ static void commit_planes_for_stream(struct dc *dc, if (update_type == UPDATE_TYPE_FAST) continue; - stream_status = + pipe_stream_status = stream_get_status(context, pipe_ctx->stream); - if (dc->hwss.apply_ctx_for_surface && stream_status) + if (dc->hwss.apply_ctx_for_surface && pipe_stream_status) dc->hwss.apply_ctx_for_surface( - dc, pipe_ctx->stream, stream_status->plane_count, context); + dc, pipe_ctx->stream, pipe_stream_status->plane_count, context); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c index ad2c0a93a41b..7edeed52cc32 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c @@ -218,13 +218,13 @@ struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *p } if (dc->caps.dcmode_power_limits_present) { - bool status; + bool dc_power_status; DC_FP_START(); - status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source); + dc_power_status = dml2_create(dc, &dc->dml2_dc_power_options, &state->bw_ctx.dml2_dc_power_source); DC_FP_END(); - if (!status) { + if (!dc_power_status) { dc_state_release(state); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 21dcb47f671a..434654e903b1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -602,7 +602,7 @@ bool dc_stream_add_writeback(struct dc *dc, if (dc->hwss.enable_writeback) { struct dc_stream_status *stream_status = dc_stream_get_status(stream); - struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; if (stream_status) dwb->otg_inst = stream_status->primary_otg_inst; } @@ -614,7 +614,7 @@ bool dc_stream_add_writeback(struct dc *dc, /* enable writeback */ if (dc->hwss.enable_writeback) { - struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; + dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; if (dwb->funcs->is_enabled(dwb)) { /* writeback pipe already enabled, only need to update */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 9d4e7badb9f9..0ee5c0c5545c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -488,12 +488,11 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; - if (!resource_is_pipe_type(pipe, OTG_MASTER)) + if (!resource_is_pipe_type(pipe, OTG_MASTER) || !pipe->stream) continue; stream_status = dc_state_get_stream_status(context, pipe->stream); if (stream_status && stream_status->fpo_in_use) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; uint8_t min_refresh_in_hz; min_refresh_in_hz = (uint8_t)((pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index df23ced2ff5a..3ff71751db1e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -4809,14 +4809,14 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l mode_lib->vba.MaximumReadBandwidthWithoutPrefetch = 0.0; mode_lib->vba.MaximumReadBandwidthWithPrefetch = 0.0; for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes - 1; k++) { - unsigned int m; + unsigned int cursor_idx; locals->cursor_bw[k] = 0; locals->cursor_bw_pre[k] = 0; - for (m = 0; m < mode_lib->vba.NumberOfCursors[k]; m++) { - locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] + for (cursor_idx = 0; cursor_idx < mode_lib->vba.NumberOfCursors[k]; cursor_idx++) { + locals->cursor_bw[k] = mode_lib->vba.CursorWidth[k][cursor_idx] * mode_lib->vba.CursorBPP[k][cursor_idx] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * mode_lib->vba.VRatio[k]; - locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][m] * mode_lib->vba.CursorBPP[k][m] + locals->cursor_bw_pre[k] = mode_lib->vba.CursorWidth[k][cursor_idx] * mode_lib->vba.CursorBPP[k][cursor_idx] / 8.0 / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]) * locals->VRatioPreY[i][j][k]; } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c index 79c567b6806e..0ba388c6aec1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c @@ -721,9 +721,9 @@ void dcn3_fpu_build_wm_range_table(struct clk_mgr *base) base->bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; } -void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip) +void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *soc_bb) { - (void)dcn3_0_ip; + (void)soc_bb; dc_assert_fp_enabled(); if (dc->ctx->dc_bios->funcs->get_soc_bb_info) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c index 29334772408e..2f9ae79da731 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c @@ -410,15 +410,15 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c context->bw_ctx.dml.ip.odm_combine_4to1_supported = true; for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream) + if (!cur_pipe->stream) continue; - if (pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && - pipe->stream->apply_seamless_boot_optimization) { + if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && + cur_pipe->stream->apply_seamless_boot_optimization) { - if (pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { + if (cur_pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; break; } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index a97e38aa7fed..03e49d298a85 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -2216,7 +2216,7 @@ bool dcn32_internal_validate_bw(struct dc *dc, if (repopulate_pipes) { int flag_max_mpc_comb = vba->maxMpcComb; int flag_vlevel = vlevel; - int i; + int j; pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); if (!dc->config.enable_windowed_mpo_odm) @@ -2231,19 +2231,20 @@ bool dcn32_internal_validate_bw(struct dc *dc, dm_prefetch_support_uclk_fclk_and_stutter_if_possible; vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); + const int num_states = (int)context->bw_ctx.dml.soc.num_states; - if (vlevel == context->bw_ctx.dml.soc.num_states) { + if (vlevel == num_states) { /* failed after DET size changes */ goto validate_fail; } else if (flag_max_mpc_comb == 0 && flag_max_mpc_comb != context->bw_ctx.dml.vba.maxMpcComb) { /* check the context constructed with pipe split flags is still valid*/ bool flags_valid = false; - for (i = flag_vlevel; i < (int)context->bw_ctx.dml.soc.num_states; i++) { - if (vba->ModeSupport[i][flag_max_mpc_comb]) { + for (j = flag_vlevel; j < (int)context->bw_ctx.dml.soc.num_states; j++) { + if (vba->ModeSupport[j][flag_max_mpc_comb]) { vba->maxMpcComb = flag_max_mpc_comb; - vba->VoltageLevel = i; - vlevel = i; + vba->VoltageLevel = j; + vlevel = j; flags_valid = true; break; } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index bef2b0bcfcf0..c15fbc18bfdf 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -551,16 +551,16 @@ int dcn35_populate_dml_pipes_from_context_fpu(struct dc *dc, } for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream) + if (!cur_pipe->stream) continue; - if (pipe->stream->signal == SIGNAL_TYPE_EDP && + if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && - pipe->stream->apply_seamless_boot_optimization) { + cur_pipe->stream->apply_seamless_boot_optimization) { - if (pipe->stream->apply_boot_odm_mode == + if (cur_pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c index 9545d946215b..6552b26de845 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c @@ -583,16 +583,16 @@ int dcn351_populate_dml_pipes_from_context_fpu(struct dc *dc, } for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream) + if (!cur_pipe->stream) continue; - if (pipe->stream->signal == SIGNAL_TYPE_EDP && + if (cur_pipe->stream->signal == SIGNAL_TYPE_EDP && dc->debug.seamless_boot_odm_combine && - pipe->stream->apply_seamless_boot_optimization) { + cur_pipe->stream->apply_seamless_boot_optimization) { - if (pipe->stream->apply_boot_odm_mode == + if (cur_pipe->stream->apply_boot_odm_mode == dm_odm_combine_policy_2to1) { context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 13e0e9ceeae3..305860cb775a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -3636,8 +3636,8 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) if (dc->hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied) { struct dce_hwseq *hwseq = dc->hwseq; - struct timing_generator *tg = dc->res_pool->timing_generators[0]; - unsigned int cur_frame = tg->funcs->get_frame_count(tg); + struct timing_generator *wa_tg = dc->res_pool->timing_generators[0]; + unsigned int cur_frame = wa_tg->funcs->get_frame_count(wa_tg); if (cur_frame != hwseq->wa_state.disallow_self_refresh_during_multi_plane_transition_applied_on_frame) { struct hubbub *hubbub = dc->res_pool->hubbub; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index d4a118e047b7..c6ec58367678 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1952,6 +1952,9 @@ void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx) * This is meant to work around a known HW issue where VREADY will cancel the pending 3DLUT_ENABLE signal regardless * of whether OTG lock is currently being held or not. */ + if (!pipe_ctx) + return; + struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL }; struct pipe_ctx *odm_pipe, *mpc_pipe; int i, wa_pipe_ct = 0; diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c index beb97cbdad6e..03d88e78165d 100644 --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c @@ -690,7 +690,7 @@ static bool find_software_points( static bool build_custom_gamma_mapping_coefficients_worker( const struct dc_gamma *ramp, struct pixel_gamma_point *coeff, - const struct hw_x_point *coordinates_x, + const struct hw_x_point *hw_coordinates_x, const struct gamma_pixel *axis_x, enum channel_name channel, uint32_t number_of_points) @@ -712,11 +712,11 @@ static bool build_custom_gamma_mapping_coefficients_worker( struct fixed31_32 right_pos; if (channel == CHANNEL_NAME_RED) - coord_x = coordinates_x[i].regamma_y_red; + coord_x = hw_coordinates_x[i].regamma_y_red; else if (channel == CHANNEL_NAME_GREEN) - coord_x = coordinates_x[i].regamma_y_green; + coord_x = hw_coordinates_x[i].regamma_y_green; else - coord_x = coordinates_x[i].regamma_y_blue; + coord_x = hw_coordinates_x[i].regamma_y_blue; if (!find_software_points( ramp, axis_x, coord_x, channel, @@ -1539,11 +1539,11 @@ static void build_evenly_distributed_points( } static inline void copy_rgb_regamma_to_coordinates_x( - struct hw_x_point *coordinates_x, + struct hw_x_point *hw_coordinates_x, uint32_t hw_points_num, const struct pwl_float_data_ex *rgb_ex) { - struct hw_x_point *coords = coordinates_x; + struct hw_x_point *coords = hw_coordinates_x; uint32_t i = 0; const struct pwl_float_data_ex *rgb_regamma = rgb_ex; @@ -1562,7 +1562,7 @@ static bool calculate_interpolated_hardware_curve( const struct dc_gamma *ramp, struct pixel_gamma_point *coeff128, struct pwl_float_data *rgb_user, - const struct hw_x_point *coordinates_x, + const struct hw_x_point *hw_coordinates_x, const struct gamma_pixel *axis_x, uint32_t number_of_points, struct dc_transfer_func_distributed_points *tf_pts) @@ -1575,7 +1575,7 @@ static bool calculate_interpolated_hardware_curve( for (i = 0; i < 3; i++) { if (!build_custom_gamma_mapping_coefficients_worker( - ramp, coeff128, coordinates_x, axis_x, i, + ramp, coeff128, hw_coordinates_x, axis_x, i, number_of_points)) return false; } @@ -1786,14 +1786,14 @@ bool mod_color_calculate_degamma_params(struct dc_color_caps *dc_caps, if (input_tf->tf == TRANSFER_FUNCTION_PQ) { /* just copy current rgb_regamma into tf_pts */ struct pwl_float_data_ex *curvePt = curve; - int i = 0; + int j = 0; - while (i <= MAX_HW_POINTS) { - tf_pts->red[i] = curvePt->r; - tf_pts->green[i] = curvePt->g; - tf_pts->blue[i] = curvePt->b; + while (j <= MAX_HW_POINTS) { + tf_pts->red[j] = curvePt->r; + tf_pts->green[j] = curvePt->g; + tf_pts->blue[j] = curvePt->b; ++curvePt; - ++i; + ++j; } } else { // clamps to 0-1 From c3fb1fb9e65fa6a108b4d19c61bdcb47fd4fe180 Mon Sep 17 00:00:00 2001 From: Clay King Date: Mon, 27 Apr 2026 14:51:35 -0400 Subject: [PATCH 38/71] drm/amd/display: Fix warnings [Why & How] Fix various warnings related to unsigned/signed mismatches - Consistently use the same signedness for a given value - Explcitly cast between types when needed Reviewed-by: Dillon Varone Signed-off-by: Clay King Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../display/dc/clk_mgr/dce100/dce_clk_mgr.c | 6 +- .../display/dc/clk_mgr/dce100/dce_clk_mgr.h | 2 +- .../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 8 +- .../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 4 +- .../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h | 2 +- .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +- .../dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 2 +- .../dc/clk_mgr/dcn401/dcn401_clk_mgr.h | 4 +- .../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c | 4 +- .../clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h | 2 +- .../display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +- .../drm/amd/display/dc/core/dc_link_exports.c | 2 +- .../gpu/drm/amd/display/dc/core/dc_resource.c | 18 +- .../drm/amd/display/dc/core/dc_vm_helper.c | 4 +- drivers/gpu/drm/amd/display/dc/dc.h | 68 +-- drivers/gpu/drm/amd/display/dc/dc_dsc.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_stream.h | 4 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +- .../amd/display/dc/dcn21/dcn21_link_encoder.c | 2 +- .../display/dc/dio/dcn10/dcn10_link_encoder.c | 2 +- .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 4 +- .../dc/dml/dcn21/display_mode_vba_21.c | 28 +- .../dc/dml/dcn30/display_mode_vba_30.c | 342 +++++++-------- .../dc/dml/dcn31/display_mode_vba_31.c | 408 +++++++++--------- .../dc/dml/dcn314/display_mode_vba_314.c | 400 ++++++++--------- .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 +- .../dc/dml/dcn32/display_mode_vba_util_32.c | 8 +- .../dc/dml/dcn32/display_mode_vba_util_32.h | 8 +- .../drm/amd/display/dc/dml/display_mode_vba.h | 12 +- .../amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c | 2 +- .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 2 +- .../amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c | 4 +- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 +- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 8 +- .../drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c | 8 +- .../amd/display/dc/dsc/dcn401/dcn401_dsc.c | 10 +- .../amd/display/dc/hubp/dcn401/dcn401_hubp.c | 4 +- .../amd/display/dc/hubp/dcn401/dcn401_hubp.h | 2 +- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 6 +- .../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 2 +- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 +- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 4 +- .../amd/display/dc/inc/hw/timing_generator.h | 8 +- .../gpu/drm/amd/display/dc/inc/link_service.h | 2 +- .../gpu/drm/amd/display/dc/inc/reg_helper.h | 72 ++-- .../drm/amd/display/dc/link/link_detection.c | 2 +- .../drm/amd/display/dc/link/link_detection.h | 2 +- .../link/protocols/link_edp_panel_control.c | 8 +- .../drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c | 2 +- .../drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c | 6 +- .../drm/amd/display/dc/opp/dcn20/dcn20_opp.c | 2 +- .../drm/amd/display/dc/opp/dcn20/dcn20_opp.h | 2 +- .../amd/display/dc/optc/dcn32/dcn32_optc.c | 2 +- .../gpu/drm/amd/display/include/fixed31_32.h | 6 +- .../drm/amd/display/modules/hdcp/hdcp_log.c | 2 +- 59 files changed, 769 insertions(+), 767 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index 6d41df52d7c9..808e24f0e88f 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -88,7 +88,7 @@ static const struct state_dependent_clocks dce80_max_clks_by_state[] = { /* ClocksStatePerformance */ { .display_clk_khz = 625000, .pixel_clk_khz = 400000 } }; -int dentist_get_divider_from_did(int did) +unsigned int dentist_get_divider_from_did(unsigned int did) { if (did < DENTIST_BASE_DID_1) did = DENTIST_BASE_DID_1; @@ -155,8 +155,8 @@ static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); - int dprefclk_wdivider; - int dprefclk_src_sel; + uint32_t dprefclk_wdivider; + uint32_t dprefclk_src_sel; int dp_ref_clk_khz; int target_div; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h index f6622f58f62e..9ea1b0a9923d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h @@ -54,6 +54,6 @@ int dce_set_clock( void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr); -int dentist_get_divider_from_did(int did); +unsigned int dentist_get_divider_from_did(unsigned int did); #endif /* _DCE_CLK_MGR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index c0abbdd2cf5c..cbd989b6a3df 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -430,8 +430,8 @@ void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base) struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); uint32_t dispclk_wdivider; uint32_t dppclk_wdivider; - int disp_divider; - int dpp_divider; + unsigned int disp_divider; + unsigned int dpp_divider; REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider); @@ -534,8 +534,8 @@ void dcn20_clk_mgr_construct( struct pp_smu_funcs *pp_smu, struct dccg *dccg) { - int dprefclk_did; - int target_div; + unsigned int dprefclk_did; + unsigned int target_div; uint32_t pll_req_reg; struct fixed31_32 pll_req; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c index 827bc2431d5d..e36233127b15 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c @@ -123,12 +123,12 @@ bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input) return false; } -bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version) +bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version) { smu_print("SMU Get SMU version\n"); if (dcn30_smu_send_msg_with_param(clk_mgr, - DALSMC_MSG_GetSmuVersion, 0, version)) { + DALSMC_MSG_GetSmuVersion, 0, (uint32_t *)version)) { smu_print("SMU version: %d\n", *version); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h index ca9f5296be94..67e93f9cac71 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h @@ -31,7 +31,7 @@ struct clk_mgr_internal; bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input); -bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version); +bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version); bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr); bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr); void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 478527a0bca2..90fdbf279868 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -475,7 +475,7 @@ static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); uint32_t dispclk_wdivider; - int disp_divider; + unsigned int disp_divider; REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); disp_divider = dentist_get_divider_from_did(dispclk_wdivider); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c index 6ad38cb28d23..5bf6f2d50705 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c @@ -1490,7 +1490,7 @@ static int dcn401_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); uint32_t dispclk_wdivider; - int disp_divider; + unsigned int disp_divider; REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); disp_divider = dentist_get_divider_from_did(dispclk_wdivider); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h index 97a1ce1e8a9e..370d2ddd6064 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h @@ -17,14 +17,14 @@ union dcn401_clk_mgr_block_sequence_params { uint32_t ppclk; uint16_t freq_mhz; /* outputs */ - uint32_t *response; + int *response; } update_hardmin_params; struct { /* inputs */ uint32_t ppclk; int freq_khz; /* outputs */ - uint32_t *response; + int *response; } update_hardmin_optimized_params; struct { /* inputs */ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c index 3a263840893e..82ccd9b407f4 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.c @@ -143,12 +143,12 @@ static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mg return false; } -bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version) +bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version) { smu_print("SMU Get SMU version\n"); if (dcn401_smu_send_msg_with_param(clk_mgr, - DALSMC_MSG_GetSmuVersion, 0, version)) { + DALSMC_MSG_GetSmuVersion, 0, (uint32_t *)version)) { smu_print("SMU version: %d\n", *version); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h index 4f5ac603e822..1addbed1cb99 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr_smu_msg.h @@ -10,7 +10,7 @@ struct clk_mgr_internal; -bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version); +bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, int *version); bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr); bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr); void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index 41729426d08c..245a217894a7 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -879,7 +879,7 @@ int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) (void)clk_mgr_base; struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); uint32_t dispclk_wdivider; - int disp_divider; + unsigned int disp_divider; REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); disp_divider = dentist_get_divider_from_did(dispclk_wdivider); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 4dc76935f8aa..4a601bf8c9d3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -7005,7 +7005,7 @@ bool dc_can_clear_cursor_limit(const struct dc *dc) return false; } -void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, +void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data) { struct timing_generator *tg = NULL; @@ -7023,7 +7023,7 @@ void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, dc->hwss.get_underflow_debug_data(dc, tg, out_data); } -void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, +void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data) { (void)primary_otg_inst; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c index f4e99ca7918f..5ac5ad86bd01 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c @@ -282,7 +282,7 @@ unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link) struct dc_sink *dc_link_add_remote_sink( struct dc_link *link, const uint8_t *edid, - int len, + unsigned int len, struct dc_sink_init_data *init_data) { return link->dc->link_srv->add_remote_sink(link, edid, len, init_data); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ad377a991451..f57e9d85563e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -982,7 +982,7 @@ static struct rect calculate_mpc_slice_in_timing_active( } static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx, - int *base_offset, int *dpp_offset) + unsigned int *base_offset, unsigned int *dpp_offset) { struct dc *dc = pipe_ctx->stream->ctx->dc; *base_offset = 0; @@ -1004,7 +1004,7 @@ static void calculate_adjust_recout_for_visual_confirm(struct pipe_ctx *pipe_ctx static void reverse_adjust_recout_for_visual_confirm(struct rect *recout, struct pipe_ctx *pipe_ctx) { - int dpp_offset, base_offset; + unsigned int dpp_offset, base_offset; calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset, &dpp_offset); @@ -1015,7 +1015,7 @@ static void reverse_adjust_recout_for_visual_confirm(struct rect *recout, static void adjust_recout_for_visual_confirm(struct rect *recout, struct pipe_ctx *pipe_ctx) { - int dpp_offset, base_offset; + unsigned int dpp_offset, base_offset; calculate_adjust_recout_for_visual_confirm(pipe_ctx, &base_offset, &dpp_offset); @@ -1692,7 +1692,7 @@ bool resource_can_pipe_disable_cursor(struct pipe_ctx *pipe_ctx) struct pipe_ctx *test_pipe, *split_pipe; struct rect r1 = pipe_ctx->plane_res.scl_data.recout; int r1_right, r1_bottom; - int cur_layer = pipe_ctx->plane_state->layer_index; + unsigned int cur_layer = pipe_ctx->plane_state->layer_index; reverse_adjust_recout_for_visual_confirm(&r1, pipe_ctx); r1_right = r1.x + r1.width; @@ -4103,9 +4103,9 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) static bool planes_changed_for_existing_stream(struct dc_state *context, struct dc_stream_state *stream, const struct dc_validation_set set[], - int set_count) + unsigned int set_count) { - int i, j; + unsigned int i, j; struct dc_stream_status *stream_status = NULL; for (i = 0; i < context->stream_count; i++) { @@ -4141,10 +4141,10 @@ static bool add_all_planes_for_stream( const struct dc *dc, struct dc_stream_state *stream, const struct dc_validation_set set[], - int set_count, + unsigned int set_count, struct dc_state *state) { - int i, j; + unsigned int i, j; for (i = 0; i < set_count; i++) if (set[i].stream == stream) @@ -4182,7 +4182,7 @@ static bool add_all_planes_for_stream( */ enum dc_status dc_validate_with_context(struct dc *dc, const struct dc_validation_set set[], - int set_count, + unsigned int set_count, struct dc_state *context, enum dc_validate_mode validate_mode) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c index d1e68dc57a2a..3743555133f6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c @@ -34,9 +34,9 @@ void vm_helper_mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos, uin vmids.vmid_usage[1] = 1 << pos; } -int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config) +unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config) { - int num_vmids = 0; + unsigned int num_vmids = 0; /* Call HWSS to setup HUBBUB for address config */ if (dc->hwss.init_sys_ctx) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9bd4b0bb47df..e5933e3a8206 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -540,7 +540,7 @@ struct dc_config { bool use_default_clock_table; bool force_bios_enable_lttpr; uint8_t force_bios_fixed_vs; - int sdpif_request_limit_words_per_umc; + unsigned int sdpif_request_limit_words_per_umc; bool dc_mode_clk_limit_support; bool EnableMinDispClkODM; bool enable_auto_dpm_test_logs; @@ -944,20 +944,20 @@ struct dc_virtual_addr_space_config { }; struct dc_bounding_box_overrides { - int sr_exit_time_ns; - int sr_enter_plus_exit_time_ns; - int sr_exit_z8_time_ns; - int sr_enter_plus_exit_z8_time_ns; - int urgent_latency_ns; - int percent_of_ideal_drambw; - int dram_clock_change_latency_ns; - int dummy_clock_change_latency_ns; - int fclk_clock_change_latency_ns; + unsigned int sr_exit_time_ns; + unsigned int sr_enter_plus_exit_time_ns; + unsigned int sr_exit_z8_time_ns; + unsigned int sr_enter_plus_exit_z8_time_ns; + unsigned int urgent_latency_ns; + unsigned int percent_of_ideal_drambw; + unsigned int dram_clock_change_latency_ns; + unsigned int dummy_clock_change_latency_ns; + unsigned int fclk_clock_change_latency_ns; /* This forces a hard min on the DCFCLK we use * for DML. Unlike the debug option for forcing * DCFCLK, this override affects watermark calculations */ - int min_dcfclk_mhz; + unsigned int min_dcfclk_mhz; }; struct dc_qos_info { @@ -990,7 +990,7 @@ struct link_service; struct dc_debug_options { bool disable_dsc; enum visual_confirm visual_confirm; - int visual_confirm_rect_height; + unsigned int visual_confirm_rect_height; bool sanity_checks; bool max_disp_clk; @@ -1026,23 +1026,23 @@ struct dc_debug_options { bool disable_io_clk_power_gate; bool disable_mem_power_gate; bool disable_dio_power_gate; - int dsc_min_slice_height_override; - int dsc_bpp_increment_div; + unsigned int dsc_min_slice_height_override; + unsigned int dsc_bpp_increment_div; bool disable_pplib_wm_range; enum wm_report_mode pplib_wm_report_mode; unsigned int min_disp_clk_khz; unsigned int min_dpp_clk_khz; unsigned int min_dram_clk_khz; - int sr_exit_time_dpm0_ns; - int sr_enter_plus_exit_time_dpm0_ns; - int sr_exit_time_ns; - int sr_enter_plus_exit_time_ns; - int sr_exit_z8_time_ns; - int sr_enter_plus_exit_z8_time_ns; - int urgent_latency_ns; + unsigned int sr_exit_time_dpm0_ns; + unsigned int sr_enter_plus_exit_time_dpm0_ns; + unsigned int sr_exit_time_ns; + unsigned int sr_enter_plus_exit_time_ns; + unsigned int sr_exit_z8_time_ns; + unsigned int sr_enter_plus_exit_z8_time_ns; + unsigned int urgent_latency_ns; uint32_t underflow_assert_delay_us; - int percent_of_ideal_drambw; - int dram_clock_change_latency_ns; + unsigned int percent_of_ideal_drambw; + unsigned int dram_clock_change_latency_ns; bool optimized_watermark; int always_scale; bool disable_pplib_clock_request; @@ -1067,8 +1067,8 @@ struct dc_debug_options { uint8_t seamless_boot_odm_combine; uint8_t force_odm_combine_4to1; //bit vector based on otg inst - int minimum_z8_residency_time; - int minimum_z10_residency_time; + unsigned int minimum_z8_residency_time; + unsigned int minimum_z10_residency_time; bool disable_z9_mpc; unsigned int force_fclk_khz; bool enable_tri_buf; @@ -1117,7 +1117,7 @@ struct dc_debug_options { uint8_t fec_enable_delay_in100us; bool enable_driver_sequence_debug; enum det_size crb_alloc_policy; - int crb_alloc_policy_min_disp_count; + unsigned int crb_alloc_policy_min_disp_count; bool disable_z10; bool enable_z9_disable_interface; bool psr_skip_crtc_disable; @@ -1291,7 +1291,7 @@ void dc_hardware_init(struct dc *dc); int dc_get_vmid_use_vector(struct dc *dc); void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); /* Returns the number of vmids supported */ -int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); +unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); void dc_init_callbacks(struct dc *dc, const struct dc_callback_init *init_params); void dc_deinit_callbacks(struct dc *dc); @@ -1520,7 +1520,7 @@ struct dc_plane_state { bool visible; bool flip_immediate; bool horizontal_mirror; - int layer_index; + unsigned int layer_index; union surface_update_flags update_flags; bool flip_int_enabled; @@ -1550,7 +1550,7 @@ struct dc_plane_state { struct dc_csc_transform cursor_csc_color_matrix; bool adaptive_sharpness_en; int adaptive_sharpness_policy; - int sharpness_level; + unsigned int sharpness_level; enum linear_light_scaling linear_light_scaling; unsigned int sdr_white_level_nits; struct cm_hist_control cm_hist_control; @@ -1573,7 +1573,7 @@ struct dc_plane_info { bool global_alpha; int global_alpha_value; bool input_csc_enabled; - int layer_index; + unsigned int layer_index; enum chroma_cositing cositing; }; @@ -1965,7 +1965,7 @@ enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *pla enum dc_status dc_validate_with_context(struct dc *dc, const struct dc_validation_set set[], - int set_count, + unsigned int set_count, struct dc_state *context, enum dc_validate_mode validate_mode); @@ -2072,7 +2072,7 @@ struct dc_sink_init_data; struct dc_sink *dc_link_add_remote_sink( struct dc_link *dc_link, const uint8_t *edid, - int len, + unsigned int len, struct dc_sink_init_data *init_data); /* Remove remote sink from a link with dc_connection_mst_branch connection type. @@ -2869,9 +2869,9 @@ bool dc_can_clear_cursor_limit(const struct dc *dc); * including OTG underflow status, current read positions, frame count, and per-HUBP debug data. * The results are stored in the provided out_data structure for further analysis or logging. */ -void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, struct dc_underflow_debug_data *out_data); +void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data); -void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, struct power_features *out_data); +void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data); /* * Software state variables used to program register fields across the display pipeline diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h index 101bce6b8de6..7cb34e2b44a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -92,7 +92,7 @@ uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing, uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps( const struct dc_crtc_timing *timing, - const int num_slices_h, + const uint32_t num_slices_h, const bool is_dp); void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc, diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 32f7c7c076c8..1649fbab08aa 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -159,8 +159,8 @@ struct luminance_data { int luminance_millinits[LUMINANCE_DATA_TABLE_SIZE]; int flicker_criteria_milli_nits_GAMING; int flicker_criteria_milli_nits_STATIC; - int nominal_refresh_rate; - int dm_max_decrease_from_nominal; + unsigned int nominal_refresh_rate; + unsigned int dm_max_decrease_from_nominal; }; enum dc_drr_trigger_mode { diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 12ce4a059231..3ec49f4e277f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -917,7 +917,7 @@ struct dsc_dec_dpcd_caps { union dsc_slice_caps2 slice_caps2; int32_t lb_bit_depth; bool is_block_pred_supported; - int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ + uint32_t edp_max_bits_per_pixel; /* Valid only in eDP */ union dsc_color_formats color_formats; union dsc_color_depth color_depth; int32_t throughput_mode_0_mps; /* In MPs */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c index 36456c9971c8..fcaa3884d705 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c @@ -205,7 +205,7 @@ static bool update_cfg_data( static bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc) { struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - int value; + uint32_t value; if (enc->features.flags.bits.DP_IS_USB_C) { REG_GET(RDPCSTX_PHY_CNTL6, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c index 872ea3646023..59b68422334d 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c @@ -450,7 +450,7 @@ static uint8_t get_frontend_source( unsigned int dcn10_get_dig_frontend(struct link_encoder *enc) { struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); - int32_t value; + uint32_t value; enum engine_id result; REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index 71710d96ffe3..ed7c989a5b13 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -1105,7 +1105,7 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc } static void dcn20_adjust_freesync_v_startup( - const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start) + const struct dc_crtc_timing *dc_crtc_timing, unsigned int *vstartup_start) { struct dc_crtc_timing patched_crtc_timing; uint32_t asic_blank_end = 0; @@ -1253,7 +1253,7 @@ void dcn20_calculate_dlg_params(struct dc *dc, static void swizzle_to_dml_params( enum swizzle_mode_values swizzle, - unsigned int *sw_mode) + int *sw_mode) { switch (swizzle) { case DC_SW_LINEAR: diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index 3ff71751db1e..961b705acfa9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -296,7 +296,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double UrgentOutOfOrderReturn, double ReturnBW, bool GPUVMEnable, - int dpte_group_bytes[], + unsigned int dpte_group_bytes[], unsigned int MetaChunkSize, double UrgentLatency, double ExtraLatency, @@ -307,7 +307,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double SRExitTime, double SREnterPlusExitTime, double DCFCLKDeepSleep, - int DPPPerPlane[], + unsigned int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], double SwathWidthSingleDPPY[], @@ -346,7 +346,7 @@ static void CalculateDCFCLKDeepSleep( double BytePerPixelDETC[], double VRatio[], double SwathWidthY[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double HRatio[], double PixelClock[], double PSCL_THROUGHPUT[], @@ -390,7 +390,7 @@ static void CalculatePixelDeliveryTimes( double VRatioPrefetchC[], unsigned int swath_width_luma_ub[], unsigned int swath_width_chroma_ub[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double HRatio[], double PixelClock[], double PSCL_THROUGHPUT[], @@ -436,7 +436,7 @@ static void CalculateMetaAndPTETimes( unsigned int meta_row_height[], unsigned int meta_req_width[], unsigned int meta_req_height[], - int dpte_group_bytes[], + unsigned int dpte_group_bytes[], unsigned int PTERequestSizeY[], unsigned int PTERequestSizeC[], unsigned int PixelPTEReqWidthY[], @@ -477,8 +477,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, int HostVMMaxPageTableLevels, @@ -5257,7 +5257,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double UrgentOutOfOrderReturn, double ReturnBW, bool GPUVMEnable, - int dpte_group_bytes[], + unsigned int dpte_group_bytes[], unsigned int MetaChunkSize, double UrgentLatency, double ExtraLatency, @@ -5268,7 +5268,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double SRExitTime, double SREnterPlusExitTime, double DCFCLKDeepSleep, - int DPPPerPlane[], + unsigned int DPPPerPlane[], bool DCCEnable[], double DPPCLK[], double SwathWidthSingleDPPY[], @@ -5543,7 +5543,7 @@ static void CalculateDCFCLKDeepSleep( double BytePerPixelDETC[], double VRatio[], double SwathWidthY[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double HRatio[], double PixelClock[], double PSCL_THROUGHPUT[], @@ -5749,7 +5749,7 @@ static void CalculatePixelDeliveryTimes( double VRatioPrefetchC[], unsigned int swath_width_luma_ub[], unsigned int swath_width_chroma_ub[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double HRatio[], double PixelClock[], double PSCL_THROUGHPUT[], @@ -5870,7 +5870,7 @@ static void CalculateMetaAndPTETimes( unsigned int meta_row_height[], unsigned int meta_req_width[], unsigned int meta_req_height[], - int dpte_group_bytes[], + unsigned int dpte_group_bytes[], unsigned int PTERequestSizeY[], unsigned int PTERequestSizeC[], unsigned int PixelPTEReqWidthY[], @@ -6126,8 +6126,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, int HostVMMaxPageTableLevels, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index 3c9040117cc4..f0b1bfb408f6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -285,8 +285,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], @@ -327,7 +327,7 @@ static void CalculateUrgentBurstFactor( static void UseMinimumDCFCLK( struct display_mode_lib *mode_lib, struct vba_vars_st *v, - int MaxPrefetchMode, + unsigned int MaxPrefetchMode, int ReorderingBytes); static void CalculatePixelDeliveryTimes( @@ -345,7 +345,7 @@ static void CalculatePixelDeliveryTimes( double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][2], @@ -370,35 +370,35 @@ static void CalculateMetaAndPTETimes( bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, - int HTotal[], + unsigned int HTotal[], double VRatio[], double VRatioChroma[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], - int dpte_row_height[], - int dpte_row_height_chroma[], - int meta_row_width[], - int meta_row_width_chroma[], - int meta_row_height[], - int meta_row_height_chroma[], - int meta_req_width[], - int meta_req_width_chroma[], - int meta_req_height[], - int meta_req_height_chroma[], - int dpte_group_bytes[], - int PTERequestSizeY[], - int PTERequestSizeC[], - int PixelPTEReqWidthY[], - int PixelPTEReqHeightY[], - int PixelPTEReqWidthC[], - int PixelPTEReqHeightC[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], @@ -421,18 +421,18 @@ static void CalculateVMGroupAndRequestTimes( bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], - int vm_group_bytes[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], - int meta_pte_bytes_per_frame_ub_l[], - int meta_pte_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], @@ -446,27 +446,27 @@ static void CalculateStutterEfficiency( double ReturnBW, double SRExitTime, bool SynchronizedVBlank, - int DPPPerPlane[], + unsigned int DPPPerPlane[], unsigned int DETBufferSizeY[], - int BytePerPixelY[], + unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], double DCCRateLuma[], double DCCRateChroma[], - int HTotal[], - int VTotal[], + unsigned int HTotal[], + unsigned int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], - int BlockHeight256BytesY[], - int BlockWidth256BytesY[], - int BlockHeight256BytesC[], - int BlockWidth256BytesC[], - int DCCYMaxUncompressedBlock[], - int DCCCMaxUncompressedBlock[], - int VActive[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], @@ -486,32 +486,32 @@ static void CalculateSwathAndDETConfiguration( enum scan_direction_class SourceScan[], enum source_format_class SourcePixelFormat[], enum dm_swizzle_mode SurfaceTiling[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], enum odm_combine_mode ODMCombineEnabled[], - int BlendingAndTiming[], - int BytePerPixY[], - int BytePerPixC[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], double BytePerPixDETY[], double BytePerPixDETC[], - int HActive[], + unsigned int HActive[], double HRatio[], double HRatioChroma[], - int DPPPerPlane[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], double SwathWidth[], double SwathWidthChroma[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], @@ -528,22 +528,22 @@ static void CalculateSwathWidth( unsigned int SurfaceHeightY[], unsigned int SurfaceHeightC[], enum odm_combine_mode ODMCombineEnabled[], - int BytePerPixY[], - int BytePerPixC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], - int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], unsigned int HActive[], double HRatio[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double SwathWidthSingleDPPY[], double SwathWidthSingleDPPC[], double SwathWidthY[], double SwathWidthC[], - int MaximumSwathHeightY[], - int MaximumSwathHeightC[], + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], unsigned int swath_width_luma_ub[], unsigned int swath_width_chroma_ub[]); static double CalculateExtraLatency( @@ -558,8 +558,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, double HostVMMinPageSize, @@ -573,8 +573,8 @@ static double CalculateExtraLatencyBytes( bool GPUVMEnable, bool HostVMEnable, unsigned int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, double HostVMMinPageSize, @@ -2888,18 +2888,18 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) // Display Pipe Configuration double BytePerPixDETY[DC__NUM_DPP__MAX] = { 0 }; double BytePerPixDETC[DC__NUM_DPP__MAX] = { 0 }; - int BytePerPixY[DC__NUM_DPP__MAX] = { 0 }; - int BytePerPixC[DC__NUM_DPP__MAX] = { 0 }; - int Read256BytesBlockHeightY[DC__NUM_DPP__MAX] = { 0 }; - int Read256BytesBlockHeightC[DC__NUM_DPP__MAX] = { 0 }; - int Read256BytesBlockWidthY[DC__NUM_DPP__MAX] = { 0 }; - int Read256BytesBlockWidthC[DC__NUM_DPP__MAX] = { 0 }; + unsigned int BytePerPixY[DC__NUM_DPP__MAX] = { 0 }; + unsigned int BytePerPixC[DC__NUM_DPP__MAX] = { 0 }; + unsigned int Read256BytesBlockHeightY[DC__NUM_DPP__MAX] = { 0 }; + unsigned int Read256BytesBlockHeightC[DC__NUM_DPP__MAX] = { 0 }; + unsigned int Read256BytesBlockWidthY[DC__NUM_DPP__MAX] = { 0 }; + unsigned int Read256BytesBlockWidthC[DC__NUM_DPP__MAX] = { 0 }; double dummy1[DC__NUM_DPP__MAX] = { 0 }; double dummy2[DC__NUM_DPP__MAX] = { 0 }; double dummy3[DC__NUM_DPP__MAX] = { 0 }; double dummy4[DC__NUM_DPP__MAX] = { 0 }; - int dummy5[DC__NUM_DPP__MAX] = { 0 }; - int dummy6[DC__NUM_DPP__MAX] = { 0 }; + unsigned int dummy5[DC__NUM_DPP__MAX] = { 0 }; + unsigned int dummy6[DC__NUM_DPP__MAX] = { 0 }; bool dummy7[DC__NUM_DPP__MAX] = { 0 }; bool dummysinglestring = 0; unsigned int k; @@ -3381,7 +3381,7 @@ static double TruncToValidBPP( void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) { struct vba_vars_st *v = &mode_lib->vba; - int MinPrefetchMode, MaxPrefetchMode; + unsigned int MinPrefetchMode, MaxPrefetchMode; int idx, start_state; unsigned int i, j, k, m; bool EnoughWritebackUnits = true; @@ -4550,7 +4550,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l for (i = start_state; i < mode_lib->soc.num_states; ++i) { for (j = 0; j <= 1; ++j) { - int NextPrefetchModeState = MinPrefetchMode; + unsigned int NextPrefetchModeState = MinPrefetchMode; v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j]; @@ -5153,8 +5153,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], @@ -5306,7 +5306,7 @@ static void CalculatePixelDeliveryTimes( double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][2], @@ -5411,35 +5411,35 @@ static void CalculateMetaAndPTETimes( bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, - int HTotal[], + unsigned int HTotal[], double VRatio[], double VRatioChroma[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], - int dpte_row_height[], - int dpte_row_height_chroma[], - int meta_row_width[], - int meta_row_width_chroma[], - int meta_row_height[], - int meta_row_height_chroma[], - int meta_req_width[], - int meta_req_width_chroma[], - int meta_req_height[], - int meta_req_height_chroma[], - int dpte_group_bytes[], - int PTERequestSizeY[], - int PTERequestSizeC[], - int PixelPTEReqWidthY[], - int PixelPTEReqHeightY[], - int PixelPTEReqWidthC[], - int PixelPTEReqHeightC[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], @@ -5584,18 +5584,18 @@ static void CalculateVMGroupAndRequestTimes( bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], - int vm_group_bytes[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], - int meta_pte_bytes_per_frame_ub_l[], - int meta_pte_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], @@ -5700,27 +5700,27 @@ static void CalculateStutterEfficiency( double ReturnBW, double SRExitTime, bool SynchronizedVBlank, - int DPPPerPlane[], + unsigned int DPPPerPlane[], unsigned int DETBufferSizeY[], - int BytePerPixelY[], + unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], double DCCRateLuma[], double DCCRateChroma[], - int HTotal[], - int VTotal[], + unsigned int HTotal[], + unsigned int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], - int BlockHeight256BytesY[], - int BlockWidth256BytesY[], - int BlockHeight256BytesC[], - int BlockWidth256BytesC[], - int DCCYMaxUncompressedBlock[], - int DCCCMaxUncompressedBlock[], - int VActive[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], @@ -5854,42 +5854,42 @@ static void CalculateSwathAndDETConfiguration( enum scan_direction_class SourceScan[], enum source_format_class SourcePixelFormat[], enum dm_swizzle_mode SurfaceTiling[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], enum odm_combine_mode ODMCombineEnabled[], - int BlendingAndTiming[], - int BytePerPixY[], - int BytePerPixC[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], double BytePerPixDETY[], double BytePerPixDETC[], - int HActive[], + unsigned int HActive[], double HRatio[], double HRatioChroma[], - int DPPPerPlane[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], double SwathWidth[], double SwathWidthChroma[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], bool *ViewportSizeSupport) { (void)HRatioChroma; - int MaximumSwathHeightY[DC__NUM_DPP__MAX] = { 0 }; - int MaximumSwathHeightC[DC__NUM_DPP__MAX] = { 0 }; - int MinimumSwathHeightY = 0; - int MinimumSwathHeightC = 0; + unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX] = { 0 }; + unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX] = { 0 }; + unsigned int MinimumSwathHeightY = 0; + unsigned int MinimumSwathHeightC = 0; long RoundedUpMaxSwathSizeBytesY = 0; long RoundedUpMaxSwathSizeBytesC = 0; long RoundedUpMinSwathSizeBytesY = 0; @@ -6049,22 +6049,22 @@ static void CalculateSwathWidth( unsigned int SurfaceHeightY[], unsigned int SurfaceHeightC[], enum odm_combine_mode ODMCombineEnabled[], - int BytePerPixY[], - int BytePerPixC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], - int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], unsigned int HActive[], double HRatio[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double SwathWidthSingleDPPY[], double SwathWidthSingleDPPC[], double SwathWidthY[], double SwathWidthC[], - int MaximumSwathHeightY[], - int MaximumSwathHeightC[], + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], unsigned int swath_width_luma_ub[], unsigned int swath_width_chroma_ub[]) { @@ -6157,8 +6157,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, double HostVMMinPageSize, @@ -6193,8 +6193,8 @@ static double CalculateExtraLatencyBytes( bool GPUVMEnable, bool HostVMEnable, unsigned int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly, double HostVMMinPageSize, @@ -6251,7 +6251,7 @@ static double CalculateUrgentLatency( static noinline_for_stack void UseMinimumDCFCLK( struct display_mode_lib *mode_lib, struct vba_vars_st *v, - int MaxPrefetchMode, + unsigned int MaxPrefetchMode, int ReorderingBytes) { double NormalEfficiency = 0; @@ -6276,7 +6276,7 @@ static noinline_for_stack void UseMinimumDCFCLK( double ExtraLatencyBytes = 0; double ExtraLatencyCycles = 0; double DCFCLKRequiredForPeakBandwidth = 0; - int NoOfDPPState[DC__NUM_DPP__MAX] = { 0 }; + unsigned int NoOfDPPState[DC__NUM_DPP__MAX] = { 0 }; double MinimumTvmPlus2Tr0 = 0; TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index 173251d738f2..f9224a433220 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -157,7 +157,7 @@ static bool CalculatePrefetchSchedule( double *Tdmdl_vm, double *Tdmdl, double *TSetup, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix); static double RoundToDFSGranularityUp(double Clock, double VCOSpeed); @@ -218,19 +218,19 @@ static unsigned int CalculateVMAndRowBytes( unsigned int *MetaRowByte, unsigned int *PixelPTEBytesPerRow, bool *PTEBufferSizeNotExceeded, - int *dpte_row_width_ub, + unsigned int *dpte_row_width_ub, unsigned int *dpte_row_height, unsigned int *MetaRequestWidth, unsigned int *MetaRequestHeight, unsigned int *meta_row_width, unsigned int *meta_row_height, - int *vm_group_bytes, + unsigned int *vm_group_bytes, unsigned int *dpte_group_bytes, unsigned int *PixelPTEReqWidth, unsigned int *PixelPTEReqHeight, unsigned int *PTERequestSize, - int *DPDE0BytesFrame, - int *MetaPTEBytesFrame); + unsigned int *DPDE0BytesFrame, + unsigned int *MetaPTEBytesFrame); static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime); static void CalculateRowBandwidth( bool GPUVMEnable, @@ -285,7 +285,7 @@ static void CalculateVupdateAndDynamicMetadataParameters( double *Tdmbf, double *Tdmec, double *Tdmsks, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix); @@ -318,8 +318,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], @@ -377,7 +377,7 @@ static void CalculatePixelDeliveryTimes( double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], @@ -402,35 +402,35 @@ static void CalculateMetaAndPTETimes( bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, - int HTotal[], + unsigned int HTotal[], double VRatio[], double VRatioChroma[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], - int dpte_row_height[], - int dpte_row_height_chroma[], - int meta_row_width[], - int meta_row_width_chroma[], - int meta_row_height[], - int meta_row_height_chroma[], - int meta_req_width[], - int meta_req_width_chroma[], - int meta_req_height[], - int meta_req_height_chroma[], - int dpte_group_bytes[], - int PTERequestSizeY[], - int PTERequestSizeC[], - int PixelPTEReqWidthY[], - int PixelPTEReqHeightY[], - int PixelPTEReqWidthC[], - int PixelPTEReqHeightC[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], @@ -453,18 +453,18 @@ static void CalculateVMGroupAndRequestTimes( bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], - int vm_group_bytes[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], - int meta_pte_bytes_per_frame_ub_l[], - int meta_pte_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], @@ -492,29 +492,29 @@ static void CalculateStutterEfficiency( bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], unsigned int DETBufferSizeY[], - int BytePerPixelY[], + unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], double NetDCCRateLuma[], double NetDCCRateChroma[], double DCCFractionOfZeroSizeRequestsLuma[], double DCCFractionOfZeroSizeRequestsChroma[], - int HTotal[], - int VTotal[], + unsigned int HTotal[], + unsigned int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], - int BlockHeight256BytesY[], - int BlockWidth256BytesY[], - int BlockHeight256BytesC[], - int BlockWidth256BytesC[], - int DCCYMaxUncompressedBlock[], - int DCCCMaxUncompressedBlock[], - int VActive[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], @@ -539,32 +539,32 @@ static void CalculateSwathAndDETConfiguration( enum scan_direction_class SourceScan[], enum source_format_class SourcePixelFormat[], enum dm_swizzle_mode SurfaceTiling[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], enum odm_combine_mode ODMCombineEnabled[], - int BlendingAndTiming[], - int BytePerPixY[], - int BytePerPixC[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], double BytePerPixDETY[], double BytePerPixDETC[], - int HActive[], + unsigned int HActive[], double HRatio[], double HRatioChroma[], - int DPPPerPlane[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], double SwathWidth[], double SwathWidthChroma[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], @@ -574,31 +574,31 @@ static void CalculateSwathWidth( int NumberOfActivePlanes, enum source_format_class SourcePixelFormat[], enum scan_direction_class SourceScan[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], enum odm_combine_mode ODMCombineEnabled[], - int BytePerPixY[], - int BytePerPixC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], - int BlendingAndTiming[], - int HActive[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], + unsigned int HActive[], double HRatio[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double SwathWidthSingleDPPY[], double SwathWidthSingleDPPC[], double SwathWidthY[], double SwathWidthC[], - int MaximumSwathHeightY[], - int MaximumSwathHeightC[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[]); + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[]); static double CalculateExtraLatency( int RoundTripPingLatencyCycles, @@ -612,8 +612,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels); @@ -627,8 +627,8 @@ static double CalculateExtraLatencyBytes( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels); @@ -652,7 +652,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize( int CompressedBufferSegmentSizeInkByteFinal, enum output_encoder_class *Output, bool *UnboundedRequestEnabled, - int *CompressedBufferSizeInkByte); + unsigned int *CompressedBufferSizeInkByte); static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output); @@ -869,7 +869,7 @@ static bool CalculatePrefetchSchedule( double *Tdmdl_vm, double *Tdmdl, double *TSetup, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix) { @@ -1818,19 +1818,19 @@ static unsigned int CalculateVMAndRowBytes( unsigned int *MetaRowByte, unsigned int *PixelPTEBytesPerRow, bool *PTEBufferSizeNotExceeded, - int *dpte_row_width_ub, + unsigned int *dpte_row_width_ub, unsigned int *dpte_row_height, unsigned int *MetaRequestWidth, unsigned int *MetaRequestHeight, unsigned int *meta_row_width, unsigned int *meta_row_height, - int *vm_group_bytes, + unsigned int *vm_group_bytes, unsigned int *dpte_group_bytes, unsigned int *PixelPTEReqWidth, unsigned int *PixelPTEReqHeight, unsigned int *PTERequestSize, - int *DPDE0BytesFrame, - int *MetaPTEBytesFrame) + unsigned int *DPDE0BytesFrame, + unsigned int *MetaPTEBytesFrame) { (void)SourcePixelFormat; struct vba_vars_st *v = &mode_lib->vba; @@ -3278,18 +3278,18 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) // Display Pipe Configuration double BytePerPixDETY[DC__NUM_DPP__MAX]; double BytePerPixDETC[DC__NUM_DPP__MAX]; - int BytePerPixY[DC__NUM_DPP__MAX]; - int BytePerPixC[DC__NUM_DPP__MAX]; - int Read256BytesBlockHeightY[DC__NUM_DPP__MAX]; - int Read256BytesBlockHeightC[DC__NUM_DPP__MAX]; - int Read256BytesBlockWidthY[DC__NUM_DPP__MAX]; - int Read256BytesBlockWidthC[DC__NUM_DPP__MAX]; + unsigned int BytePerPixY[DC__NUM_DPP__MAX]; + unsigned int BytePerPixC[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockHeightY[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockHeightC[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockWidthY[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockWidthC[DC__NUM_DPP__MAX]; double dummy1[DC__NUM_DPP__MAX]; double dummy2[DC__NUM_DPP__MAX]; double dummy3[DC__NUM_DPP__MAX]; double dummy4[DC__NUM_DPP__MAX]; - int dummy5[DC__NUM_DPP__MAX]; - int dummy6[DC__NUM_DPP__MAX]; + unsigned int dummy5[DC__NUM_DPP__MAX]; + unsigned int dummy6[DC__NUM_DPP__MAX]; bool dummy7[DC__NUM_DPP__MAX]; bool dummysinglestring; @@ -3429,7 +3429,7 @@ static void CalculateVupdateAndDynamicMetadataParameters( double *Tdmbf, double *Tdmec, double *Tdmsks, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix) { @@ -3783,7 +3783,7 @@ static noinline void CalculatePrefetchSchedulePerPlane( &v->VReadyOffsetPix[k]); } -static void PatchDETBufferSizeInKByte(unsigned int NumberOfActivePlanes, int NoOfDPPThisState[], unsigned int config_return_buffer_size_in_kbytes, unsigned int DETBufferSizeInKByte[]) +static void PatchDETBufferSizeInKByte(unsigned int NumberOfActivePlanes, unsigned int NoOfDPPThisState[], unsigned int config_return_buffer_size_in_kbytes, unsigned int DETBufferSizeInKByte[]) { int total_pipes = 0; unsigned int i; @@ -3804,7 +3804,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l int idx; unsigned int i, j, k, m; int ReorderingBytes; - int MinPrefetchMode = 0, MaxPrefetchMode = 2; + unsigned int MinPrefetchMode = 0, MaxPrefetchMode = 2; bool NoChroma = true; bool EnoughWritebackUnits = true; bool P2IWith420 = false; @@ -5119,7 +5119,7 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l double HostVMInefficiencyFactor = 1; int NextPrefetchModeState = MinPrefetchMode; bool UnboundedRequestEnabledThisState = false; - int CompressedBufferSizeInkByteThisState = 0; + unsigned int CompressedBufferSizeInkByteThisState = 0; double dummy; v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j]; @@ -5774,8 +5774,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], @@ -5926,7 +5926,7 @@ static void CalculatePixelDeliveryTimes( double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], @@ -6050,35 +6050,35 @@ static void CalculateMetaAndPTETimes( bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, - int HTotal[], + unsigned int HTotal[], double VRatio[], double VRatioChroma[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], - int dpte_row_height[], - int dpte_row_height_chroma[], - int meta_row_width[], - int meta_row_width_chroma[], - int meta_row_height[], - int meta_row_height_chroma[], - int meta_req_width[], - int meta_req_width_chroma[], - int meta_req_height[], - int meta_req_height_chroma[], - int dpte_group_bytes[], - int PTERequestSizeY[], - int PTERequestSizeC[], - int PixelPTEReqWidthY[], - int PixelPTEReqHeightY[], - int PixelPTEReqWidthC[], - int PixelPTEReqHeightC[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], @@ -6223,18 +6223,18 @@ static void CalculateVMGroupAndRequestTimes( bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], - int vm_group_bytes[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], - int meta_pte_bytes_per_frame_ub_l[], - int meta_pte_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], @@ -6342,29 +6342,29 @@ static void CalculateStutterEfficiency( bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], unsigned int DETBufferSizeY[], - int BytePerPixelY[], + unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], double NetDCCRateLuma[], double NetDCCRateChroma[], double DCCFractionOfZeroSizeRequestsLuma[], double DCCFractionOfZeroSizeRequestsChroma[], - int HTotal[], - int VTotal[], + unsigned int HTotal[], + unsigned int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], - int BlockHeight256BytesY[], - int BlockWidth256BytesY[], - int BlockHeight256BytesC[], - int BlockWidth256BytesC[], - int DCCYMaxUncompressedBlock[], - int DCCCMaxUncompressedBlock[], - int VActive[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], @@ -6649,42 +6649,42 @@ static void CalculateSwathAndDETConfiguration( enum scan_direction_class SourceScan[], enum source_format_class SourcePixelFormat[], enum dm_swizzle_mode SurfaceTiling[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], enum odm_combine_mode ODMCombineEnabled[], - int BlendingAndTiming[], - int BytePerPixY[], - int BytePerPixC[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], double BytePerPixDETY[], double BytePerPixDETC[], - int HActive[], + unsigned int HActive[], double HRatio[], double HRatioChroma[], - int DPPPerPlane[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], double SwathWidth[], double SwathWidthChroma[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], bool *ViewportSizeSupport) { (void)HRatioChroma; - int MaximumSwathHeightY[DC__NUM_DPP__MAX]; - int MaximumSwathHeightC[DC__NUM_DPP__MAX]; - int MinimumSwathHeightY; - int MinimumSwathHeightC; + unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX]; + unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX]; + unsigned int MinimumSwathHeightY; + unsigned int MinimumSwathHeightC; unsigned int RoundedUpMaxSwathSizeBytesY; unsigned int RoundedUpMaxSwathSizeBytesC; unsigned int RoundedUpMinSwathSizeBytesY; @@ -6829,31 +6829,31 @@ static void CalculateSwathWidth( int NumberOfActivePlanes, enum source_format_class SourcePixelFormat[], enum scan_direction_class SourceScan[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], enum odm_combine_mode ODMCombineEnabled[], - int BytePerPixY[], - int BytePerPixC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], - int BlendingAndTiming[], - int HActive[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], + unsigned int HActive[], double HRatio[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double SwathWidthSingleDPPY[], double SwathWidthSingleDPPC[], double SwathWidthY[], double SwathWidthC[], - int MaximumSwathHeightY[], - int MaximumSwathHeightC[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[]) + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[]) { (void)BytePerPixY; enum odm_combine_mode MainPlaneODMCombine; @@ -6960,8 +6960,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels) @@ -7006,8 +7006,8 @@ static double CalculateExtraLatencyBytes( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels) @@ -7061,7 +7061,7 @@ static noinline_for_stack void UseMinimumDCFCLK( int ReorderingBytes) { struct vba_vars_st *v = &mode_lib->vba; - int dummy1; + unsigned int dummy1; unsigned int j, k; unsigned int i; double NormalEfficiency, dummy2, dummy3; @@ -7081,7 +7081,7 @@ static noinline_for_stack void UseMinimumDCFCLK( double ExtraLatencyBytes; double ExtraLatencyCycles; double DCFCLKRequiredForPeakBandwidth; - int NoOfDPPState[DC__NUM_DPP__MAX]; + unsigned int NoOfDPPState[DC__NUM_DPP__MAX]; double MinimumTvmPlus2Tr0; TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0; @@ -7226,7 +7226,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize( int CompressedBufferSegmentSizeInkByteFinal, enum output_encoder_class *Output, bool *UnboundedRequestEnabled, - int *CompressedBufferSizeInkByte) + unsigned int *CompressedBufferSizeInkByte) { double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64); @@ -7244,7 +7244,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize( dml_print("DML::%s: UseUnboundedRequestingFinal = %d\n", __func__, UseUnboundedRequestingFinal); dml_print("DML::%s: actDETBufferSizeInKByte = %f\n", __func__, actDETBufferSizeInKByte); dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, *UnboundedRequestEnabled); - dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte); + dml_print("DML::%s: CompressedBufferSizeInkByte = %u\n", __func__, *CompressedBufferSizeInkByte); #endif } diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c index d6dcebb1ab14..dd9dc0c8cb43 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c @@ -166,7 +166,7 @@ static bool CalculatePrefetchSchedule( double *Tdmdl_vm, double *Tdmdl, double *TSetup, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix); static double RoundToDFSGranularityUp(double Clock, double VCOSpeed); @@ -227,19 +227,19 @@ static unsigned int CalculateVMAndRowBytes( unsigned int *MetaRowByte, unsigned int *PixelPTEBytesPerRow, bool *PTEBufferSizeNotExceeded, - int *dpte_row_width_ub, + unsigned int *dpte_row_width_ub, unsigned int *dpte_row_height, unsigned int *MetaRequestWidth, unsigned int *MetaRequestHeight, unsigned int *meta_row_width, unsigned int *meta_row_height, - int *vm_group_bytes, + unsigned int *vm_group_bytes, unsigned int *dpte_group_bytes, unsigned int *PixelPTEReqWidth, unsigned int *PixelPTEReqHeight, unsigned int *PTERequestSize, - int *DPDE0BytesFrame, - int *MetaPTEBytesFrame); + unsigned int *DPDE0BytesFrame, + unsigned int *MetaPTEBytesFrame); static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime); static void CalculateRowBandwidth( bool GPUVMEnable, @@ -294,7 +294,7 @@ static void CalculateVupdateAndDynamicMetadataParameters( double *Tdmbf, double *Tdmec, double *Tdmsks, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix); @@ -327,8 +327,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], @@ -386,7 +386,7 @@ static void CalculatePixelDeliveryTimes( double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], @@ -411,35 +411,35 @@ static void CalculateMetaAndPTETimes( bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, - int HTotal[], + unsigned int HTotal[], double VRatio[], double VRatioChroma[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], - int dpte_row_height[], - int dpte_row_height_chroma[], - int meta_row_width[], - int meta_row_width_chroma[], - int meta_row_height[], - int meta_row_height_chroma[], - int meta_req_width[], - int meta_req_width_chroma[], - int meta_req_height[], - int meta_req_height_chroma[], - int dpte_group_bytes[], - int PTERequestSizeY[], - int PTERequestSizeC[], - int PixelPTEReqWidthY[], - int PixelPTEReqHeightY[], - int PixelPTEReqWidthC[], - int PixelPTEReqHeightC[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], @@ -462,18 +462,18 @@ static void CalculateVMGroupAndRequestTimes( bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], - int vm_group_bytes[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], - int meta_pte_bytes_per_frame_ub_l[], - int meta_pte_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], @@ -501,29 +501,29 @@ static void CalculateStutterEfficiency( bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], unsigned int DETBufferSizeY[], - int BytePerPixelY[], + unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], double NetDCCRateLuma[], double NetDCCRateChroma[], double DCCFractionOfZeroSizeRequestsLuma[], double DCCFractionOfZeroSizeRequestsChroma[], - int HTotal[], - int VTotal[], + unsigned int HTotal[], + unsigned int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], - int BlockHeight256BytesY[], - int BlockWidth256BytesY[], - int BlockHeight256BytesC[], - int BlockWidth256BytesC[], - int DCCYMaxUncompressedBlock[], - int DCCCMaxUncompressedBlock[], - int VActive[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], @@ -547,32 +547,32 @@ static void CalculateSwathAndDETConfiguration( enum scan_direction_class SourceScan[], enum source_format_class SourcePixelFormat[], enum dm_swizzle_mode SurfaceTiling[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], enum odm_combine_mode ODMCombineEnabled[], - int BlendingAndTiming[], - int BytePerPixY[], - int BytePerPixC[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], double BytePerPixDETY[], double BytePerPixDETC[], - int HActive[], + unsigned int HActive[], double HRatio[], double HRatioChroma[], - int DPPPerPlane[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], double SwathWidth[], double SwathWidthChroma[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], @@ -582,31 +582,31 @@ static void CalculateSwathWidth( int NumberOfActivePlanes, enum source_format_class SourcePixelFormat[], enum scan_direction_class SourceScan[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], enum odm_combine_mode ODMCombineEnabled[], - int BytePerPixY[], - int BytePerPixC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], - int BlendingAndTiming[], - int HActive[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], + unsigned int HActive[], double HRatio[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double SwathWidthSingleDPPY[], double SwathWidthSingleDPPC[], double SwathWidthY[], double SwathWidthC[], - int MaximumSwathHeightY[], - int MaximumSwathHeightC[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[]); + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[]); static double CalculateExtraLatency( int RoundTripPingLatencyCycles, @@ -620,8 +620,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels); @@ -635,8 +635,8 @@ static double CalculateExtraLatencyBytes( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels); @@ -660,7 +660,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize( int CompressedBufferSegmentSizeInkByteFinal, enum output_encoder_class *Output, bool *UnboundedRequestEnabled, - int *CompressedBufferSizeInkByte); + unsigned int *CompressedBufferSizeInkByte); static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output); static unsigned int CalculateMaxVStartup( @@ -887,7 +887,7 @@ static bool CalculatePrefetchSchedule( double *Tdmdl_vm, double *Tdmdl, double *TSetup, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix) { @@ -1835,19 +1835,19 @@ static unsigned int CalculateVMAndRowBytes( unsigned int *MetaRowByte, unsigned int *PixelPTEBytesPerRow, bool *PTEBufferSizeNotExceeded, - int *dpte_row_width_ub, + unsigned int *dpte_row_width_ub, unsigned int *dpte_row_height, unsigned int *MetaRequestWidth, unsigned int *MetaRequestHeight, unsigned int *meta_row_width, unsigned int *meta_row_height, - int *vm_group_bytes, + unsigned int *vm_group_bytes, unsigned int *dpte_group_bytes, unsigned int *PixelPTEReqWidth, unsigned int *PixelPTEReqHeight, unsigned int *PTERequestSize, - int *DPDE0BytesFrame, - int *MetaPTEBytesFrame) + unsigned int *DPDE0BytesFrame, + unsigned int *MetaPTEBytesFrame) { (void)SourcePixelFormat; struct vba_vars_st *v = &mode_lib->vba; @@ -3297,18 +3297,18 @@ static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib) // Display Pipe Configuration double BytePerPixDETY[DC__NUM_DPP__MAX]; double BytePerPixDETC[DC__NUM_DPP__MAX]; - int BytePerPixY[DC__NUM_DPP__MAX]; - int BytePerPixC[DC__NUM_DPP__MAX]; - int Read256BytesBlockHeightY[DC__NUM_DPP__MAX]; - int Read256BytesBlockHeightC[DC__NUM_DPP__MAX]; - int Read256BytesBlockWidthY[DC__NUM_DPP__MAX]; - int Read256BytesBlockWidthC[DC__NUM_DPP__MAX]; + unsigned int BytePerPixY[DC__NUM_DPP__MAX]; + unsigned int BytePerPixC[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockHeightY[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockHeightC[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockWidthY[DC__NUM_DPP__MAX]; + unsigned int Read256BytesBlockWidthC[DC__NUM_DPP__MAX]; double dummy1[DC__NUM_DPP__MAX]; double dummy2[DC__NUM_DPP__MAX]; double dummy3[DC__NUM_DPP__MAX]; double dummy4[DC__NUM_DPP__MAX]; - int dummy5[DC__NUM_DPP__MAX]; - int dummy6[DC__NUM_DPP__MAX]; + unsigned int dummy5[DC__NUM_DPP__MAX]; + unsigned int dummy6[DC__NUM_DPP__MAX]; bool dummy7[DC__NUM_DPP__MAX]; bool dummysinglestring; @@ -3535,7 +3535,7 @@ static void CalculateVupdateAndDynamicMetadataParameters( double *Tdmbf, double *Tdmec, double *Tdmsks, - int *VUpdateOffsetPix, + unsigned int *VUpdateOffsetPix, double *VUpdateWidthPix, double *VReadyOffsetPix) { @@ -3897,7 +3897,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ unsigned int i; unsigned int k, m; int ReorderingBytes; - int MinPrefetchMode = 0, MaxPrefetchMode = 2; + unsigned int MinPrefetchMode = 0, MaxPrefetchMode = 2; bool NoChroma = true; bool EnoughWritebackUnits = true; bool P2IWith420 = false; @@ -5205,7 +5205,7 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_ double HostVMInefficiencyFactor = 1; int NextPrefetchModeState = MinPrefetchMode; bool UnboundedRequestEnabledThisState = false; - int CompressedBufferSizeInkByteThisState = 0; + unsigned int CompressedBufferSizeInkByteThisState = 0; double dummy; v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j]; @@ -5867,8 +5867,8 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateDCFCLKDeepSleep( struct display_mode_lib *mode_lib, unsigned int NumberOfActivePlanes, - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], double VRatio[], double VRatioChroma[], double SwathWidthY[], @@ -6019,7 +6019,7 @@ static void CalculatePixelDeliveryTimes( double PSCL_THROUGHPUT[], double PSCL_THROUGHPUT_CHROMA[], double DPPCLK[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], unsigned int NumberOfCursors[], unsigned int CursorWidth[][DC__NUM_CURSOR__MAX], @@ -6144,35 +6144,35 @@ static void CalculateMetaAndPTETimes( bool GPUVMEnable, int MetaChunkSize, int MinMetaChunkSizeBytes, - int HTotal[], + unsigned int HTotal[], double VRatio[], double VRatioChroma[], double DestinationLinesToRequestRowInVBlank[], double DestinationLinesToRequestRowInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int BytePerPixelY[], - int BytePerPixelC[], + unsigned int BytePerPixelY[], + unsigned int BytePerPixelC[], enum scan_direction_class SourceScan[], - int dpte_row_height[], - int dpte_row_height_chroma[], - int meta_row_width[], - int meta_row_width_chroma[], - int meta_row_height[], - int meta_row_height_chroma[], - int meta_req_width[], - int meta_req_width_chroma[], - int meta_req_height[], - int meta_req_height_chroma[], - int dpte_group_bytes[], - int PTERequestSizeY[], - int PTERequestSizeC[], - int PixelPTEReqWidthY[], - int PixelPTEReqHeightY[], - int PixelPTEReqWidthC[], - int PixelPTEReqHeightC[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], + unsigned int dpte_row_height[], + unsigned int dpte_row_height_chroma[], + unsigned int meta_row_width[], + unsigned int meta_row_width_chroma[], + unsigned int meta_row_height[], + unsigned int meta_row_height_chroma[], + unsigned int meta_req_width[], + unsigned int meta_req_width_chroma[], + unsigned int meta_req_height[], + unsigned int meta_req_height_chroma[], + unsigned int dpte_group_bytes[], + unsigned int PTERequestSizeY[], + unsigned int PTERequestSizeC[], + unsigned int PixelPTEReqWidthY[], + unsigned int PixelPTEReqHeightY[], + unsigned int PixelPTEReqWidthC[], + unsigned int PixelPTEReqHeightC[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], double DST_Y_PER_PTE_ROW_NOM_L[], double DST_Y_PER_PTE_ROW_NOM_C[], double DST_Y_PER_META_ROW_NOM_L[], @@ -6317,18 +6317,18 @@ static void CalculateVMGroupAndRequestTimes( bool GPUVMEnable, unsigned int GPUVMMaxPageTableLevels, unsigned int HTotal[], - int BytePerPixelC[], + unsigned int BytePerPixelC[], double DestinationLinesToRequestVMInVBlank[], double DestinationLinesToRequestVMInImmediateFlip[], bool DCCEnable[], double PixelClock[], - int dpte_row_width_luma_ub[], - int dpte_row_width_chroma_ub[], - int vm_group_bytes[], + unsigned int dpte_row_width_luma_ub[], + unsigned int dpte_row_width_chroma_ub[], + unsigned int vm_group_bytes[], unsigned int dpde0_bytes_per_frame_ub_l[], unsigned int dpde0_bytes_per_frame_ub_c[], - int meta_pte_bytes_per_frame_ub_l[], - int meta_pte_bytes_per_frame_ub_c[], + unsigned int meta_pte_bytes_per_frame_ub_l[], + unsigned int meta_pte_bytes_per_frame_ub_c[], double TimePerVMGroupVBlank[], double TimePerVMGroupFlip[], double TimePerVMRequestVBlank[], @@ -6436,29 +6436,29 @@ static void CalculateStutterEfficiency( bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], unsigned int DETBufferSizeY[], - int BytePerPixelY[], + unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], double NetDCCRateLuma[], double NetDCCRateChroma[], double DCCFractionOfZeroSizeRequestsLuma[], double DCCFractionOfZeroSizeRequestsChroma[], - int HTotal[], - int VTotal[], + unsigned int HTotal[], + unsigned int VTotal[], double PixelClock[], double VRatio[], enum scan_direction_class SourceScan[], - int BlockHeight256BytesY[], - int BlockWidth256BytesY[], - int BlockHeight256BytesC[], - int BlockWidth256BytesC[], - int DCCYMaxUncompressedBlock[], - int DCCCMaxUncompressedBlock[], - int VActive[], + unsigned int BlockHeight256BytesY[], + unsigned int BlockWidth256BytesY[], + unsigned int BlockHeight256BytesC[], + unsigned int BlockWidth256BytesC[], + unsigned int DCCYMaxUncompressedBlock[], + unsigned int DCCCMaxUncompressedBlock[], + unsigned int VActive[], bool DCCEnable[], bool WritebackEnable[], double ReadBandwidthPlaneLuma[], @@ -6742,40 +6742,40 @@ static void CalculateSwathAndDETConfiguration( enum scan_direction_class SourceScan[], enum source_format_class SourcePixelFormat[], enum dm_swizzle_mode SurfaceTiling[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], enum odm_combine_mode ODMCombineEnabled[], - int BlendingAndTiming[], - int BytePerPixY[], - int BytePerPixC[], + unsigned int BlendingAndTiming[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], double BytePerPixDETY[], double BytePerPixDETC[], - int HActive[], + unsigned int HActive[], double HRatio[], double HRatioChroma[], - int DPPPerPlane[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[], + unsigned int DPPPerPlane[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[], double SwathWidth[], double SwathWidthChroma[], - int SwathHeightY[], - int SwathHeightC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], unsigned int DETBufferSizeY[], unsigned int DETBufferSizeC[], bool ViewportSizeSupportPerPlane[], bool *ViewportSizeSupport) { (void)HRatioChroma; - int MaximumSwathHeightY[DC__NUM_DPP__MAX]; - int MaximumSwathHeightC[DC__NUM_DPP__MAX]; + unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX]; + unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX]; int MinimumSwathHeightY; int MinimumSwathHeightC; unsigned int RoundedUpMaxSwathSizeBytesY; @@ -6919,31 +6919,31 @@ static void CalculateSwathWidth( int NumberOfActivePlanes, enum source_format_class SourcePixelFormat[], enum scan_direction_class SourceScan[], - int ViewportWidth[], - int ViewportHeight[], - int SurfaceWidthY[], - int SurfaceWidthC[], - int SurfaceHeightY[], - int SurfaceHeightC[], + unsigned int ViewportWidth[], + unsigned int ViewportHeight[], + unsigned int SurfaceWidthY[], + unsigned int SurfaceWidthC[], + unsigned int SurfaceHeightY[], + unsigned int SurfaceHeightC[], enum odm_combine_mode ODMCombineEnabled[], - int BytePerPixY[], - int BytePerPixC[], - int Read256BytesBlockHeightY[], - int Read256BytesBlockHeightC[], - int Read256BytesBlockWidthY[], - int Read256BytesBlockWidthC[], - int BlendingAndTiming[], - int HActive[], + unsigned int BytePerPixY[], + unsigned int BytePerPixC[], + unsigned int Read256BytesBlockHeightY[], + unsigned int Read256BytesBlockHeightC[], + unsigned int Read256BytesBlockWidthY[], + unsigned int Read256BytesBlockWidthC[], + unsigned int BlendingAndTiming[], + unsigned int HActive[], double HRatio[], - int DPPPerPlane[], + unsigned int DPPPerPlane[], double SwathWidthSingleDPPY[], double SwathWidthSingleDPPC[], double SwathWidthY[], double SwathWidthC[], - int MaximumSwathHeightY[], - int MaximumSwathHeightC[], - int swath_width_luma_ub[], - int swath_width_chroma_ub[]) + unsigned int MaximumSwathHeightY[], + unsigned int MaximumSwathHeightC[], + unsigned int swath_width_luma_ub[], + unsigned int swath_width_chroma_ub[]) { (void)BytePerPixY; enum odm_combine_mode MainPlaneODMCombine; @@ -7049,8 +7049,8 @@ static double CalculateExtraLatency( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels) @@ -7095,8 +7095,8 @@ static double CalculateExtraLatencyBytes( bool GPUVMEnable, bool HostVMEnable, int NumberOfActivePlanes, - int NumberOfDPP[], - int dpte_group_bytes[], + unsigned int NumberOfDPP[], + unsigned int dpte_group_bytes[], double HostVMInefficiencyFactor, double HostVMMinPageSize, int HostVMMaxNonCachedPageTableLevels) @@ -7147,7 +7147,7 @@ static noinline_for_stack void UseMinimumDCFCLK( int ReorderingBytes) { struct vba_vars_st *v = &mode_lib->vba; - int dummy1, j; + unsigned int dummy1, j; unsigned int i, k; double NormalEfficiency, dummy2, dummy3; double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2]; @@ -7166,7 +7166,7 @@ static noinline_for_stack void UseMinimumDCFCLK( double ExtraLatencyBytes; double ExtraLatencyCycles; double DCFCLKRequiredForPeakBandwidth; - int NoOfDPPState[DC__NUM_DPP__MAX]; + unsigned int NoOfDPPState[DC__NUM_DPP__MAX]; double MinimumTvmPlus2Tr0; TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0; @@ -7314,7 +7314,7 @@ static void CalculateUnboundedRequestAndCompressedBufferSize( int CompressedBufferSegmentSizeInkByteFinal, enum output_encoder_class *Output, bool *UnboundedRequestEnabled, - int *CompressedBufferSizeInkByte) + unsigned int *CompressedBufferSizeInkByte) { double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64); diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index 03e49d298a85..1b1ab6a6d53a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -1400,7 +1400,7 @@ static void try_odm_power_optimization_and_revalidate( display_e2e_pipe_params_st *pipes, int *split, bool *merge, - unsigned int *vlevel, + int *vlevel, int pipe_cnt) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c index 8a2dbb4a2fbb..15f5248340a7 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c @@ -2954,7 +2954,7 @@ void dml32_UseMinimumDCFCLK( unsigned int VTotal[], unsigned int VActive[], unsigned int DynamicMetadataTransmittedBytes[], - unsigned int DynamicMetadataLinesBeforeActiveRequired[], + int DynamicMetadataLinesBeforeActiveRequired[], bool Interlace[], double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX], double RequiredDISPCLK[][2], @@ -5631,7 +5631,7 @@ void dml32_CalculateStutterEfficiency( bool Interlace[], double MinTTUVBlank[], unsigned int DPPPerSurface[], - unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeY[], unsigned int BytePerPixelY[], double BytePerPixelDETY[], double SwathWidthY[], @@ -5663,10 +5663,10 @@ void dml32_CalculateStutterEfficiency( /* Output */ double *StutterEfficiencyNotIncludingVBlank, double *StutterEfficiency, - unsigned int *NumberOfStutterBurstsPerFrame, + int *NumberOfStutterBurstsPerFrame, double *Z8StutterEfficiencyNotIncludingVBlank, double *Z8StutterEfficiency, - unsigned int *Z8NumberOfStutterBurstsPerFrame, + int *Z8NumberOfStutterBurstsPerFrame, double *StutterPeriod, bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE) { diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h index 5d34735df83d..9ea36f3ff27c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h @@ -614,7 +614,7 @@ void dml32_UseMinimumDCFCLK( unsigned int VTotal[], unsigned int VActive[], unsigned int DynamicMetadataTransmittedBytes[], - unsigned int DynamicMetadataLinesBeforeActiveRequired[], + int DynamicMetadataLinesBeforeActiveRequired[], bool Interlace[], double RequiredDPPCLKPerSurface[][2][DC__NUM_DPP__MAX], double RequiredDISPCLK[][2], @@ -1013,7 +1013,7 @@ void dml32_CalculateStutterEfficiency( bool ProgressiveToInterlaceUnitInOPP, bool Interlace[], double MinTTUVBlank[], - unsigned int DPPPerSurface[], + unsigned int DPPPerSurface[], unsigned int DETBufferSizeY[], unsigned int BytePerPixelY[], double BytePerPixelDETY[], @@ -1046,10 +1046,10 @@ void dml32_CalculateStutterEfficiency( /* Output */ double *StutterEfficiencyNotIncludingVBlank, double *StutterEfficiency, - unsigned int *NumberOfStutterBurstsPerFrame, + int *NumberOfStutterBurstsPerFrame, double *Z8StutterEfficiencyNotIncludingVBlank, double *Z8StutterEfficiency, - unsigned int *Z8NumberOfStutterBurstsPerFrame, + int *Z8NumberOfStutterBurstsPerFrame, double *StutterPeriod, bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE); diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 07993741f5e6..cde84dfb0953 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -472,7 +472,7 @@ struct vba_vars_st { unsigned int VTotal[DC__NUM_DPP__MAX]; unsigned int VTotal_Max[DC__NUM_DPP__MAX]; unsigned int VTotal_Min[DC__NUM_DPP__MAX]; - int DPPPerPlane[DC__NUM_DPP__MAX]; + unsigned int DPPPerPlane[DC__NUM_DPP__MAX]; double PixelClock[DC__NUM_DPP__MAX]; double PixelClockBackEnd[DC__NUM_DPP__MAX]; bool DCCEnable[DC__NUM_DPP__MAX]; @@ -739,7 +739,7 @@ struct vba_vars_st { /* ms locals */ double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2]; unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; - int NoOfDPPThisState[DC__NUM_DPP__MAX]; + unsigned int NoOfDPPThisState[DC__NUM_DPP__MAX]; enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX]; double SwathWidthYThisState[DC__NUM_DPP__MAX]; unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; @@ -900,7 +900,7 @@ struct vba_vars_st { int PTEBufferSizeInRequestsForChroma; // Missing from VBA - int dpte_group_bytes_chroma; + unsigned int dpte_group_bytes_chroma; unsigned int vm_group_bytes_chroma; double dst_x_after_scaler; double dst_y_after_scaler; @@ -1100,8 +1100,8 @@ struct vba_vars_st { unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX]; bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX]; bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX]; - int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX]; - int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX]; + unsigned int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX]; + unsigned int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX]; double UrgLatency[DC__VOLTAGE_STATES]; double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX]; @@ -1172,7 +1172,7 @@ struct vba_vars_st { int ConfigReturnBufferSizeInKByte; enum unbounded_requesting_policy UseUnboundedRequesting; int CompressedBufferSegmentSizeInkByte; - int CompressedBufferSizeInkByte; + unsigned int CompressedBufferSizeInkByte; int MetaFIFOSizeInKEntries; int ZeroSizeBufferEntries; int COMPBUF_RESERVED_SPACE_64B; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c index 2b8afe46ff1c..53b21adc6267 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c @@ -307,7 +307,7 @@ void dpp1_cm_set_output_csc_default( { struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); const uint16_t *regval = NULL; - int arr_size; + uint32_t arr_size; regval = find_color_matrix(colorspace, &arr_size); if (regval == NULL) { diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index d24f02d201f4..8faffc2993b4 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -548,7 +548,7 @@ bool dpp3_get_optimal_number_of_taps( static void dpp3_deferred_update(struct dpp *dpp_base) { - int bypass_state; + uint32_t bypass_state; struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); if (dpp_base->deferred_reg_writes.bits.disable_dscl) { diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c index 8170a86ad0ea..99581f35e54b 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c @@ -317,7 +317,7 @@ void dpp3_set_hdr_multiplier( static void program_gamut_remap( struct dcn3_dpp *dpp, const uint16_t *regval, - int select) + unsigned int select) { uint16_t selection = 0; struct color_matrices_reg gam_regs; @@ -379,7 +379,7 @@ void dpp3_cm_set_gamut_remap( { struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); int i = 0; - int gamut_mode; + uint32_t gamut_mode; if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) /* Bypass if type is bypass or hw */ diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 8dcdda46ee1e..9aa5adb15103 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -1336,7 +1336,7 @@ uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing, uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps( const struct dc_crtc_timing *timing, - const int num_slices_h, + const uint32_t num_slices_h, const bool is_dp) { struct fixed31_32 max_dsc_overhead; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index 7ee31cae5959..cede9588bad8 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -228,9 +228,9 @@ bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) { struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); - int dsc_clock_en; - int dsc_fw_config; - int enabled_opp_pipe; + uint32_t dsc_clock_en; + uint32_t dsc_fw_config; + uint32_t enabled_opp_pipe; DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); @@ -253,7 +253,7 @@ void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) void dsc2_disable(struct display_stream_compressor *dsc) { struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); - int dsc_clock_en; + uint32_t dsc_clock_en; DC_LOG_DSC("disable DSC %d", dsc->inst); diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c index 17acb64a9d80..d84c3399d386 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c @@ -79,9 +79,9 @@ void dsc35_construct(struct dcn20_dsc *dsc, static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe) { struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); - int dsc_clock_en; - int dsc_fw_config; - int enabled_opp_pipe; + uint32_t dsc_clock_en; + uint32_t dsc_fw_config; + uint32_t enabled_opp_pipe; DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); @@ -96,7 +96,7 @@ static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe) REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { - DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); + DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe); ASSERT(0); } diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index 363e83ad21db..749547960046 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -145,16 +145,16 @@ void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_c void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe) { struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); - int dsc_clock_en; - int dsc_fw_config; - int enabled_opp_pipe; + uint32_t dsc_clock_en; + uint32_t dsc_fw_config; + uint32_t enabled_opp_pipe; DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { - DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); + DC_LOG_DSC("ERROR: DSC %d at opp pipe %u already enabled!", dsc->inst, enabled_opp_pipe); ASSERT(0); } @@ -170,7 +170,7 @@ void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe) void dsc401_disable(struct display_stream_compressor *dsc) { struct dcn401_dsc *dsc401 = TO_DCN401_DSC(dsc); - int dsc_clock_en; + uint32_t dsc_clock_en; DC_LOG_DSC("disable DSC %d", dsc->inst); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index 3c7a6569b692..302515128358 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -63,10 +63,10 @@ void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable) REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, enable ? 1 : 0); } -int hubp401_get_3dlut_fl_done(struct hubp *hubp) +uint32_t hubp401_get_3dlut_fl_done(struct hubp *hubp) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - int ret; + uint32_t ret; REG_GET(HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, &ret); return ret; diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h index 4570b8016de5..4116834c552d 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h @@ -324,7 +324,7 @@ bool hubp401_construct( void hubp401_init(struct hubp *hubp); -int hubp401_get_3dlut_fl_done(struct hubp *hubp); +uint32_t hubp401_get_3dlut_fl_done(struct hubp *hubp); void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 305860cb775a..3a6e3a0d18b0 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -2485,7 +2485,8 @@ void dcn10_enable_vblanks_synchronization( (void)group_index; struct output_pixel_processor *opp; struct timing_generator *tg; - int i, width = 0, height = 0, master; + int i, master; + uint32_t width = 0, height = 0; DC_LOGGER_INIT(dc->ctx); @@ -2551,7 +2552,8 @@ void dcn10_enable_timing_synchronization( (void)group_index; struct output_pixel_processor *opp; struct timing_generator *tg; - int i, width = 0, height = 0; + int i; + uint32_t width = 0, height = 0; DC_LOGGER_INIT(dc->ctx); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index 408d417318c2..09dfbb16dd29 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -147,7 +147,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) // Given any pipe_ctx, return the total ODM combine factor, and optionally return // the OPPids which are used -static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) +static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances) { unsigned int opp_count = 1; struct pipe_ctx *odm_pipe; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index fd42f0afc3a9..415b3f875f0d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -1119,7 +1119,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) * Given any pipe_ctx, return the total ODM combine factor, and optionally return * the OPPids which are used * */ -static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) +static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances) { unsigned int opp_count = 1; struct pipe_ctx *odm_pipe; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index a094c8b40a85..1a0123338dfa 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -403,7 +403,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) // Given any pipe_ctx, return the total ODM combine factor, and optionally return // the OPPids which are used -static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_instances) +static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, int *opp_instances) { unsigned int opp_count = 1; struct pipe_ctx *odm_pipe; diff --git a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h index d567d4bd585d..3fdd9a770334 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h +++ b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h @@ -126,7 +126,7 @@ static inline struct bw_fixed bw_div(const struct bw_fixed arg1, const struct bw static inline struct bw_fixed bw_mod(const struct bw_fixed arg1, const struct bw_fixed arg2) { struct bw_fixed res; - div64_u64_rem(arg1.value, arg2.value, (uint64_t *)&res.value); + div64_u64_rem((uint64_t)arg1.value, (uint64_t)arg2.value, (uint64_t *)&res.value); return res; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 0530b214c4b6..1c18898aa475 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -305,7 +305,7 @@ struct hubp_funcs { enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); - int (*hubp_get_3dlut_fl_done)(struct hubp *hubp); + uint32_t (*hubp_get_3dlut_fl_done)(struct hubp *hubp); void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg); void (*hubp_clear_tiling)(struct hubp *hubp); uint32_t (*hubp_get_current_read_line)(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index e1428a83ecbc..73cc34ea7726 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -356,8 +356,8 @@ struct opp_funcs { void (*opp_program_dpg_dimensions)( struct output_pixel_processor *opp, - int width, - int height); + uint32_t width, + uint32_t height); bool (*dpg_is_blanked)( struct output_pixel_processor *opp); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 2f70bb476c97..3a80369cde16 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -32,9 +32,9 @@ struct dc_bios; /* Contains CRTC vertical/horizontal pixel counters */ struct crtc_position { - int32_t vertical_count; - int32_t horizontal_count; - int32_t nominal_vcount; + uint32_t vertical_count; + uint32_t horizontal_count; + uint32_t nominal_vcount; }; struct dcp_gsl_params { @@ -321,7 +321,7 @@ struct timing_generator { const struct timing_generator_funcs *funcs; struct dc_bios *bp; struct dc_context *ctx; - int inst; + uint32_t inst; }; struct dc_crtc_timing; diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_service.h b/drivers/gpu/drm/amd/display/dc/inc/link_service.h index 57bb82e94942..d0609443af49 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_service.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_service.h @@ -110,7 +110,7 @@ struct link_service { struct dc_sink *(*add_remote_sink)( struct dc_link *link, const uint8_t *edid, - int len, + unsigned int len, struct dc_sink_init_data *init_data); void (*remove_remote_sink)(struct dc_link *link, struct dc_sink *sink); bool (*get_hpd_state)(struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h index 26cb1459b743..7a1ecb8d986f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h +++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h @@ -155,63 +155,63 @@ * read given register and fill in field value in output parameter */ #define REG_GET(reg_name, field, val) \ generic_reg_get(CTX, REG(reg_name), \ - FN(reg_name, field), val) + FN(reg_name, field), (uint32_t *)val) #define REG_GET_2(reg_name, f1, v1, f2, v2) \ generic_reg_get2(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2) #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \ generic_reg_get3(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2, \ - FN(reg_name, f3), v3) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2, \ + FN(reg_name, f3), (uint32_t *)v3) #define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \ generic_reg_get4(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2, \ - FN(reg_name, f3), v3, \ - FN(reg_name, f4), v4) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2, \ + FN(reg_name, f3), (uint32_t *)v3, \ + FN(reg_name, f4), (uint32_t *)v4) #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ generic_reg_get5(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2, \ - FN(reg_name, f3), v3, \ - FN(reg_name, f4), v4, \ - FN(reg_name, f5), v5) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2, \ + FN(reg_name, f3), (uint32_t *)v3, \ + FN(reg_name, f4), (uint32_t *)v4, \ + FN(reg_name, f5), (uint32_t *)v5) #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ generic_reg_get6(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2, \ - FN(reg_name, f3), v3, \ - FN(reg_name, f4), v4, \ - FN(reg_name, f5), v5, \ - FN(reg_name, f6), v6) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2, \ + FN(reg_name, f3), (uint32_t *)v3, \ + FN(reg_name, f4), (uint32_t *)v4, \ + FN(reg_name, f5), (uint32_t *)v5, \ + FN(reg_name, f6), (uint32_t *)v6) #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ generic_reg_get7(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2, \ - FN(reg_name, f3), v3, \ - FN(reg_name, f4), v4, \ - FN(reg_name, f5), v5, \ - FN(reg_name, f6), v6, \ - FN(reg_name, f7), v7) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2, \ + FN(reg_name, f3), (uint32_t *)v3, \ + FN(reg_name, f4), (uint32_t *)v4, \ + FN(reg_name, f5), (uint32_t *)v5, \ + FN(reg_name, f6), (uint32_t *)v6, \ + FN(reg_name, f7), (uint32_t *)v7) #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ generic_reg_get8(CTX, REG(reg_name), \ - FN(reg_name, f1), v1, \ - FN(reg_name, f2), v2, \ - FN(reg_name, f3), v3, \ - FN(reg_name, f4), v4, \ - FN(reg_name, f5), v5, \ - FN(reg_name, f6), v6, \ - FN(reg_name, f7), v7, \ - FN(reg_name, f8), v8) + FN(reg_name, f1), (uint32_t *)v1, \ + FN(reg_name, f2), (uint32_t *)v2, \ + FN(reg_name, f3), (uint32_t *)v3, \ + FN(reg_name, f4), (uint32_t *)v4, \ + FN(reg_name, f5), (uint32_t *)v5, \ + FN(reg_name, f6), (uint32_t *)v6, \ + FN(reg_name, f7), (uint32_t *)v7, \ + FN(reg_name, f8), (uint32_t *)v8) /* macro to poll and wait for a register field to read back given value */ diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 026c55ca0196..1ac6a22fecfe 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -1562,7 +1562,7 @@ static bool link_add_remote_sink_helper(struct dc_link *dc_link, struct dc_sink struct dc_sink *link_add_remote_sink( struct dc_link *link, const uint8_t *edid, - int len, + unsigned int len, struct dc_sink_init_data *init_data) { struct dc_sink *dc_sink; diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.h b/drivers/gpu/drm/amd/display/dc/link/link_detection.h index 1ab29476060b..e8d29fa1550d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.h +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.h @@ -32,7 +32,7 @@ bool link_detect_connection_type(struct dc_link *link, struct dc_sink *link_add_remote_sink( struct dc_link *link, const uint8_t *edid, - int len, + unsigned int len, struct dc_sink_init_data *init_data); void link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink); bool link_reset_cur_dp_mst_topology(struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 6aa65815af22..72b5921227d2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -47,9 +47,9 @@ #define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B /* Travis */ -static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; +static const char DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; /* Nutmeg */ -static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; +static const char DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode) { @@ -1210,9 +1210,9 @@ int edp_get_backlight_level(const struct dc_link *link) fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight) - return panel_cntl->funcs->get_current_backlight(panel_cntl); + return (int)panel_cntl->funcs->get_current_backlight(panel_cntl); else if (abm != NULL && abm->funcs->get_current_backlight != NULL) - return (int) abm->funcs->get_current_backlight(abm); + return (int)abm->funcs->get_current_backlight(abm); else return DC_ERROR_UNEXPECTED; } diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c index 0779db249765..0f2294bedcc3 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c @@ -375,7 +375,7 @@ void mpc1_mpc_init(struct mpc *mpc) void mpc1_mpc_init_single_inst(struct mpc *mpc, unsigned int mpcc_id) { struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); - int opp_id; + uint32_t opp_id; REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c index 4e91e9f6f11a..d7a07e29d23a 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn30/dcn30_mpc.c @@ -1067,7 +1067,7 @@ static void program_gamut_remap( struct dcn30_mpc *mpc30, int mpcc_id, const uint16_t *regval, - int select) + uint32_t select) { uint16_t selection = 0; struct color_matrices_reg gam_regs; @@ -1129,7 +1129,7 @@ void mpc3_set_gamut_remap( { struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); int i = 0; - int gamut_mode; + uint32_t gamut_mode; if (adjust->gamut_adjust_type != GRAPHICS_GAMUT_ADJUST_TYPE_SW) program_gamut_remap(mpc30, mpcc_id, NULL, GAMUT_REMAP_BYPASS); @@ -1201,7 +1201,7 @@ void mpc3_get_gamut_remap(struct mpc *mpc, { struct dcn30_mpc *mpc30 = TO_DCN30_MPC(mpc); uint16_t arr_reg_val[12] = {0}; - int select; + uint32_t select; read_gamut_remap(mpc30, mpcc_id, arr_reg_val, &select); diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c index ce826a5be4c7..83730bbe26a8 100644 --- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c +++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.c @@ -293,7 +293,7 @@ void opp2_set_disp_pattern_generator( void opp2_program_dpg_dimensions( struct output_pixel_processor *opp, - int width, int height) + uint32_t width, uint32_t height) { struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp); diff --git a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h index fb0c047c1788..8944fa6c8f79 100644 --- a/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h +++ b/drivers/gpu/drm/amd/display/dc/opp/dcn20/dcn20_opp.h @@ -156,7 +156,7 @@ void opp2_set_disp_pattern_generator( void opp2_program_dpg_dimensions( struct output_pixel_processor *opp, - int width, int height); + uint32_t width, uint32_t height); bool opp2_dpg_is_blanked(struct output_pixel_processor *opp); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 60e546b69a05..07895d5f4dfa 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -101,7 +101,7 @@ static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, i void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments) { struct optc *optc1 = DCN10TG_FROM_TG(tg); - int segments; + uint32_t segments; REG_GET(OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, &segments); diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h index 990fa1f19c22..109093311984 100644 --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h @@ -445,7 +445,7 @@ static inline struct fixed31_32 dc_fixpt_pow(struct fixed31_32 arg1, struct fixe */ static inline int dc_fixpt_floor(struct fixed31_32 arg) { - unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value; + unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value); if (arg.value >= 0) return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); @@ -459,7 +459,7 @@ static inline int dc_fixpt_floor(struct fixed31_32 arg) */ static inline int dc_fixpt_round(struct fixed31_32 arg) { - unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value; + unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value); const long long summand = dc_fixpt_half.value; @@ -479,7 +479,7 @@ static inline int dc_fixpt_round(struct fixed31_32 arg) */ static inline int dc_fixpt_ceil(struct fixed31_32 arg) { - unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value; + unsigned long long arg_value = (unsigned long long)(arg.value > 0 ? arg.value : -arg.value); const long long summand = dc_fixpt_one.value - dc_fixpt_epsilon.value; diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c index 5cb979c2cf8c..1164fd96b714 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c @@ -44,7 +44,7 @@ void mod_hdcp_dump_binary_message(uint8_t *msg, uint32_t msg_size, for (i = 0; i < msg_size; i++) { if (i % bytes_per_line == 0) buf[buf_pos++] = '\n'; - sprintf(&buf[buf_pos], "%02X ", msg[i]); + sprintf((char *)&buf[buf_pos], "%02X ", msg[i]); buf_pos += byte_size; } buf[buf_pos++] = '\0'; From 0b19e2bd18cd95594cda64e8da24bccffbce0d10 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Mon, 20 Apr 2026 11:47:11 -0400 Subject: [PATCH 39/71] drm/amd/display: only call pmfw if smu present flags true [Why & How] for fault safe case: only call pmfw if smu present flags true and default to 2 channle for bios intergration info table error. Reviewed-by: Alvin Lee Signed-off-by: Charlene Liu Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c index 245a217894a7..d856a7a807b1 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -1078,10 +1078,11 @@ void dcn42_clk_mgr_construct( dcn42_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type; dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4; - dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1; - clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); - clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base); - + dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 2; + if (clk_mgr->base.smu_present) { + clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base); + clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); + } clk_mgr->base.base.bw_params = &dcn42_bw_params; if (clk_mgr->base.smu_present) From 615c3102e9673910b9dd160b3a8267657f8907b9 Mon Sep 17 00:00:00 2001 From: Matthew Stewart Date: Thu, 2 Apr 2026 17:42:54 -0400 Subject: [PATCH 40/71] drm/amd/display: Refactor dc_link_aux_transfer_raw [Why & How] The logic for choosing between the dce_aux_transfer function variants is moved into dce_aux.c rather than link_ddc.c. The "dce_aux_transfer_with_retries" function now uses dce_aux_transfer_raw in its implementation as the logic is equivalent. Reviewed-by: Nevenko Stupar Reviewed-by: Gabe Teeger Signed-off-by: Matthew Stewart Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 20 ++++++++++++------- drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 4 ++++ .../amd/display/dc/link/protocols/link_ddc.c | 7 +------ 3 files changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c index eee58f946fae..181944ce77ab 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c @@ -559,6 +559,18 @@ static enum i2caux_transaction_action i2caux_action_from_payload(struct aux_payl int dce_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *payload, enum aux_return_code_type *operation_result) +{ + if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc || + !ddc->ddc_pin) { + return dce_aux_transfer_dmub_raw(ddc, payload, operation_result); + } else { + return dce_aux_transfer_raw_with_ddc_pin(ddc, payload, operation_result); + } +} + +int dce_aux_transfer_raw_with_ddc_pin(struct ddc_service *ddc, + struct aux_payload *payload, + enum aux_return_code_type *operation_result) { struct ddc *ddc_pin = ddc->ddc_pin; struct dce_aux *aux_engine; @@ -740,13 +752,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, if (payload->write) dce_aux_log_payload(" write", payload->data, payload->length, 16); - /* Check whether aux to be processed via dmub or dcn directly */ - if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc - || ddc->ddc_pin == NULL) { - ret = dce_aux_transfer_dmub_raw(ddc, payload, &operation_result); - } else { - ret = dce_aux_transfer_raw(ddc, payload, &operation_result); - } + ret = dce_aux_transfer_raw(ddc, payload, &operation_result); DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION, LOG_FLAG_I2cAux_DceAux, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h index c850ed49281f..8f4745694016 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h @@ -304,6 +304,10 @@ int dce_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *cmd, enum aux_return_code_type *operation_result); +int dce_aux_transfer_raw_with_ddc_pin(struct ddc_service *ddc, + struct aux_payload *cmd, + enum aux_return_code_type *operation_result); + int dce_aux_transfer_dmub_raw(struct ddc_service *ddc, struct aux_payload *payload, enum aux_return_code_type *operation_result); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c index 1bf0903a3cf8..a0ea853f5f64 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c @@ -401,12 +401,7 @@ int link_aux_transfer_raw(struct ddc_service *ddc, struct aux_payload *payload, enum aux_return_code_type *operation_result) { - if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc || - !ddc->ddc_pin) { - return dce_aux_transfer_dmub_raw(ddc, payload, operation_result); - } else { - return dce_aux_transfer_raw(ddc, payload, operation_result); - } + return dce_aux_transfer_raw(ddc, payload, operation_result); } uint32_t link_get_fixed_vs_pe_retimer_write_address(struct dc_link *link) From 293dd2182e64331727f989a323fb40227f07bcbf Mon Sep 17 00:00:00 2001 From: Rafal Ostrowski Date: Tue, 21 Apr 2026 17:15:50 +0200 Subject: [PATCH 41/71] drm/amd/display: Introduce dc_plane_cm and migrate surface update color path [Why] Introduce dc_plane_cm struct. TRIM_CM2 flag is used to synchronize between old and new implementation. [How] Introduce dc_plane_cm struct. Reviewed-by: Dillon Varone Signed-off-by: Rafal Ostrowski Signed-off-by: James Lin Signed-off-by: Alex Deucher --- .../dml2_0/dml21/dml21_translation_helper.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c index d89fd876975e..25557c99a28e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c @@ -613,6 +613,7 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm plane->composition.viewport.stationary = false; +#ifndef TRIM_CM2 if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { plane->tdlut.setup_for_tdlut = true; @@ -643,7 +644,39 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm break; } } +#else + if (plane_state->cm.flags.bits.lut3d_dma_enable) { + plane->tdlut.setup_for_tdlut = true; + switch (plane_state->cm.lut3d_dma.swizzle) { + case CM_LUT_3D_SWIZZLE_LINEAR_RGB: + case CM_LUT_3D_SWIZZLE_LINEAR_BGR: + plane->tdlut.tdlut_addressing_mode = dml2_tdlut_sw_linear; + break; + case CM_LUT_1D_PACKED_LINEAR: + plane->tdlut.tdlut_addressing_mode = dml2_tdlut_simple_linear; + break; + } + + switch (plane_state->cm.lut3d_dma.size) { + case CM_LUT_SIZE_171717: + plane->tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube; + break; + case CM_LUT_SIZE_333333: + plane->tdlut.tdlut_width_mode = dml2_tdlut_width_33_cube; + break; + // handling when use case and HW support available + case CM_LUT_SIZE_454545: + case CM_LUT_SIZE_656565: + break; + case CM_LUT_SIZE_NONE: + case CM_LUT_SIZE_999: + default: + //plane->tdlut.tdlut_width_mode = dml2_tdlut_width_flatten; // dml2_tdlut_width_flatten undefined + break; + } + } +#endif // TRIM_CM2 plane->tdlut.setup_for_tdlut |= dml_ctx->config.force_tdlut_enable; plane->dynamic_meta_data.enable = false; From a349b97b88e26a88171b8672cee744cac2cff5ae Mon Sep 17 00:00:00 2001 From: Gaghik Khachatrian Date: Wed, 29 Apr 2026 20:05:29 -0400 Subject: [PATCH 42/71] drm/amd/display: always-true lower-bound assert [Why] A recent type change made the lower-bound part of the OTG instance assert redundant, which can trigger static-analysis noise and distract from actionable diagnostics. [How] Kept the meaningful upper-bound range validation required for safe narrowing to uint8_t. Removed the redundant non-negative portion of the assert so the check matches current type semantics. Revalidated with the latest debug build log: no warnings and no build-failure markers. Reviewed-by: Aric Cyr Signed-off-by: Gaghik Khachatrian Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c index 1bc81e26a11f..5ed14f694fb0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c @@ -255,7 +255,7 @@ static void populate_pipe_ctx_dlg_params_from_dml(struct pipe_ctx *pipe_ctx, str pipe_ctx->pipe_dlg_param.vupdate_width = dml_get_vupdate_width(mode_lib, pipe_idx); pipe_ctx->pipe_dlg_param.vready_offset = dml_get_vready_offset(mode_lib, pipe_idx); - ASSERT(pipe_ctx->stream_res.tg->inst >= 0 && pipe_ctx->stream_res.tg->inst <= 0xFF); + ASSERT(pipe_ctx->stream_res.tg->inst <= 0xFF); pipe_ctx->pipe_dlg_param.otg_inst = (unsigned char)pipe_ctx->stream_res.tg->inst; pipe_ctx->pipe_dlg_param.hactive = hactive; From 254a47ce0c8a52ff78a60f92a13b56db69f69096 Mon Sep 17 00:00:00 2001 From: Lohita Mudimela Date: Tue, 10 Mar 2026 17:46:01 +0530 Subject: [PATCH 43/71] drm/amd/display: Separate ABM functions into dedicated power_abm.c file [Why] Improves code organization by separating Adaptive Backlight Modulation functionality from general power management. This modular approach enhances maintainability and makes the codebase easier to navigate. [How] Create new power_abm.c file containing all ABM-related functions moved from power.c. Remove static qualifier from shared functions to enable cross-file access: - initialize_backlight_caps: Initialize backlight capabilities - validate_ext_backlight_caps: Validate external backlight capabilities - backlight_millipercent_to_pwm: Convert brightness percent to PWM - backlight_millipercent_to_millinit: Convert brightness percent to nits - fill_backlight_level_params: Populate backlight level parametersAdd function declarations to mod_power.h header. Update CMakeLists.txt to include power_abm.c in build. Maintain forward declaration of struct core_power for type compatibility. Rename struct core_power field from 'public' to 'mod_public'. Move internal structures (backlight_state, backlight_properties, dmcu_varibright_cached_properties, core_power) to power_helpers.h to ensure consistent memory layouts across compilation units. Reviewed-by: Martin Leung Signed-off-by: Lohita Mudimela Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../drm/amd/display/modules/inc/mod_power.h | 25 + .../drm/amd/display/modules/power/Makefile | 2 +- .../gpu/drm/amd/display/modules/power/power.c | 1209 +-------- .../drm/amd/display/modules/power/power_abm.c | 2160 +++++++++++++++++ .../amd/display/modules/power/power_helpers.c | 815 ------- .../amd/display/modules/power/power_helpers.h | 1 + 6 files changed, 2194 insertions(+), 2018 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/modules/power/power_abm.c diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_power.h b/drivers/gpu/drm/amd/display/modules/inc/mod_power.h index 89037f7b7961..440e4284b6f0 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_power.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_power.h @@ -5,6 +5,8 @@ #include "dm_services.h" +struct core_power; + struct mod_power_init_params { bool disable_fractional_pwm; @@ -412,4 +414,27 @@ bool mod_power_backlight_nits_to_percent(struct mod_power *mod_power, unsigned int backlight_millinit, unsigned int *backlight_millipercent); +void initialize_backlight_caps(struct core_power *core_power, unsigned int inst); + +unsigned int backlight_millipercent_to_pwm( + struct core_power *core_power, unsigned int millipercent, unsigned int inst); + +unsigned int backlight_millipercent_to_millinit( + struct core_power *core_power, unsigned int millipercent, unsigned int inst); + +void fill_backlight_level_params(struct core_power *core_power, + struct set_backlight_level_params *backlight_level_params, + int panel_inst, uint8_t aux_inst, unsigned int backlight_pwm, + enum backlight_control_type backlight_control_type, + unsigned int backlight_millinit, unsigned int transition_time_millisec, + bool is_hdr); + +bool mod_power_hw_init_backlight(struct mod_power *mod_power); + +void mod_power_update_backlight_on_mode_change( + struct core_power *core_power, + struct dc_link *link, + unsigned int panel_inst, + uint8_t aux_inst, + bool is_hdr); #endif /* MODULES_INC_MOD_POWER_H_ */ diff --git a/drivers/gpu/drm/amd/display/modules/power/Makefile b/drivers/gpu/drm/amd/display/modules/power/Makefile index b27a1ff3d86b..dd11f7d5617d 100644 --- a/drivers/gpu/drm/amd/display/modules/power/Makefile +++ b/drivers/gpu/drm/amd/display/modules/power/Makefile @@ -23,7 +23,7 @@ # Makefile for the 'power' sub-module of DAL. # -MOD_POWER = power_helpers.o power.o +MOD_POWER = power_helpers.o power.o power_abm.o AMD_DAL_MOD_POWER = $(addprefix $(AMDDALPATH)/modules/power/,$(MOD_POWER)) #$(info ************ DAL POWER MODULE MAKEFILE ************) diff --git a/drivers/gpu/drm/amd/display/modules/power/power.c b/drivers/gpu/drm/amd/display/modules/power/power.c index 1ee671119ddd..f8a0b252c745 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power.c +++ b/drivers/gpu/drm/amd/display/modules/power/power.c @@ -114,7 +114,7 @@ struct dmcu_varibright_cached_properties { }; struct core_power { - struct mod_power public; + struct mod_power mod_public; struct dc *dc; struct power_entity *map; struct dmcu_varibright_cached_properties varibright_prop; @@ -153,7 +153,7 @@ static const unsigned int default_ac_backlight_percent = 100; static const unsigned int default_dc_backlight_percent = 70; #define MOD_POWER_TO_CORE(mod_power)\ - container_of(mod_power, struct core_power, public) + container_of(mod_power, struct core_power, mod_public) static unsigned int calc_psr_num_static_frames(unsigned int vsync_rate_hz) { @@ -199,467 +199,12 @@ static unsigned int map_index_from_stream(struct core_power *core_power, return 0; } -static uint16_t backlight_8_to_16(unsigned int backlight_8bit) -{ - return (uint16_t)(backlight_8bit * 0x101); -} - - -static unsigned int backlight_millipercent_to_millinit( - struct core_power *core_power, unsigned int millipercent, unsigned int inst) -{ - unsigned int millinit = 0; - unsigned long long numerator = 0; - - if (core_power == NULL) - return 0; - - numerator = ((unsigned long long)millipercent) * - core_power->bl_prop[inst].nits_range; - millinit = ((unsigned int)div_u64(numerator, 100000)) + - core_power->bl_prop[inst].min_brightness_millinits; - - return millinit; -} - -static unsigned int backlight_millinit_to_millipercent( - struct core_power *core_power, unsigned int millinit, unsigned int inst) -{ - unsigned int millipercent = 0; - unsigned long long numerator = 0; - - if (core_power == NULL) - return 0; - - if (millinit <= core_power->bl_prop[inst].min_brightness_millinits) - return 0; - - if (millinit >= core_power->bl_prop[inst].max_brightness_millinits) - return (100 * 1000); - - numerator = (((unsigned long long)millinit) - - core_power->bl_prop[inst].min_brightness_millinits) * 100000; - millipercent = ((unsigned int)div_u64(numerator, - core_power->bl_prop[inst].nits_range)); - - return millipercent; -} - -static unsigned int backlight_pwm_to_millipercent( - struct core_power *core_power, unsigned int pwm, unsigned int inst) -{ - unsigned int millipercent = 0; - unsigned int max_index = 0; - - if (core_power == NULL) - return 0; - - if (!core_power->bl_prop[inst].backlight_caps_valid) - return 0; - - /* Doesn't really make sense to have one single backlight level - * possible... - */ - if (core_power->bl_prop[inst].num_backlight_levels < 2) - return 0; - - max_index = core_power->bl_prop[inst].num_backlight_levels - 1; - - if (pwm <= core_power->bl_prop[inst].backlight_lut[0]) - return 0; - - if (pwm > core_power->bl_prop[inst].backlight_lut[max_index]) - return (100 * 1000); - - /* We need to do a binary search over the array for where the pwm level - * is in the lut. Based on the index we can determine percentage. - */ - unsigned int min = 0; - unsigned int max = max_index; - unsigned int mid = 0; - - while (max >= min) { - mid = (min + max) / 2; /* floor of half range */ - - if (core_power->bl_prop[inst].backlight_lut[mid] < pwm) - min = mid + 1; - else if (core_power->bl_prop[inst].backlight_lut[mid] > pwm) - max = mid - 1; - else - break; - } - - /* In this case, exact match is not found. Check if mid/min/max - * value is actually closer. - */ - if (max < min) { - unsigned int min_delta; - unsigned int mid_delta; - unsigned int max_delta; - - min_delta = (core_power->bl_prop[inst].backlight_lut[min] > pwm) ? - core_power->bl_prop[inst].backlight_lut[min] - pwm : - pwm - core_power->bl_prop[inst].backlight_lut[min]; - - mid_delta = (core_power->bl_prop[inst].backlight_lut[mid] > pwm) ? - core_power->bl_prop[inst].backlight_lut[mid] - pwm : - pwm - core_power->bl_prop[inst].backlight_lut[mid]; - - max_delta = (core_power->bl_prop[inst].backlight_lut[max] > pwm) ? - core_power->bl_prop[inst].backlight_lut[max] - pwm : - pwm - core_power->bl_prop[inst].backlight_lut[max]; - - if ((min_delta < mid_delta) && (min_delta < max_delta)) - mid = min; - - if ((max_delta < mid_delta) && (max_delta < min_delta)) - mid = max; - } - - /* No interpolation, just take closest index */ - millipercent = 1000 * 100 * mid / max_index; - - return millipercent; -} - -static unsigned int backlight_pwm_to_millinit( - struct core_power *core_power, unsigned int pwm, unsigned int inst) -{ - unsigned int millinit = 0; - - if (core_power == NULL) - return 0; - - if (pwm <= core_power->bl_prop[inst].min_backlight_pwm) - return core_power->bl_prop[inst].min_brightness_millinits; - - if (pwm >= core_power->bl_prop[inst].max_backlight_pwm) - return core_power->bl_prop[inst].max_brightness_millinits; - - millinit = ((unsigned int)div_u64(((unsigned long long)pwm - - core_power->bl_prop[inst].min_backlight_pwm) * - core_power->bl_prop[inst].nits_range, - core_power->bl_prop[inst].backlight_range)); - - millinit += core_power->bl_prop[inst].min_brightness_millinits; - - if (millinit > core_power->bl_prop[inst].max_brightness_millinits) - millinit = core_power->bl_prop[inst].max_brightness_millinits; - - return millinit; -} - -static unsigned int backlight_millipercent_to_pwm( - struct core_power *core_power, unsigned int millipercent, unsigned int inst) -{ - unsigned int pwm = (unsigned int)-1; - unsigned int index = 0; - - if (core_power == NULL) - return 0; - - // Bypass the brightness mapping LUT - if (core_power->bl_prop->use_linear_backlight_curve) { - pwm = core_power->bl_prop[inst].min_backlight_pwm + - (unsigned int) div_u64((unsigned long long) millipercent * - core_power->bl_prop[inst].backlight_range, - 100000); - - if (pwm > core_power->bl_prop[inst].max_backlight_pwm) - pwm = core_power->bl_prop[inst].max_backlight_pwm; - - return pwm; - } - - if (millipercent >= (100 * 1000)) - return core_power->bl_prop[inst].backlight_lut[core_power->bl_prop[inst].num_backlight_levels - 1]; - - /* This will give the floor index. */ - index = ((core_power->bl_prop[inst].num_backlight_levels - 1) * - millipercent) / 100000; - /* Null check otherwise eDP doesn't lightup when connected to DP1 */ - if (core_power->bl_prop[inst].backlight_lut == NULL) - return pwm; - - pwm = core_power->bl_prop[inst].backlight_lut[index]; - - return pwm; -} - -static unsigned int backlight_millinit_to_pwm( - struct core_power *core_power, unsigned int millinit, unsigned int inst) -{ - unsigned int pwm = 0; - - if (core_power == NULL) - return 0; - - /* For nits based brightness, the signal will be a value - * between the minimum and maximum value. - */ - if (millinit >= core_power->bl_prop[inst].max_brightness_millinits) - return core_power->bl_prop[inst].max_backlight_pwm; - else if (millinit <= core_power->bl_prop[inst].min_brightness_millinits) - return core_power->bl_prop[inst].min_backlight_pwm; - - pwm = ((unsigned int)div_u64(((unsigned long long)millinit - - core_power->bl_prop[inst].min_brightness_millinits) * - core_power->bl_prop[inst].backlight_range, - core_power->bl_prop[inst].nits_range)); - - pwm += core_power->bl_prop[inst].min_backlight_pwm; - - if (pwm > core_power->bl_prop[inst].max_backlight_pwm) - pwm = core_power->bl_prop[inst].max_backlight_pwm; - - return pwm; -} - -static bool validate_ext_backlight_caps( - struct dm_acpi_atif_backlight_caps *ext_backlight_caps) -{ - unsigned int i; - unsigned int num_of_data_points = 0; - unsigned int last_signal_level = 0; - unsigned int last_luminance = 0; - - num_of_data_points = ext_backlight_caps->num_data_points; - - /* Validation rules: - * 1. BIOS should carry customized data points and - * the number of data points should not be larger than 99. - * 2. The max_input_signal should be larger than min_input_signal. - * 3. For each data point: - * a. luminance should be in ascending order and - * should not be 0 or 100 since the corresponding signal_level - * are assigned by min_input_signal and max_input_signal. - * b. signal_level should be in ascending order and - * be within the range of min/max_input_signal. - */ - if (num_of_data_points > BL_DATA_POINTS) - return false; - - if (ext_backlight_caps->min_input_signal >= ext_backlight_caps->max_input_signal) - return false; - - last_signal_level = ext_backlight_caps->min_input_signal; - for (i = 0; i < num_of_data_points; i++) { - unsigned int luminance = ext_backlight_caps->data_points[i].luminance; - unsigned int signal_level = ext_backlight_caps->data_points[i].signal_level; - - if ((luminance <= last_luminance) || (luminance > BL_DATA_POINTS)) - return false; - - if ((signal_level <= last_signal_level) || (signal_level >= ext_backlight_caps->max_input_signal)) - return false; - - last_signal_level = signal_level; - last_luminance = luminance; - } - - return true; -} - -/* hard coded to default backlight curve. */ -static void initialize_backlight_caps(struct core_power *core_power, unsigned int inst) -{ - unsigned int i; - struct dm_acpi_atif_backlight_caps *ext_backlight_caps = NULL; - bool custom_curve_present = false; - unsigned int num_levels = 0; - struct dc *dc = NULL; - enum dm_acpi_display_type acpi_display_type = - (inst == 0) ? AcpiDisplayType_LCD1 : AcpiDisplayType_LCD2; - - if (core_power == NULL) - return; - dc = core_power->dc; - - num_levels = core_power->bl_prop[inst].num_backlight_levels; - - /* Allocate memory for ATIF output - * (do not want to use 256 bytes on the stack) - */ - ext_backlight_caps = (struct dm_acpi_atif_backlight_caps *) - (kzalloc(sizeof(struct dm_acpi_atif_backlight_caps), - GFP_KERNEL)); - - if (ext_backlight_caps == NULL) - return; - - /* Retrieve ACPI extended brightness caps */ - if (dm_query_extended_brightness_caps - (dc->ctx, acpi_display_type, ext_backlight_caps)) { - custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps); - } - - if (core_power->bl_prop[inst].use_custom_backlight_caps && - fill_custom_backlight_caps( - core_power->bl_prop[inst].custom_backlight_caps_config_no, - ext_backlight_caps)) { - custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps); - } - - if (custom_curve_present) { - unsigned int index = 1; - unsigned int num_of_data_points = ext_backlight_caps->num_data_points; - - core_power->bl_prop[inst].ac_backlight_percent = - ext_backlight_caps->ac_level_percentage; - core_power->bl_prop[inst].dc_backlight_percent = - ext_backlight_caps->dc_level_percentage; - core_power->bl_prop[inst].backlight_lut[0] = - backlight_8_to_16( - ext_backlight_caps->min_input_signal); - core_power->bl_prop[inst].backlight_lut[num_levels - 1] = - backlight_8_to_16( - ext_backlight_caps->max_input_signal); - - /* Filling translation table from data points - - * between every two provided data points we - * lineary interpolate missing values - */ - for (i = 0; i < num_of_data_points; i++) { - unsigned int luminance = - ext_backlight_caps->data_points[i].luminance; - unsigned int signal_level = - backlight_8_to_16( - ext_backlight_caps->data_points[i].signal_level); - - /* Since luminance is a percentage, scale it by num_levels*/ - luminance = (luminance * num_levels) / 101; - - /* Lineary interpolate missing values */ - if (index < luminance) { - unsigned int base_value = - core_power->bl_prop[inst].backlight_lut[index-1]; - unsigned int delta_signal = - signal_level - base_value; - unsigned int delta_luma = - luminance - index + 1; - unsigned int step = delta_signal; - - for (; index < luminance; index++) { - core_power->bl_prop[inst].backlight_lut[index] = - base_value + (step / delta_luma); - step += delta_signal; - } - } - - /* Now [index == luminance], - * so we can add data point to the translation table - */ - core_power->bl_prop[inst].backlight_lut[index++] = signal_level; - } - - /* Complete the final segment of interpolation - - * between last datapoint and maximum value - */ - if (index < num_levels - 1) { - unsigned int base_value = - core_power->bl_prop[inst].backlight_lut[index-1]; - unsigned int delta_signal = - core_power->bl_prop[inst].backlight_lut[num_levels - 1] - - base_value; - unsigned int delta_luma = num_levels - index; - unsigned int step = delta_signal; - - for (; index < num_levels - 1; index++) { - core_power->bl_prop[inst].backlight_lut[index] = - base_value + (step / delta_luma); - step += delta_signal; - } - } - /* Build backlight translation table based on default curve */ - } else { - /* Defines default backlight curve F(x) = A(x*x) + Bx + C. - * - * Backlight curve should always satisfy: - * F(0) = min, F(100) = max, - * So polynom coefficients are: - * A is 0.0255 - B/100 - min/10000 - (255-max)/10000 = - * (max - min)/10000 - B/100 - * B is adjustable factor to modify the curve. - * Bigger B results in less concave curve. - * B range is [0..(max-min)/100] - * C is backlight minimum - */ - unsigned int backlight_curve_coeff_a_factor = - num_levels * num_levels; - unsigned int backlight_curve_coeff_b = num_levels; - unsigned int delta = - core_power->bl_prop[inst].backlight_lut[num_levels - 1] - - core_power->bl_prop[inst].backlight_lut[0]; - unsigned int coeffC = core_power->bl_prop[inst].backlight_lut[0]; - unsigned int coeffB = - (backlight_curve_coeff_b < delta ? - backlight_curve_coeff_b : delta); - unsigned long long coeffA = delta - coeffB; /* coeffB is B*100 */ - - for (i = 1; i < num_levels - 1; i++) { - uint64_t lut_val = div_u64(coeffA * i * i, backlight_curve_coeff_a_factor) + - div_u64((uint64_t)coeffB * i, backlight_curve_coeff_b) + coeffC; - - ASSERT(lut_val <= 0xFFFFFFFF); - core_power->bl_prop[inst].backlight_lut[i] = (unsigned int)lut_val; - } - } - - if (ext_backlight_caps != NULL) - kfree(ext_backlight_caps); - - /* Successfully initialized */ - core_power->bl_prop[inst].backlight_caps_valid = true; -} - -static void varibright_set_level(struct core_power *core_power) -{ - if (!core_power->varibright_prop.varibright_active || - !core_power->varibright_prop.varibright_user_enable) - core_power->varibright_prop.varibright_hw_level = 0; - else - core_power->varibright_prop.varibright_hw_level = - core_power->varibright_prop.varibright_level; -} - bool mod_power_hw_init(struct mod_power *mod_power) { - struct core_power *core_power = NULL; - struct dc *dc = NULL; - struct dmcu *dmcu = NULL; - struct dmcu_iram_parameters params; - unsigned int i; + /* Call backlight initialization */ + return mod_power_hw_init_backlight(mod_power); - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - dc = core_power->dc; - - for (i = 0; i < core_power->edp_num; i++) { - params.set = core_power->varibright_prop.varibright_config_setting; - params.backlight_ramping_override = core_power->bl_prop[i].backlight_ramping_override; - params.backlight_ramping_reduction = core_power->bl_prop[i].backlight_ramping_reduction; - params.backlight_ramping_start = core_power->bl_prop[i].backlight_ramping_start; - params.backlight_lut_array = core_power->bl_prop[i].backlight_lut; - params.backlight_lut_array_size = core_power->bl_prop[i].num_backlight_levels; - params.min_abm_backlight = core_power->bl_prop[i].min_abm_backlight; - - dmcu = dc->res_pool->dmcu; - - // In the case where abm is implemented on dmcub, - // dmcu object will be null. - // ABM 2.4 and up are implemented on dmcub. - if (dmcu) { - //DMCU does not support multiple eDP - return dmcu_load_iram(dmcu, params); - } else if (dc->ctx->dmub_srv) { - if (!dmub_init_abm_config(dc->res_pool, params, i)) - return false; - } else - return false; - } - return true; + /* Future: Add other HW init here */ } struct mod_power *mod_power_create(struct dc *dc, @@ -829,7 +374,7 @@ struct mod_power *mod_power_create(struct dc *dc, core_power->bl_state[inst].backlight_millipercent, inst); } - return &core_power->public; + return &core_power->mod_public; fail_bad_brightness_range: fail_alloc_backlight_array: @@ -1020,531 +565,6 @@ bool mod_power_replace_stream(struct mod_power *mod_power, return true; } -static bool set_backlight_millinits_aux(struct core_power *core_power, - struct dc_stream_state *stream, - unsigned int backlight_millinits, - unsigned int transition_time_millisec, - unsigned int inst) -{ - struct dc_link *link = NULL; - - if (core_power == NULL) - return false; - - if (stream == NULL) - return true; - - link = dc_stream_get_link(stream); - - return dc_link_set_backlight_level_nits(link, core_power->bl_state[inst].isHDR, - backlight_millinits, transition_time_millisec); -} - -static bool set_backlight(struct core_power *core_power, - struct dc_stream_state *stream, - struct set_backlight_level_params *backlight_level_params, - unsigned int inst) -{ - bool retv = false; - unsigned int frame_ramp = 0; - unsigned int vsync_rate_hz; - union dmcu_abm_set_bl_params params; - const struct dc_link *link = NULL; - unsigned int backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16; - unsigned int transition_time_millisec = backlight_level_params->transition_time_in_ms; - - if (core_power == NULL) - return false; - - core_power->bl_state[inst].backlight_pwm = backlight_pwm_u16_16; - - if (stream == NULL) - return true; - - if (stream->link->connector_signal != SIGNAL_TYPE_EDP) - return false; - - if (transition_time_millisec != 0) { - unsigned int v_total = - (stream->adjust.v_total_max == 0) ? stream->timing.v_total : stream->adjust.v_total_max; - - vsync_rate_hz = (unsigned int)div_u64(div_u64((stream-> - timing.pix_clk_100hz * 100), - v_total), - stream->timing.h_total); - - if (core_power->bl_state[inst].smooth_brightness_enabled) - frame_ramp = ((vsync_rate_hz * - transition_time_millisec) + 500) / 1000; - } - - core_power->bl_state[inst].frame_ramp = frame_ramp; - params.u32All = 0; - params.bits.gradual_change = (frame_ramp > 0); - params.bits.frame_ramp = frame_ramp; - link = dc_stream_get_link(stream); - - mod_power_set_psr_event(&core_power->public, stream, true, psr_event_hw_programming, true); - mod_power_set_replay_event(&core_power->public, stream, true, replay_event_hw_programming, true); - - backlight_level_params->frame_ramp = params.u32All; - retv = dc_link_set_backlight_level(link, backlight_level_params); - - mod_power_set_psr_event(&core_power->public, stream, false, psr_event_hw_programming, false); - mod_power_set_replay_event(&core_power->public, stream, false, replay_event_hw_programming, false); - - return retv; -} - -static void fill_backlight_level_params(struct core_power *core_power, - struct set_backlight_level_params *backlight_level_params, - int panel_inst, uint8_t aux_inst, unsigned int backlight_pwm, - enum backlight_control_type backlight_control_type, - unsigned int backlight_millinit, unsigned int transition_time_millisec, - bool is_hdr) -{ - struct pwr_backlight_properties *bl_prop = &core_power->bl_prop[panel_inst]; - - backlight_level_params->aux_inst = aux_inst; - backlight_level_params->backlight_pwm_u16_16 = backlight_pwm; - backlight_level_params->control_type = backlight_control_type; - backlight_level_params->backlight_millinits = backlight_millinit; - backlight_level_params->transition_time_in_ms = transition_time_millisec; - backlight_level_params->min_luminance = bl_prop->min_brightness_millinits; - backlight_level_params->max_luminance = bl_prop->max_brightness_millinits; - backlight_level_params->min_backlight_pwm = bl_prop->min_backlight_pwm; - backlight_level_params->max_backlight_pwm = bl_prop->max_backlight_pwm; - - if (backlight_control_type == BACKLIGHT_CONTROL_AMD_AUX && !is_hdr) - backlight_level_params->control_type = BACKLIGHT_CONTROL_PWM; -} - -bool mod_power_set_backlight_nits(struct mod_power *mod_power, - struct dc_stream_state *stream, - unsigned int backlight_millinit, - unsigned int transition_time_millisec, - bool skip_aux, - bool is_hdr) -{ - struct core_power *core_power = NULL; - unsigned int backlight_pwm; - unsigned int panel_inst = 0; - struct set_backlight_level_params backlight_level_params = { 0 }; - const struct dc_link *link = NULL; - uint8_t aux_inst = 0; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - link = dc_stream_get_link(stream); - - ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF); - aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel; - - if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst)) - return false; - - if (!skip_aux) { - if (!set_backlight_millinits_aux(core_power, stream, - backlight_millinit, transition_time_millisec, panel_inst)) - return false; - } -// always send both AUX (above) and PWM (below) - core_power->bl_state[panel_inst].backlight_millinit = backlight_millinit; - - core_power->bl_state[panel_inst].backlight_millipercent = - backlight_millinit_to_millipercent( - core_power, backlight_millinit, panel_inst); - - backlight_pwm = backlight_millinit_to_pwm( - core_power, backlight_millinit, panel_inst); - - fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst, backlight_pwm, - link->backlight_control_type, backlight_millinit, transition_time_millisec, is_hdr); - - return set_backlight(core_power, stream, - &backlight_level_params, panel_inst); -} - - -bool mod_power_backlight_percent_to_nits(struct mod_power *mod_power, - struct dc_stream_state *stream, - unsigned int backlight_millipercent, - unsigned int *backlight_millinit) -{ - struct core_power *core_power = NULL; - unsigned int inst = 0; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) - return false; - - *backlight_millinit = backlight_millipercent_to_millinit( - core_power, backlight_millipercent, inst); - return true; -} - -bool mod_power_backlight_nits_to_percent(struct mod_power *mod_power, - struct dc_stream_state *stream, - unsigned int backlight_millinit, - unsigned int *backlight_millipercent) -{ - struct core_power *core_power = NULL; - unsigned int inst = 0; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) - return false; - - *backlight_millipercent = backlight_millinit_to_millipercent( - core_power, backlight_millinit, inst); - return true; -} - -bool mod_power_set_backlight_percent(struct mod_power *mod_power, - struct dc_stream_state *stream, - unsigned int backlight_millipercent, - unsigned int transition_time_millisec, - bool is_hdr) -{ - struct core_power *core_power = NULL; - struct set_backlight_level_params backlight_level_params = { 0 }; - const struct dc_link *link = NULL; - unsigned int backlight_pwm; - unsigned int panel_inst = 0; - uint8_t aux_inst = 0; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - link = dc_stream_get_link(stream); - ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF); - aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel; - - if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst)) - return false; - core_power->bl_state[panel_inst].backlight_millipercent = backlight_millipercent; - - core_power->bl_state[panel_inst].backlight_millinit = - backlight_millipercent_to_millinit( - core_power, backlight_millipercent, panel_inst); - - backlight_pwm = backlight_millipercent_to_pwm( - core_power, backlight_millipercent, panel_inst); - - fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, - aux_inst, backlight_pwm, link->backlight_control_type, - core_power->bl_state[panel_inst].backlight_millinit, transition_time_millisec, is_hdr); - - return set_backlight(core_power, stream, - &backlight_level_params, panel_inst); -} - -void mod_power_update_backlight(struct mod_power *mod_power, - struct dc_stream_state *stream, - unsigned int backlight_millipercent) -{ - struct core_power *core_power = NULL; - unsigned int inst = 0; - - if (mod_power == NULL) - return; - - core_power = MOD_POWER_TO_CORE(mod_power); - - if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) - return; - core_power->bl_state[inst].backlight_millipercent = backlight_millipercent; - - core_power->bl_state[inst].backlight_millinit = - backlight_millipercent_to_millinit( - core_power, backlight_millipercent, inst); - - core_power->bl_state[inst].backlight_pwm = backlight_millipercent_to_pwm( - core_power, backlight_millipercent, inst); -} - -void mod_power_update_backlight_nits(struct mod_power *mod_power, - struct dc_stream_state *stream, - unsigned int backlight_millinit) -{ - struct core_power *core_power = NULL; - unsigned int inst = 0; - - if (mod_power == NULL) - return; - - core_power = MOD_POWER_TO_CORE(mod_power); - - if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) - return; - - core_power->bl_state[inst].backlight_millinit = backlight_millinit; - - core_power->bl_state[inst].backlight_millipercent = backlight_millinit_to_millipercent( - core_power, backlight_millinit, inst); - core_power->bl_state[inst].backlight_pwm = backlight_millinit_to_pwm( - core_power, backlight_millinit, inst); -} - -bool mod_power_get_backlight_pwm(struct mod_power *mod_power, - unsigned int *backlight_pwm, - unsigned int inst) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - *backlight_pwm = core_power->bl_state[inst].backlight_pwm; - - return true; -} - -bool mod_power_get_backlight_nits(struct mod_power *mod_power, - unsigned int *backlight_millinit, - unsigned int inst) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - *backlight_millinit = core_power->bl_state[inst].backlight_millinit; - - return true; -} - -bool mod_power_get_backlight_percent(struct mod_power *mod_power, - unsigned int *backlight_millipercent, - unsigned int inst) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - *backlight_millipercent = core_power->bl_state[inst].backlight_millipercent; - - return true; -} - -bool mod_power_get_hw_target_backlight_pwm_nits(struct mod_power *mod_power, - const struct dc_link *link, - unsigned int *backlight_millinit, - unsigned int inst) -{ - struct core_power *core_power = NULL; - unsigned int backlight_u16_16 = 0; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - if (mod_power_get_hw_target_backlight_pwm(mod_power, link, - &backlight_u16_16)) { - *backlight_millinit = - backlight_pwm_to_millinit(core_power, - backlight_u16_16, inst); - return true; - } - return false; -} - -bool mod_power_get_hw_target_backlight_pwm_percent(struct mod_power *mod_power, - const struct dc_link *link, - unsigned int *backlight_millipercent, - unsigned int inst) -{ - struct core_power *core_power = NULL; - unsigned int backlight_u16_16 = 0; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - if (mod_power_get_hw_target_backlight_pwm(mod_power, link, - &backlight_u16_16)) { - *backlight_millipercent = - backlight_pwm_to_millipercent(core_power, - backlight_u16_16, inst); - return true; - } - return false; -} - -bool mod_power_get_hw_target_backlight_pwm(struct mod_power *mod_power, - const struct dc_link *link, - unsigned int *backlight_u16_16) -{ - if (mod_power == NULL) - return false; - - *backlight_u16_16 = dc_link_get_target_backlight_pwm(link); - - return true; -} - -bool mod_power_get_hw_backlight_pwm_nits(struct mod_power *mod_power, - const struct dc_link *link, - unsigned int *backlight_millinit, - unsigned int inst) -{ - struct core_power *core_power = NULL; - unsigned int backlight_u16_16 = 0; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) { - *backlight_millinit = - backlight_pwm_to_millinit(core_power, - backlight_u16_16, inst); - return true; - } - return false; -} - -bool mod_power_get_hw_backlight_aux_nits(struct mod_power *mod_power, - struct dc_stream_state **streams, int num_streams, - unsigned int *backlight_millinit_avg, - unsigned int *backlight_millinit_peak) -{ - struct core_power *core_power = NULL; - struct dc_link *link = NULL; - int stream_index; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - if (core_power == NULL) - return false; - - if (num_streams < 1) - return true; - - for (stream_index = 0; stream_index < num_streams; stream_index++) - if (streams[stream_index]->link->connector_signal == SIGNAL_TYPE_EDP || - streams[stream_index]->link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) - break; - - if (stream_index == num_streams) - return false; - - link = dc_stream_get_link(streams[stream_index]); - if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 0) - return false; - - return dc_link_get_backlight_level_nits(link, backlight_millinit_avg, - backlight_millinit_peak); -} - -bool mod_power_get_hw_backlight_pwm_percent(struct mod_power *mod_power, - const struct dc_link *link, - unsigned int *backlight_millipercent, - unsigned int inst) -{ - struct core_power *core_power = NULL; - unsigned int backlight_u16_16 = 0; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) { - *backlight_millipercent = - backlight_pwm_to_millipercent(core_power, - backlight_u16_16, inst); - return true; - } - return false; -} - -bool mod_power_get_hw_backlight_pwm(struct mod_power *mod_power, - const struct dc_link *link, - unsigned int *backlight_u16_16) -{ - if (mod_power == NULL) - return false; - - *backlight_u16_16 = dc_link_get_backlight_level(link); - - return true; -} - -bool mod_power_get_panel_backlight_boundaries( - struct mod_power *mod_power, - unsigned int *out_min_backlight, - unsigned int *out_max_backlight, - unsigned int *out_ac_backlight_percent, - unsigned int *out_dc_backlight_percent, - unsigned int inst) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - /* If cache was successfully updated, - * copy the values to output structure and return success - */ - if (core_power->bl_prop[inst].backlight_caps_valid) { - *out_min_backlight = core_power->bl_prop[inst].backlight_lut[0]; - *out_max_backlight = - core_power->bl_prop[inst].backlight_lut[ - core_power->bl_prop[inst].num_backlight_levels - 1]; - *out_ac_backlight_percent = - core_power->bl_prop[inst].ac_backlight_percent; - *out_dc_backlight_percent = - core_power->bl_prop[inst].dc_backlight_percent; - - return true; - } - - return false; -} - -bool mod_power_set_smooth_brightness(struct mod_power *mod_power, - bool enable_brightness, - unsigned int inst) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - core_power->bl_state[inst].smooth_brightness_enabled = enable_brightness; - - return true; -} - bool mod_power_notify_mode_change(struct mod_power *mod_power, const struct dc_stream_state *stream, bool is_hdr) @@ -1577,23 +597,10 @@ bool mod_power_notify_mode_change(struct mod_power *mod_power, active_psr_events = core_power->map[stream_index].psr_events; active_replay_events = core_power->map[stream_index].replay_events; if (link != NULL && dc_get_edp_link_panel_inst(dc, link, &panel_inst)) { - struct set_backlight_level_params backlight_level_params = { 0 }; - ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF); uint8_t aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel; - if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || - link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) - dc_link_set_backlight_level_nits(link, core_power->bl_state[panel_inst].isHDR, - core_power->bl_state[panel_inst].backlight_millinit, 0); - - backlight_level_params.frame_ramp = 0; - - fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst, - core_power->bl_state[panel_inst].backlight_pwm, link->backlight_control_type, - core_power->bl_state[panel_inst].backlight_millinit, 0, is_hdr); - - dc_link_set_backlight_level(link, &backlight_level_params); + mod_power_update_backlight_on_mode_change(core_power, link, panel_inst, aux_inst, is_hdr); mod_power_calc_psr_configs(&psr_config, link, stream); @@ -1643,208 +650,6 @@ bool mod_power_notify_mode_change(struct mod_power *mod_power, return true; } -bool mod_power_varibright_feature_enable(struct mod_power *mod_power, bool enable, - struct dc_stream_update *stream_update) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - core_power->varibright_prop.varibright_user_enable = enable; - - /* find abm hw level to program, and save in stream update */ - varibright_set_level(core_power); - *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; - - DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, - WPP_BIT_FLAG_Backlight_ABM, - ">ABM feature enable: enable=%u su->varibright_level=%u varibright_hw_level=%u", - (unsigned int) enable, - *stream_update->abm_level, - core_power->varibright_prop.varibright_hw_level); - return true; -} - -bool mod_power_varibright_activate(struct mod_power *mod_power, - bool activate, - struct dc_stream_update *stream_update) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - core_power->varibright_prop.varibright_active = activate; - - /* find abm hw level to program, and save in stream update */ - varibright_set_level(core_power); - *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; - - DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, - WPP_BIT_FLAG_Backlight_ABM, - ">ABM activate: activate=%u su->varibright_level=%u", - (unsigned int) activate, - *stream_update->abm_level); - return true; -} -bool mod_power_varibright_set_level(struct mod_power *mod_power, unsigned int level, - struct dc_stream_update *stream_update) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - core_power->varibright_prop.varibright_level = level; - core_power->varibright_prop.varibright_hw_level = level; - - /* find abm hw level to program, and save in stream update */ - varibright_set_level(core_power); - *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; - - DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, - WPP_BIT_FLAG_Backlight_ABM, - ">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u", - level, - core_power->varibright_prop.varibright_level, - core_power->varibright_prop.varibright_hw_level, - *stream_update->abm_level); - return true; -} - -bool mod_power_varibright_set_hw_level(struct mod_power *mod_power, unsigned int level, - struct dc_stream_update *stream_update) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - if (level == 0 || level == ABM_LEVEL_IMMEDIATE_DISABLE) - core_power->varibright_prop.varibright_active = 0; - else - core_power->varibright_prop.varibright_active = 1; - core_power->varibright_prop.varibright_hw_level = level; - *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; - - DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, - WPP_BIT_FLAG_Backlight_ABM, - ">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u", - level, - core_power->varibright_prop.varibright_level, - core_power->varibright_prop.varibright_hw_level, - *stream_update->abm_level); - return true; -} - -bool mod_power_get_varibright_level(struct mod_power *mod_power, - unsigned int *varibright_level) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - *varibright_level = core_power->varibright_prop.varibright_level; - - DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, - WPP_BIT_FLAG_Backlight_ABM, - ">get varibright level: cp->varibright_level=%u", - *varibright_level); - return true; - -} - -bool mod_power_get_varibright_hw_level(struct mod_power *mod_power, - unsigned int *varibright_level) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - *varibright_level = core_power->varibright_prop.varibright_hw_level; - DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, - WPP_BIT_FLAG_Backlight_ABM, - ">get varibright HW level: hw_level=%u", - *varibright_level); - return true; -} - -bool mod_power_get_varibright_default_level(struct mod_power *mod_power, - unsigned int *varibright_level) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - *varibright_level = core_power->varibright_prop.def_varibright_level; - DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, - WPP_BIT_FLAG_Backlight_ABM, - ">get varibright default level: def_varibright_level=%u", - *varibright_level); - return true; -} - -bool mod_power_get_varibright_enable(struct mod_power *mod_power, - bool *varibright_enable) -{ - struct core_power *core_power = NULL; - - if (mod_power == NULL) - return false; - - core_power = MOD_POWER_TO_CORE(mod_power); - - *varibright_enable = core_power->varibright_prop.varibright_user_enable; - DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, - WPP_BIT_FLAG_Backlight_ABM, - ">get varibright enable state: varibright_user_enable=%u", - (unsigned int) (*varibright_enable)); - return true; -} - -bool mod_power_is_abm_active(struct mod_power *mod_power, - const struct dc_link *link, - unsigned int inst) -{ - unsigned int user_backlight = 0; - unsigned int current_backlight = 0; - bool is_active = false; - - if (mod_power == NULL) - return false; - - mod_power_get_backlight_pwm(mod_power, &user_backlight, inst); - mod_power_get_hw_backlight_pwm(mod_power, link, ¤t_backlight); - - if (user_backlight != current_backlight) - is_active = true; - else - is_active = false; - DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, - WPP_BIT_FLAG_Backlight_ABM, - ">get ABM active state: is_active=%u (user_backlight_pwm=%u, current_backlight_pwm=%u)", - (unsigned int)is_active, - user_backlight, - current_backlight); - return is_active; -} - - static void mod_power_psr_set_power_opt(struct mod_power *mod_power, struct dc_stream_state *stream, unsigned int active_psr_events, diff --git a/drivers/gpu/drm/amd/display/modules/power/power_abm.c b/drivers/gpu/drm/amd/display/modules/power/power_abm.c new file mode 100644 index 000000000000..c41ace406519 --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/power/power_abm.c @@ -0,0 +1,2160 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "dc.h" +#include "mod_power.h" +#include "core_types.h" +#include "dmcu.h" +#include "abm.h" +#include "power_helpers.h" +#include "dce/dmub_psr.h" +#include "dal_asic_id.h" +#include "link_service.h" +#include + +#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */ +#define DC_TRACE_LEVEL_MESSAGEP(...) /* do nothing */ + +#define DIV_ROUNDUP(a, b) (((a)+((b)/2))/(b)) +#define bswap16_based_on_endian(big_endian, value) \ + ((big_endian) ? cpu_to_be16(value) : cpu_to_le16(value)) + +/* Possible Min Reduction config from least aggressive to most aggressive + * 0 1 2 3 4 5 6 7 8 9 10 11 12 + * 100 98.0 94.1 94.1 85.1 80.3 75.3 69.4 60.0 57.6 50.2 49.8 40.0 % + */ +static const unsigned char min_reduction_table[13] = { +0xff, 0xfa, 0xf0, 0xf0, 0xd9, 0xcd, 0xc0, 0xb1, 0x99, 0x93, 0x80, 0x82, 0x66}; + +/* Possible Max Reduction configs from least aggressive to most aggressive + * 0 1 2 3 4 5 6 7 8 9 10 11 12 + * 96.1 89.8 85.1 80.3 69.4 64.7 64.7 50.2 39.6 30.2 30.2 30.2 19.6 % + */ +static const unsigned char max_reduction_table[13] = { +0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0xa5, 0x80, 0x65, 0x4d, 0x4d, 0x4d, 0x32}; + +/* Possible ABM 2.2 Min Reduction configs from least aggressive to most aggressive + * 0 1 2 3 4 5 6 7 8 9 10 11 12 + * 100 100 100 100 100 100 100 100 100 92.2 83.1 75.3 75.3 % + */ +static const unsigned char min_reduction_table_v_2_2[13] = { +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0xd4, 0xc0, 0xc0}; + +/* Possible ABM 2.2 Max Reduction configs from least aggressive to most aggressive + * 0 1 2 3 4 5 6 7 8 9 10 11 12 + * 96.1 89.8 74.9 69.4 64.7 52.2 48.6 39.6 30.2 25.1 19.6 12.5 12.5 % + */ +static const unsigned char max_reduction_table_v_2_2[13] = { +0xf5, 0xe5, 0xbf, 0xb1, 0xa5, 0x85, 0x7c, 0x65, 0x4d, 0x40, 0x32, 0x20, 0x20}; + +/* Predefined ABM configuration sets. We may have different configuration sets + * in order to satisfy different power/quality requirements. + */ +static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_level] = { +/* ABM Level 1, ABM Level 2, ABM Level 3, ABM Level 4 */ +{ 2, 5, 7, 8 }, /* Default - Medium aggressiveness */ +{ 2, 5, 8, 11 }, /* Alt #1 - Increased aggressiveness */ +{ 0, 2, 4, 8 }, /* Alt #2 - Minimal aggressiveness */ +{ 3, 6, 10, 12 }, /* Alt #3 - Super aggressiveness */ +}; + +struct abm_parameters { + unsigned char min_reduction; + unsigned char max_reduction; + unsigned char bright_pos_gain; + unsigned char dark_pos_gain; + unsigned char brightness_gain; + unsigned char contrast_factor; + unsigned char deviation_gain; + unsigned char min_knee; + unsigned char max_knee; + unsigned short blRampReduction; + unsigned short blRampStart; +}; + +static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = { +// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart + {0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xe0, 0xf777, 0xcccc}, + {0xde, 0x85, 0x20, 0x00, 0xe0, 0x90, 0xa8, 0x40, 0xc8, 0xf777, 0xcccc}, + {0xb0, 0x50, 0x20, 0x00, 0xc0, 0x88, 0x78, 0x70, 0xa0, 0xeeee, 0x9999}, + {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xe333, 0xb333}, +}; + +static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = { +// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart + {0xf0, 0xd9, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, + {0xcd, 0xa5, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, + {0x99, 0x65, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, + {0x82, 0x4d, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, +}; + +static const struct abm_parameters abm_settings_config2[abm_defines_max_level] = { +// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart + {0xf0, 0xbf, 0x20, 0x00, 0x88, 0x99, 0xb3, 0x40, 0xe0, 0x0000, 0xcccc}, + {0xd8, 0x85, 0x20, 0x00, 0x70, 0x90, 0xa8, 0x40, 0xc8, 0x0700, 0xb333}, + {0xb8, 0x58, 0x20, 0x00, 0x64, 0x88, 0x78, 0x70, 0xa0, 0x7000, 0x9999}, + {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xc333, 0xb333}, +}; + +static const struct abm_parameters * const abm_settings[] = { + abm_settings_config0, + abm_settings_config1, + abm_settings_config2, +}; + +static const struct dm_bl_data_point custom_backlight_curve0[] = { + {2, 14}, {4, 16}, {6, 18}, {8, 21}, {10, 23}, {12, 26}, {14, 29}, {16, 32}, {18, 35}, + {20, 38}, {22, 41}, {24, 44}, {26, 48}, {28, 52}, {30, 55}, {32, 59}, {34, 62}, + {36, 67}, {38, 71}, {40, 75}, {42, 80}, {44, 84}, {46, 88}, {48, 93}, {50, 98}, + {52, 103}, {54, 108}, {56, 113}, {58, 118}, {60, 123}, {62, 129}, {64, 135}, {66, 140}, + {68, 146}, {70, 152}, {72, 158}, {74, 164}, {76, 171}, {78, 177}, {80, 183}, {82, 190}, + {84, 197}, {86, 204}, {88, 211}, {90, 218}, {92, 225}, {94, 232}, {96, 240}, {98, 247}}; + +struct custom_backlight_profile { + uint8_t ac_level_percentage; + uint8_t dc_level_percentage; + uint8_t min_input_signal; + uint8_t max_input_signal; + uint8_t num_data_points; + const struct dm_bl_data_point *data_points; +}; + +static const struct custom_backlight_profile custom_backlight_profiles[] = { + {100, 32, 12, 255, ARRAY_SIZE(custom_backlight_curve0), custom_backlight_curve0}, +}; + +#define NUM_AMBI_LEVEL 5 +#define NUM_AGGR_LEVEL 4 +#define NUM_POWER_FN_SEGS 8 +#define NUM_BL_CURVE_SEGS 16 +#define IRAM_SIZE 256 + +#define IRAM_RESERVE_AREA_START_V2 0xF0 // reserve 0xF0~0xF6 are write by DMCU only +#define IRAM_RESERVE_AREA_END_V2 0xF6 // reserve 0xF0~0xF6 are write by DMCU only + +#define IRAM_RESERVE_AREA_START_V2_2 0xF0 // reserve 0xF0~0xFF are write by DMCU only +#define IRAM_RESERVE_AREA_END_V2_2 0xFF // reserve 0xF0~0xFF are write by DMCU only + +#pragma pack(push, 1) +/* NOTE: iRAM is 256B in size */ +struct iram_table_v_2 { + /* flags */ + uint16_t min_abm_backlight; /* 0x00 U16 */ + + /* parameters for ABM2.0 algorithm */ + uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */ + uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */ + uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */ + uint8_t bright_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */ + uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x52 U2.6 */ + uint8_t dark_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x66 U2.6 */ + uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x7a U0.8 */ + uint8_t deviation_gain; /* 0x7f U0.8 */ + + /* parameters for crgb conversion */ + uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */ + uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */ + uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */ + + /* parameters for custom curve */ + /* thresholds for brightness --> backlight */ + uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */ + /* offsets for brightness --> backlight */ + uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */ + + /* For reading PSR State directly from IRAM */ + uint8_t psr_state; /* 0xf0 */ + uint8_t dmcu_mcp_interface_version; /* 0xf1 */ + uint8_t dmcu_abm_feature_version; /* 0xf2 */ + uint8_t dmcu_psr_feature_version; /* 0xf3 */ + uint16_t dmcu_version; /* 0xf4 */ + uint8_t dmcu_state; /* 0xf6 */ + + uint16_t blRampReduction; /* 0xf7 */ + uint16_t blRampStart; /* 0xf9 */ + uint8_t dummy5; /* 0xfb */ + uint8_t dummy6; /* 0xfc */ + uint8_t dummy7; /* 0xfd */ + uint8_t dummy8; /* 0xfe */ + uint8_t dummy9; /* 0xff */ +}; + +struct iram_table_v_2_2 { + /* flags */ + uint16_t flags; /* 0x00 U16 */ + + /* parameters for ABM2.2 algorithm */ + uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */ + uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */ + uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */ + uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */ + uint8_t hybrid_factor[NUM_AGGR_LEVEL]; /* 0x52 U0.8 */ + uint8_t contrast_factor[NUM_AGGR_LEVEL]; /* 0x56 U0.8 */ + uint8_t deviation_gain[NUM_AGGR_LEVEL]; /* 0x5a U0.8 */ + uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x5e U0.8 */ + uint8_t min_knee[NUM_AGGR_LEVEL]; /* 0x63 U0.8 */ + uint8_t max_knee[NUM_AGGR_LEVEL]; /* 0x67 U0.8 */ + uint16_t min_abm_backlight; /* 0x6b U16 */ + uint8_t pad[19]; /* 0x6d U0.8 */ + + /* parameters for crgb conversion */ + uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */ + uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */ + uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */ + + /* parameters for custom curve */ + /* thresholds for brightness --> backlight */ + uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */ + /* offsets for brightness --> backlight */ + uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */ + + /* For reading PSR State directly from IRAM */ + uint8_t psr_state; /* 0xf0 */ + uint8_t dmcu_mcp_interface_version; /* 0xf1 */ + uint8_t dmcu_abm_feature_version; /* 0xf2 */ + uint8_t dmcu_psr_feature_version; /* 0xf3 */ + uint16_t dmcu_version; /* 0xf4 */ + uint8_t dmcu_state; /* 0xf6 */ + + uint8_t dummy1; /* 0xf7 */ + uint8_t dummy2; /* 0xf8 */ + uint8_t dummy3; /* 0xf9 */ + uint8_t dummy4; /* 0xfa */ + uint8_t dummy5; /* 0xfb */ + uint8_t dummy6; /* 0xfc */ + uint8_t dummy7; /* 0xfd */ + uint8_t dummy8; /* 0xfe */ + uint8_t dummy9; /* 0xff */ +}; +#pragma pack(pop) + +#define MOD_POWER_MAX_CONCURRENT_STREAMS 32 +#define SMOOTH_BRIGHTNESS_ADJUSTMENT_TIME_IN_MS 500 + + + +struct backlight_state { + /* HW uses u16.16 format for backlight PWM */ + unsigned int backlight_pwm; + /* DM may call power module to set backlight + * targeting percent brightness + */ + unsigned int backlight_millipercent; + /* DM may call power module to set backlight based on an explicit + * nits value. + */ + unsigned int backlight_millinit; + unsigned int frame_ramp; + bool smooth_brightness_enabled; + bool isHDR; +}; +struct power_entity { + struct dc_stream_state *stream; + struct psr_caps *caps; + struct mod_power_psr_context *psr_context; + + /*PSR cached properties*/ + bool psr_enabled; + unsigned int psr_events; + unsigned int psr_power_opt; + unsigned int replay_events; +}; + +struct pwr_backlight_properties { + bool use_nits_based_brightness; + bool disable_fractional_pwm; + + unsigned int min_abm_backlight; + unsigned int num_backlight_levels; + + bool backlight_ramping_override; + unsigned int backlight_ramping_reduction; + unsigned int backlight_ramping_start; + + /* Backlight cached properties */ + unsigned int ac_backlight_percent; + unsigned int dc_backlight_percent; + + /* backlight LUT stored in HW u16.16 format*/ + unsigned int *backlight_lut; + unsigned int min_backlight_pwm; + unsigned int max_backlight_pwm; + unsigned int backlight_range; + + /* Describes the panel's min and max luminance in millinits measured + * on full white screen, in min and max backlight settings. + */ + unsigned int min_brightness_millinits; + unsigned int max_brightness_millinits; + unsigned int nits_range; + + bool backlight_caps_valid; + bool use_custom_backlight_caps; + unsigned int custom_backlight_caps_config_no; + bool use_linear_backlight_curve; +}; + +struct dmcu_varibright_cached_properties { + unsigned int varibright_config_setting; + unsigned int varibright_level; + unsigned int varibright_hw_level; + unsigned int def_varibright_level; + bool varibright_user_enable; + bool varibright_active; +}; + +struct core_power { + struct mod_power mod_public; + struct dc *dc; + struct power_entity *map; + struct dmcu_varibright_cached_properties varibright_prop; + struct pwr_backlight_properties bl_prop[MAX_NUM_EDP]; + struct backlight_state bl_state[MAX_NUM_EDP]; + unsigned int edp_num; + + bool psr_smu_optimizations_support; + bool multi_disp_optimizations_support; + + unsigned int num_entities; +}; + +union dmcu_abm_set_bl_params { + struct { + unsigned int gradual_change : 1; /* [0:0] */ + unsigned int reserved : 15; /* [15:1] */ + unsigned int frame_ramp : 16; /* [31:16] */ + } bits; + unsigned int u32All; +}; + +/* If system or panel does not report some sort of brightness percent to nits + * mapping, we will use following default values so backlight control using + * nits based interfaces will still work, but might not describe panel + * correctly. In this case percentage based backlight control should ideally + * be used. + * Min = 5 nits + * Max = 300 nits + */ + +#define MOD_POWER_TO_CORE(mod_power)\ + container_of(mod_power, struct core_power, mod_public) + + + +static uint16_t backlight_8_to_16(unsigned int backlight_8bit) +{ + return (uint16_t)(backlight_8bit * 0x101); +} + +unsigned int backlight_millipercent_to_millinit( + struct core_power *core_power, unsigned int millipercent, unsigned int inst) +{ + unsigned int millinit = 0; + unsigned long long numerator = 0; + + if (core_power == NULL) + return 0; + + numerator = ((unsigned long long)millipercent) * + core_power->bl_prop[inst].nits_range; + millinit = ((unsigned int)div_u64(numerator, 100000)) + + core_power->bl_prop[inst].min_brightness_millinits; + + return millinit; +} + +static unsigned int backlight_millinit_to_millipercent( + struct core_power *core_power, unsigned int millinit, unsigned int inst) +{ + unsigned int millipercent = 0; + unsigned long long numerator = 0; + + if (core_power == NULL) + return 0; + + if (millinit <= core_power->bl_prop[inst].min_brightness_millinits) + return 0; + + if (millinit >= core_power->bl_prop[inst].max_brightness_millinits) + return (100 * 1000); + + numerator = (((unsigned long long)millinit) - + core_power->bl_prop[inst].min_brightness_millinits) * 100000; + millipercent = ((unsigned int)div_u64(numerator, + core_power->bl_prop[inst].nits_range)); + + return millipercent; +} + +static unsigned int backlight_pwm_to_millipercent( + struct core_power *core_power, unsigned int pwm, unsigned int inst) +{ + unsigned int millipercent = 0; + unsigned int max_index = 0; + + if (core_power == NULL) + return 0; + + if (!core_power->bl_prop[inst].backlight_caps_valid) + return 0; + + /* Doesn't really make sense to have one single backlight level + * possible... + */ + if (core_power->bl_prop[inst].num_backlight_levels < 2) + return 0; + + max_index = core_power->bl_prop[inst].num_backlight_levels - 1; + + if (pwm <= core_power->bl_prop[inst].backlight_lut[0]) + return 0; + + if (pwm > core_power->bl_prop[inst].backlight_lut[max_index]) + return (100 * 1000); + + /* We need to do a binary search over the array for where the pwm level + * is in the lut. Based on the index we can determine percentage. + */ + unsigned int min = 0; + unsigned int max = max_index; + unsigned int mid = 0; + + while (max >= min) { + mid = (min + max) / 2; /* floor of half range */ + + if (core_power->bl_prop[inst].backlight_lut[mid] < pwm) + min = mid + 1; + else if (core_power->bl_prop[inst].backlight_lut[mid] > pwm) + max = mid - 1; + else + break; + } + + /* In this case, exact match is not found. Check if mid/min/max + * value is actually closer. + */ + if (max < min) { + unsigned int min_delta; + unsigned int mid_delta; + unsigned int max_delta; + + min_delta = (core_power->bl_prop[inst].backlight_lut[min] > pwm) ? + core_power->bl_prop[inst].backlight_lut[min] - pwm : + pwm - core_power->bl_prop[inst].backlight_lut[min]; + + mid_delta = (core_power->bl_prop[inst].backlight_lut[mid] > pwm) ? + core_power->bl_prop[inst].backlight_lut[mid] - pwm : + pwm - core_power->bl_prop[inst].backlight_lut[mid]; + + max_delta = (core_power->bl_prop[inst].backlight_lut[max] > pwm) ? + core_power->bl_prop[inst].backlight_lut[max] - pwm : + pwm - core_power->bl_prop[inst].backlight_lut[max]; + + if ((min_delta < mid_delta) && (min_delta < max_delta)) + mid = min; + + if ((max_delta < mid_delta) && (max_delta < min_delta)) + mid = max; + } + + /* No interpolation, just take closest index */ + millipercent = 1000 * 100 * mid / max_index; + + return millipercent; +} + +static unsigned int backlight_pwm_to_millinit( + struct core_power *core_power, unsigned int pwm, unsigned int inst) +{ + unsigned int millinit = 0; + + if (core_power == NULL) + return 0; + + if (pwm <= core_power->bl_prop[inst].min_backlight_pwm) + return core_power->bl_prop[inst].min_brightness_millinits; + + if (pwm >= core_power->bl_prop[inst].max_backlight_pwm) + return core_power->bl_prop[inst].max_brightness_millinits; + + millinit = ((unsigned int)div_u64(((unsigned long long)pwm - + core_power->bl_prop[inst].min_backlight_pwm) * + core_power->bl_prop[inst].nits_range, + core_power->bl_prop[inst].backlight_range)); + + millinit += core_power->bl_prop[inst].min_brightness_millinits; + + if (millinit > core_power->bl_prop[inst].max_brightness_millinits) + millinit = core_power->bl_prop[inst].max_brightness_millinits; + + return millinit; +} + +unsigned int backlight_millipercent_to_pwm( + struct core_power *core_power, unsigned int millipercent, unsigned int inst) +{ + unsigned int pwm = (unsigned int)-1; + unsigned int index = 0; + + if (core_power == NULL) + return 0; + + // Bypass the brightness mapping LUT + if (core_power->bl_prop->use_linear_backlight_curve) { + pwm = core_power->bl_prop[inst].min_backlight_pwm + + (unsigned int) div_u64((unsigned long long) millipercent * + core_power->bl_prop[inst].backlight_range, + 100000); + + if (pwm > core_power->bl_prop[inst].max_backlight_pwm) + pwm = core_power->bl_prop[inst].max_backlight_pwm; + + return pwm; + } + + if (millipercent >= (100 * 1000)) + return core_power->bl_prop[inst].backlight_lut[core_power->bl_prop[inst].num_backlight_levels - 1]; + + /* This will give the floor index. */ + index = ((core_power->bl_prop[inst].num_backlight_levels - 1) * + millipercent) / 100000; + /* Null check otherwise eDP doesn't lightup when connected to DP1 */ + if (core_power->bl_prop[inst].backlight_lut == NULL) + return pwm; + + pwm = core_power->bl_prop[inst].backlight_lut[index]; + + return pwm; +} + +static unsigned int backlight_millinit_to_pwm( + struct core_power *core_power, unsigned int millinit, unsigned int inst) +{ + unsigned int pwm = 0; + + if (core_power == NULL) + return 0; + + /* For nits based brightness, the signal will be a value + * between the minimum and maximum value. + */ + if (millinit >= core_power->bl_prop[inst].max_brightness_millinits) + return core_power->bl_prop[inst].max_backlight_pwm; + else if (millinit <= core_power->bl_prop[inst].min_brightness_millinits) + return core_power->bl_prop[inst].min_backlight_pwm; + + pwm = ((unsigned int)div_u64(((unsigned long long)millinit - + core_power->bl_prop[inst].min_brightness_millinits) * + core_power->bl_prop[inst].backlight_range, + core_power->bl_prop[inst].nits_range)); + + pwm += core_power->bl_prop[inst].min_backlight_pwm; + + if (pwm > core_power->bl_prop[inst].max_backlight_pwm) + pwm = core_power->bl_prop[inst].max_backlight_pwm; + + return pwm; +} + +static bool validate_ext_backlight_caps( + struct dm_acpi_atif_backlight_caps *ext_backlight_caps) +{ + unsigned int i; + unsigned int num_of_data_points = 0; + unsigned int last_signal_level = 0; + unsigned int last_luminance = 0; + + num_of_data_points = ext_backlight_caps->num_data_points; + + /* Validation rules: + * 1. BIOS should carry customized data points and + * the number of data points should not be larger than 99. + * 2. The max_input_signal should be larger than min_input_signal. + * 3. For each data point: + * a. luminance should be in ascending order and + * should not be 0 or 100 since the corresponding signal_level + * are assigned by min_input_signal and max_input_signal. + * b. signal_level should be in ascending order and + * be within the range of min/max_input_signal. + */ + if (num_of_data_points > BL_DATA_POINTS) + return false; + + if (ext_backlight_caps->min_input_signal >= ext_backlight_caps->max_input_signal) + return false; + + last_signal_level = ext_backlight_caps->min_input_signal; + for (i = 0; i < num_of_data_points; i++) { + unsigned int luminance = ext_backlight_caps->data_points[i].luminance; + unsigned int signal_level = ext_backlight_caps->data_points[i].signal_level; + + if ((luminance <= last_luminance) || (luminance > BL_DATA_POINTS)) + return false; + + if ((signal_level <= last_signal_level) || (signal_level >= ext_backlight_caps->max_input_signal)) + return false; + + last_signal_level = signal_level; + last_luminance = luminance; + } + + return true; +} + +/* hard coded to default backlight curve. */ +void initialize_backlight_caps(struct core_power *core_power, unsigned int inst) +{ + unsigned int i; + struct dm_acpi_atif_backlight_caps *ext_backlight_caps = NULL; + bool custom_curve_present = false; + unsigned int num_levels = 0; + struct dc *dc = NULL; + enum dm_acpi_display_type acpi_display_type = + (inst == 0) ? AcpiDisplayType_LCD1 : AcpiDisplayType_LCD2; + + if (core_power == NULL) + return; + dc = core_power->dc; + + num_levels = core_power->bl_prop[inst].num_backlight_levels; + + /* Allocate memory for ATIF output + * (do not want to use 256 bytes on the stack) + */ + ext_backlight_caps = (struct dm_acpi_atif_backlight_caps *) + (kzalloc(sizeof(struct dm_acpi_atif_backlight_caps), + GFP_KERNEL)); + + if (ext_backlight_caps == NULL) + return; + + /* Retrieve ACPI extended brightness caps */ + if (dm_query_extended_brightness_caps + (dc->ctx, acpi_display_type, ext_backlight_caps)) { + custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps); + } + + if (core_power->bl_prop[inst].use_custom_backlight_caps && + fill_custom_backlight_caps( + core_power->bl_prop[inst].custom_backlight_caps_config_no, + ext_backlight_caps)) { + custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps); + } + + if (custom_curve_present) { + unsigned int index = 1; + unsigned int num_of_data_points = ext_backlight_caps->num_data_points; + + core_power->bl_prop[inst].ac_backlight_percent = + ext_backlight_caps->ac_level_percentage; + core_power->bl_prop[inst].dc_backlight_percent = + ext_backlight_caps->dc_level_percentage; + core_power->bl_prop[inst].backlight_lut[0] = + backlight_8_to_16( + ext_backlight_caps->min_input_signal); + core_power->bl_prop[inst].backlight_lut[num_levels - 1] = + backlight_8_to_16( + ext_backlight_caps->max_input_signal); + + /* Filling translation table from data points - + * between every two provided data points we + * lineary interpolate missing values + */ + for (i = 0; i < num_of_data_points; i++) { + unsigned int luminance = + ext_backlight_caps->data_points[i].luminance; + unsigned int signal_level = + backlight_8_to_16( + ext_backlight_caps->data_points[i].signal_level); + + /* Since luminance is a percentage, scale it by num_levels*/ + luminance = (luminance * num_levels) / 101; + + /* Lineary interpolate missing values */ + if (index < luminance) { + unsigned int base_value = + core_power->bl_prop[inst].backlight_lut[index-1]; + unsigned int delta_signal = + signal_level - base_value; + unsigned int delta_luma = + luminance - index + 1; + unsigned int step = delta_signal; + + for (; index < luminance; index++) { + core_power->bl_prop[inst].backlight_lut[index] = + base_value + (step / delta_luma); + step += delta_signal; + } + } + + /* Now [index == luminance], + * so we can add data point to the translation table + */ + core_power->bl_prop[inst].backlight_lut[index++] = signal_level; + } + + /* Complete the final segment of interpolation - + * between last datapoint and maximum value + */ + if (index < num_levels - 1) { + unsigned int base_value = + core_power->bl_prop[inst].backlight_lut[index-1]; + unsigned int delta_signal = + core_power->bl_prop[inst].backlight_lut[num_levels - 1] - + base_value; + unsigned int delta_luma = num_levels - index; + unsigned int step = delta_signal; + + for (; index < num_levels - 1; index++) { + core_power->bl_prop[inst].backlight_lut[index] = + base_value + (step / delta_luma); + step += delta_signal; + } + } + /* Build backlight translation table based on default curve */ + } else { + /* Defines default backlight curve F(x) = A(x*x) + Bx + C. + * + * Backlight curve should always satisfy: + * F(0) = min, F(100) = max, + * So polynom coefficients are: + * A is 0.0255 - B/100 - min/10000 - (255-max)/10000 = + * (max - min)/10000 - B/100 + * B is adjustable factor to modify the curve. + * Bigger B results in less concave curve. + * B range is [0..(max-min)/100] + * C is backlight minimum + */ + unsigned int backlight_curve_coeff_a_factor = + num_levels * num_levels; + unsigned int backlight_curve_coeff_b = num_levels; + unsigned int delta = + core_power->bl_prop[inst].backlight_lut[num_levels - 1] - + core_power->bl_prop[inst].backlight_lut[0]; + unsigned int coeffC = core_power->bl_prop[inst].backlight_lut[0]; + unsigned int coeffB = + (backlight_curve_coeff_b < delta ? + backlight_curve_coeff_b : delta); + unsigned long long coeffA = delta - coeffB; /* coeffB is B*100 */ + + for (i = 1; i < num_levels - 1; i++) { + uint64_t lut_val = div_u64(coeffA * i * i, backlight_curve_coeff_a_factor) + + div_u64((uint64_t)coeffB * i, backlight_curve_coeff_b) + coeffC; + + ASSERT(lut_val <= 0xFFFFFFFF); + core_power->bl_prop[inst].backlight_lut[i] = (unsigned int)lut_val; + } + } + + if (ext_backlight_caps != NULL) + kfree(ext_backlight_caps); + + /* Successfully initialized */ + core_power->bl_prop[inst].backlight_caps_valid = true; +} + +static void varibright_set_level(struct core_power *core_power) +{ + if (!core_power->varibright_prop.varibright_active || + !core_power->varibright_prop.varibright_user_enable) + core_power->varibright_prop.varibright_hw_level = 0; + else + core_power->varibright_prop.varibright_hw_level = + core_power->varibright_prop.varibright_level; +} + +bool mod_power_hw_init_backlight(struct mod_power *mod_power) +{ + struct core_power *core_power = NULL; + struct dc *dc = NULL; + struct dmcu *dmcu = NULL; + struct dmcu_iram_parameters params; + unsigned int i; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + dc = core_power->dc; + + for (i = 0; i < core_power->edp_num; i++) { + params.set = core_power->varibright_prop.varibright_config_setting; + params.backlight_ramping_override = core_power->bl_prop[i].backlight_ramping_override; + params.backlight_ramping_reduction = core_power->bl_prop[i].backlight_ramping_reduction; + params.backlight_ramping_start = core_power->bl_prop[i].backlight_ramping_start; + params.backlight_lut_array = core_power->bl_prop[i].backlight_lut; + params.backlight_lut_array_size = core_power->bl_prop[i].num_backlight_levels; + params.min_abm_backlight = core_power->bl_prop[i].min_abm_backlight; + + dmcu = dc->res_pool->dmcu; + + // In the case where abm is implemented on dmcub, + // dmcu object will be null. + // ABM 2.4 and up are implemented on dmcub. + if (dmcu) { + //DMCU does not support multiple eDP + return dmcu_load_iram(dmcu, params); + } else if (dc->ctx->dmub_srv) { + if (!dmub_init_abm_config(dc->res_pool, params, i)) + return false; + } else + return false; + } + return true; +} + +void mod_power_update_backlight_on_mode_change( + struct core_power *core_power, + struct dc_link *link, + unsigned int panel_inst, + uint8_t aux_inst, + bool is_hdr) +{ + struct set_backlight_level_params backlight_level_params = { 0 }; + + if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || + link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) + dc_link_set_backlight_level_nits(link, core_power->bl_state[panel_inst].isHDR, + core_power->bl_state[panel_inst].backlight_millinit, 0); + + backlight_level_params.frame_ramp = 0; + + fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst, + core_power->bl_state[panel_inst].backlight_pwm, link->backlight_control_type, + core_power->bl_state[panel_inst].backlight_millinit, 0, is_hdr); + + dc_link_set_backlight_level(link, &backlight_level_params); +} + +static bool set_backlight_millinits_aux(struct core_power *core_power, + struct dc_stream_state *stream, + unsigned int backlight_millinits, + unsigned int transition_time_millisec, + unsigned int inst) +{ + struct dc_link *link = NULL; + + if (core_power == NULL) + return false; + + if (stream == NULL) + return true; + + link = dc_stream_get_link(stream); + + return dc_link_set_backlight_level_nits(link, core_power->bl_state[inst].isHDR, + backlight_millinits, transition_time_millisec); +} + +static bool set_backlight(struct core_power *core_power, + struct dc_stream_state *stream, + struct set_backlight_level_params *backlight_level_params, + unsigned int inst) +{ + bool retv = false; + unsigned int frame_ramp = 0; + unsigned int vsync_rate_hz; + union dmcu_abm_set_bl_params params; + const struct dc_link *link = NULL; + unsigned int backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16; + unsigned int transition_time_millisec = backlight_level_params->transition_time_in_ms; + + if (core_power == NULL) + return false; + + core_power->bl_state[inst].backlight_pwm = backlight_pwm_u16_16; + + if (stream == NULL) + return true; + + if (stream->link->connector_signal != SIGNAL_TYPE_EDP) + return false; + + if (transition_time_millisec != 0) { + unsigned int v_total = + (stream->adjust.v_total_max == 0) ? stream->timing.v_total : stream->adjust.v_total_max; + + vsync_rate_hz = (unsigned int)div_u64(div_u64((stream-> + timing.pix_clk_100hz * 100), + v_total), + stream->timing.h_total); + + if (core_power->bl_state[inst].smooth_brightness_enabled) + frame_ramp = ((vsync_rate_hz * + transition_time_millisec) + 500) / 1000; + } + + core_power->bl_state[inst].frame_ramp = frame_ramp; + params.u32All = 0; + params.bits.gradual_change = (frame_ramp > 0); + params.bits.frame_ramp = frame_ramp; + link = dc_stream_get_link(stream); + + mod_power_set_psr_event(&core_power->mod_public, stream, true, psr_event_hw_programming, true); + mod_power_set_replay_event(&core_power->mod_public, stream, true, replay_event_hw_programming, true); + + backlight_level_params->frame_ramp = params.u32All; + retv = dc_link_set_backlight_level(link, backlight_level_params); + + mod_power_set_psr_event(&core_power->mod_public, stream, false, psr_event_hw_programming, false); + mod_power_set_replay_event(&core_power->mod_public, stream, false, replay_event_hw_programming, false); + + return retv; +} + +void fill_backlight_level_params(struct core_power *core_power, + struct set_backlight_level_params *backlight_level_params, + int panel_inst, uint8_t aux_inst, unsigned int backlight_pwm, + enum backlight_control_type backlight_control_type, + unsigned int backlight_millinit, unsigned int transition_time_millisec, + bool is_hdr) +{ + struct pwr_backlight_properties *bl_prop = &core_power->bl_prop[panel_inst]; + + backlight_level_params->aux_inst = aux_inst; + backlight_level_params->backlight_pwm_u16_16 = backlight_pwm; + backlight_level_params->control_type = backlight_control_type; + backlight_level_params->backlight_millinits = backlight_millinit; + backlight_level_params->transition_time_in_ms = transition_time_millisec; + backlight_level_params->min_luminance = bl_prop->min_brightness_millinits; + backlight_level_params->max_luminance = bl_prop->max_brightness_millinits; + backlight_level_params->min_backlight_pwm = bl_prop->min_backlight_pwm; + backlight_level_params->max_backlight_pwm = bl_prop->max_backlight_pwm; + + if (backlight_control_type == BACKLIGHT_CONTROL_AMD_AUX && !is_hdr) + backlight_level_params->control_type = BACKLIGHT_CONTROL_PWM; +} + +bool mod_power_set_backlight_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit, + unsigned int transition_time_millisec, + bool skip_aux, + bool is_hdr) +{ + struct core_power *core_power = NULL; + unsigned int backlight_pwm; + unsigned int panel_inst = 0; + struct set_backlight_level_params backlight_level_params = { 0 }; + const struct dc_link *link = NULL; + uint8_t aux_inst = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + link = dc_stream_get_link(stream); + + ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF); + aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel; + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst)) + return false; + + if (!skip_aux) { + if (!set_backlight_millinits_aux(core_power, stream, + backlight_millinit, transition_time_millisec, panel_inst)) + return false; + } +// always send both AUX (above) and PWM (below) + core_power->bl_state[panel_inst].backlight_millinit = backlight_millinit; + + core_power->bl_state[panel_inst].backlight_millipercent = + backlight_millinit_to_millipercent( + core_power, backlight_millinit, panel_inst); + + backlight_pwm = backlight_millinit_to_pwm( + core_power, backlight_millinit, panel_inst); + + fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst, backlight_pwm, + link->backlight_control_type, backlight_millinit, transition_time_millisec, is_hdr); + + return set_backlight(core_power, stream, + &backlight_level_params, panel_inst); +} + +bool mod_power_backlight_percent_to_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent, + unsigned int *backlight_millinit) +{ + struct core_power *core_power = NULL; + unsigned int inst = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) + return false; + + *backlight_millinit = backlight_millipercent_to_millinit( + core_power, backlight_millipercent, inst); + return true; +} + +bool mod_power_backlight_nits_to_percent(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit, + unsigned int *backlight_millipercent) +{ + struct core_power *core_power = NULL; + unsigned int inst = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) + return false; + + *backlight_millipercent = backlight_millinit_to_millipercent( + core_power, backlight_millinit, inst); + return true; +} + +bool mod_power_set_backlight_percent(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent, + unsigned int transition_time_millisec, + bool is_hdr) +{ + struct core_power *core_power = NULL; + struct set_backlight_level_params backlight_level_params = { 0 }; + const struct dc_link *link = NULL; + unsigned int backlight_pwm; + unsigned int panel_inst = 0; + uint8_t aux_inst = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + link = dc_stream_get_link(stream); + ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF); + aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel; + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst)) + return false; + core_power->bl_state[panel_inst].backlight_millipercent = backlight_millipercent; + + core_power->bl_state[panel_inst].backlight_millinit = + backlight_millipercent_to_millinit( + core_power, backlight_millipercent, panel_inst); + + backlight_pwm = backlight_millipercent_to_pwm( + core_power, backlight_millipercent, panel_inst); + + fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, + aux_inst, backlight_pwm, link->backlight_control_type, + core_power->bl_state[panel_inst].backlight_millinit, transition_time_millisec, is_hdr); + + return set_backlight(core_power, stream, + &backlight_level_params, panel_inst); +} + +void mod_power_update_backlight(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millipercent) +{ + struct core_power *core_power = NULL; + unsigned int inst = 0; + + if (mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) + return; + core_power->bl_state[inst].backlight_millipercent = backlight_millipercent; + + core_power->bl_state[inst].backlight_millinit = + backlight_millipercent_to_millinit( + core_power, backlight_millipercent, inst); + + core_power->bl_state[inst].backlight_pwm = backlight_millipercent_to_pwm( + core_power, backlight_millipercent, inst); +} + +void mod_power_update_backlight_nits(struct mod_power *mod_power, + struct dc_stream_state *stream, + unsigned int backlight_millinit) +{ + struct core_power *core_power = NULL; + unsigned int inst = 0; + + if (mod_power == NULL) + return; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst)) + return; + + core_power->bl_state[inst].backlight_millinit = backlight_millinit; + + core_power->bl_state[inst].backlight_millipercent = backlight_millinit_to_millipercent( + core_power, backlight_millinit, inst); + core_power->bl_state[inst].backlight_pwm = backlight_millinit_to_pwm( + core_power, backlight_millinit, inst); +} + +bool mod_power_get_backlight_pwm(struct mod_power *mod_power, + unsigned int *backlight_pwm, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *backlight_pwm = core_power->bl_state[inst].backlight_pwm; + + return true; +} + +bool mod_power_get_backlight_nits(struct mod_power *mod_power, + unsigned int *backlight_millinit, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *backlight_millinit = core_power->bl_state[inst].backlight_millinit; + + return true; +} + +bool mod_power_get_backlight_percent(struct mod_power *mod_power, + unsigned int *backlight_millipercent, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *backlight_millipercent = core_power->bl_state[inst].backlight_millipercent; + + return true; +} + +bool mod_power_get_hw_target_backlight_pwm_nits(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millinit, + unsigned int inst) +{ + struct core_power *core_power = NULL; + unsigned int backlight_u16_16 = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (mod_power_get_hw_target_backlight_pwm(mod_power, link, + &backlight_u16_16)) { + *backlight_millinit = + backlight_pwm_to_millinit(core_power, + backlight_u16_16, inst); + return true; + } + return false; +} + +bool mod_power_get_hw_target_backlight_pwm_percent(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millipercent, + unsigned int inst) +{ + struct core_power *core_power = NULL; + unsigned int backlight_u16_16 = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (mod_power_get_hw_target_backlight_pwm(mod_power, link, + &backlight_u16_16)) { + *backlight_millipercent = + backlight_pwm_to_millipercent(core_power, + backlight_u16_16, inst); + return true; + } + return false; +} + +bool mod_power_get_hw_target_backlight_pwm(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_u16_16) +{ + if (mod_power == NULL) + return false; + + *backlight_u16_16 = dc_link_get_target_backlight_pwm(link); + + return true; +} + +bool mod_power_get_hw_backlight_pwm_nits(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millinit, + unsigned int inst) +{ + struct core_power *core_power = NULL; + unsigned int backlight_u16_16 = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) { + *backlight_millinit = + backlight_pwm_to_millinit(core_power, + backlight_u16_16, inst); + return true; + } + return false; +} + +bool mod_power_get_hw_backlight_aux_nits(struct mod_power *mod_power, + struct dc_stream_state **streams, int num_streams, + unsigned int *backlight_millinit_avg, + unsigned int *backlight_millinit_peak) +{ + struct core_power *core_power = NULL; + struct dc_link *link = NULL; + int stream_index; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (core_power == NULL) + return false; + + if (num_streams < 1) + return true; + + for (stream_index = 0; stream_index < num_streams; stream_index++) + if (streams[stream_index]->link->connector_signal == SIGNAL_TYPE_EDP || + streams[stream_index]->link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) + break; + + if (stream_index == num_streams) + return false; + + link = dc_stream_get_link(streams[stream_index]); + if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 0) + return false; + + return dc_link_get_backlight_level_nits(link, backlight_millinit_avg, + backlight_millinit_peak); +} + +bool mod_power_get_hw_backlight_pwm_percent(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_millipercent, + unsigned int inst) +{ + struct core_power *core_power = NULL; + unsigned int backlight_u16_16 = 0; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) { + *backlight_millipercent = + backlight_pwm_to_millipercent(core_power, + backlight_u16_16, inst); + return true; + } + return false; +} + +bool mod_power_get_hw_backlight_pwm(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int *backlight_u16_16) +{ + if (mod_power == NULL) + return false; + + *backlight_u16_16 = dc_link_get_backlight_level(link); + + return true; +} + +bool mod_power_get_panel_backlight_boundaries( + struct mod_power *mod_power, + unsigned int *out_min_backlight, + unsigned int *out_max_backlight, + unsigned int *out_ac_backlight_percent, + unsigned int *out_dc_backlight_percent, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + /* If cache was successfully updated, + * copy the values to output structure and return success + */ + if (core_power->bl_prop[inst].backlight_caps_valid) { + *out_min_backlight = core_power->bl_prop[inst].backlight_lut[0]; + *out_max_backlight = + core_power->bl_prop[inst].backlight_lut[ + core_power->bl_prop[inst].num_backlight_levels - 1]; + *out_ac_backlight_percent = + core_power->bl_prop[inst].ac_backlight_percent; + *out_dc_backlight_percent = + core_power->bl_prop[inst].dc_backlight_percent; + + return true; + } + + return false; +} + +bool mod_power_set_smooth_brightness(struct mod_power *mod_power, + bool enable_brightness, + unsigned int inst) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + core_power->bl_state[inst].smooth_brightness_enabled = enable_brightness; + + return true; +} + +bool mod_power_varibright_feature_enable(struct mod_power *mod_power, bool enable, + struct dc_stream_update *stream_update) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + core_power->varibright_prop.varibright_user_enable = enable; + + /* find abm hw level to program, and save in stream update */ + varibright_set_level(core_power); + *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">ABM feature enable: enable=%u su->varibright_level=%u varibright_hw_level=%u", + (unsigned int) enable, + *stream_update->abm_level, + core_power->varibright_prop.varibright_hw_level); + return true; +} + +bool mod_power_varibright_activate(struct mod_power *mod_power, + bool activate, + struct dc_stream_update *stream_update) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + core_power->varibright_prop.varibright_active = activate; + + /* find abm hw level to program, and save in stream update */ + varibright_set_level(core_power); + *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">ABM activate: activate=%u su->varibright_level=%u", + (unsigned int) activate, + *stream_update->abm_level); + return true; +} +bool mod_power_varibright_set_level(struct mod_power *mod_power, unsigned int level, + struct dc_stream_update *stream_update) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + core_power->varibright_prop.varibright_level = level; + core_power->varibright_prop.varibright_hw_level = level; + + /* find abm hw level to program, and save in stream update */ + varibright_set_level(core_power); + *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u", + level, + core_power->varibright_prop.varibright_level, + core_power->varibright_prop.varibright_hw_level, + *stream_update->abm_level); + return true; +} + +bool mod_power_varibright_set_hw_level(struct mod_power *mod_power, unsigned int level, + struct dc_stream_update *stream_update) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + if (level == 0 || level == ABM_LEVEL_IMMEDIATE_DISABLE) + core_power->varibright_prop.varibright_active = 0; + else + core_power->varibright_prop.varibright_active = 1; + core_power->varibright_prop.varibright_hw_level = level; + *stream_update->abm_level = core_power->varibright_prop.varibright_hw_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u", + level, + core_power->varibright_prop.varibright_level, + core_power->varibright_prop.varibright_hw_level, + *stream_update->abm_level); + return true; +} + +bool mod_power_get_varibright_level(struct mod_power *mod_power, + unsigned int *varibright_level) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *varibright_level = core_power->varibright_prop.varibright_level; + + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get varibright level: cp->varibright_level=%u", + *varibright_level); + return true; + +} + +bool mod_power_get_varibright_hw_level(struct mod_power *mod_power, + unsigned int *varibright_level) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *varibright_level = core_power->varibright_prop.varibright_hw_level; + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get varibright HW level: hw_level=%u", + *varibright_level); + return true; +} + +bool mod_power_get_varibright_default_level(struct mod_power *mod_power, + unsigned int *varibright_level) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *varibright_level = core_power->varibright_prop.def_varibright_level; + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get varibright default level: def_varibright_level=%u", + *varibright_level); + return true; +} + +bool mod_power_get_varibright_enable(struct mod_power *mod_power, + bool *varibright_enable) +{ + struct core_power *core_power = NULL; + + if (mod_power == NULL) + return false; + + core_power = MOD_POWER_TO_CORE(mod_power); + + *varibright_enable = core_power->varibright_prop.varibright_user_enable; + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get varibright enable state: varibright_user_enable=%u", + (unsigned int) (*varibright_enable)); + return true; +} + +bool mod_power_is_abm_active(struct mod_power *mod_power, + const struct dc_link *link, + unsigned int inst) +{ + unsigned int user_backlight = 0; + unsigned int current_backlight = 0; + bool is_active = false; + + if (mod_power == NULL) + return false; + + mod_power_get_backlight_pwm(mod_power, &user_backlight, inst); + mod_power_get_hw_backlight_pwm(mod_power, link, ¤t_backlight); + + if (user_backlight != current_backlight) + is_active = true; + else + is_active = false; + DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION, + WPP_BIT_FLAG_Backlight_ABM, + ">get ABM active state: is_active=%u (user_backlight_pwm=%u, current_backlight_pwm=%u)", + (unsigned int)is_active, + user_backlight, + current_backlight); + return is_active; +} + +static void fill_backlight_transform_table(struct dmcu_iram_parameters params, + struct iram_table_v_2 *table) +{ + unsigned int i; + unsigned int num_entries = NUM_BL_CURVE_SEGS; + unsigned int lut_index; + + table->backlight_thresholds[0] = 0; + ASSERT(params.backlight_lut_array[0] <= 0xFFFF); + table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0]; + table->backlight_thresholds[num_entries-1] = 0xFFFF; + ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF); + table->backlight_offsets[num_entries-1] = + (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1]; + + /* Setup all brightness levels between 0% and 100% exclusive + * Fills brightness-to-backlight transform table. Backlight custom curve + * describes transform from brightness to backlight. It will be defined + * as set of thresholds and set of offsets, together, implying + * extrapolation of custom curve into 16 uniformly spanned linear + * segments. Each threshold/offset represented by 16 bit entry in + * format U4.10. + */ + for (i = 1; i+1 < num_entries; i++) { + lut_index = (params.backlight_lut_array_size - 1) * i / (num_entries - 1); + + ASSERT(lut_index < params.backlight_lut_array_size); + + unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries); + unsigned int offset_val = params.backlight_lut_array[lut_index]; + + ASSERT(threshold_val <= 0xFFFF); + ASSERT(offset_val <= 0xFFFF); + + table->backlight_thresholds[i] = cpu_to_be16((uint16_t)threshold_val); + table->backlight_offsets[i] = cpu_to_be16((uint16_t)offset_val); + } +} + +static void fill_backlight_transform_table_v_2_2(struct dmcu_iram_parameters params, + struct iram_table_v_2_2 *table, bool big_endian) +{ + unsigned int i; + unsigned int num_entries = NUM_BL_CURVE_SEGS; + unsigned int lut_index; + + table->backlight_thresholds[0] = 0; + ASSERT(params.backlight_lut_array[0] <= 0xFFFF); + table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0]; + table->backlight_thresholds[num_entries-1] = 0xFFFF; + ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF); + table->backlight_offsets[num_entries-1] = + (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1]; + + /* Setup all brightness levels between 0% and 100% exclusive + * Fills brightness-to-backlight transform table. Backlight custom curve + * describes transform from brightness to backlight. It will be defined + * as set of thresholds and set of offsets, together, implying + * extrapolation of custom curve into 16 uniformly spanned linear + * segments. Each threshold/offset represented by 16 bit entry in + * format U4.10. + */ + for (i = 1; i+1 < num_entries; i++) { + lut_index = DIV_ROUNDUP((i * params.backlight_lut_array_size), num_entries); + ASSERT(lut_index < params.backlight_lut_array_size); + + unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries); + unsigned int offset_val = params.backlight_lut_array[lut_index]; + + ASSERT(threshold_val <= 0xFFFF); + ASSERT(offset_val <= 0xFFFF); + + table->backlight_thresholds[i] = (big_endian) ? + cpu_to_be16((uint16_t)threshold_val) : cpu_to_le16((uint16_t)threshold_val); + table->backlight_offsets[i] = (big_endian) ? + cpu_to_be16((uint16_t)offset_val) : cpu_to_le16((uint16_t)offset_val); + } +} + +static void fill_iram_v_2(struct iram_table_v_2 *ram_table, struct dmcu_iram_parameters params) +{ + unsigned int set = params.set; + + ram_table->min_abm_backlight = + cpu_to_be16(params.min_abm_backlight); + ram_table->deviation_gain = 0xb3; + + ram_table->blRampReduction = + cpu_to_be16(params.backlight_ramping_reduction); + ram_table->blRampStart = + cpu_to_be16(params.backlight_ramping_start); + + ram_table->min_reduction[0][0] = min_reduction_table[abm_config[set][0]]; + ram_table->min_reduction[1][0] = min_reduction_table[abm_config[set][0]]; + ram_table->min_reduction[2][0] = min_reduction_table[abm_config[set][0]]; + ram_table->min_reduction[3][0] = min_reduction_table[abm_config[set][0]]; + ram_table->min_reduction[4][0] = min_reduction_table[abm_config[set][0]]; + ram_table->max_reduction[0][0] = max_reduction_table[abm_config[set][0]]; + ram_table->max_reduction[1][0] = max_reduction_table[abm_config[set][0]]; + ram_table->max_reduction[2][0] = max_reduction_table[abm_config[set][0]]; + ram_table->max_reduction[3][0] = max_reduction_table[abm_config[set][0]]; + ram_table->max_reduction[4][0] = max_reduction_table[abm_config[set][0]]; + + ram_table->min_reduction[0][1] = min_reduction_table[abm_config[set][1]]; + ram_table->min_reduction[1][1] = min_reduction_table[abm_config[set][1]]; + ram_table->min_reduction[2][1] = min_reduction_table[abm_config[set][1]]; + ram_table->min_reduction[3][1] = min_reduction_table[abm_config[set][1]]; + ram_table->min_reduction[4][1] = min_reduction_table[abm_config[set][1]]; + ram_table->max_reduction[0][1] = max_reduction_table[abm_config[set][1]]; + ram_table->max_reduction[1][1] = max_reduction_table[abm_config[set][1]]; + ram_table->max_reduction[2][1] = max_reduction_table[abm_config[set][1]]; + ram_table->max_reduction[3][1] = max_reduction_table[abm_config[set][1]]; + ram_table->max_reduction[4][1] = max_reduction_table[abm_config[set][1]]; + + ram_table->min_reduction[0][2] = min_reduction_table[abm_config[set][2]]; + ram_table->min_reduction[1][2] = min_reduction_table[abm_config[set][2]]; + ram_table->min_reduction[2][2] = min_reduction_table[abm_config[set][2]]; + ram_table->min_reduction[3][2] = min_reduction_table[abm_config[set][2]]; + ram_table->min_reduction[4][2] = min_reduction_table[abm_config[set][2]]; + ram_table->max_reduction[0][2] = max_reduction_table[abm_config[set][2]]; + ram_table->max_reduction[1][2] = max_reduction_table[abm_config[set][2]]; + ram_table->max_reduction[2][2] = max_reduction_table[abm_config[set][2]]; + ram_table->max_reduction[3][2] = max_reduction_table[abm_config[set][2]]; + ram_table->max_reduction[4][2] = max_reduction_table[abm_config[set][2]]; + + ram_table->min_reduction[0][3] = min_reduction_table[abm_config[set][3]]; + ram_table->min_reduction[1][3] = min_reduction_table[abm_config[set][3]]; + ram_table->min_reduction[2][3] = min_reduction_table[abm_config[set][3]]; + ram_table->min_reduction[3][3] = min_reduction_table[abm_config[set][3]]; + ram_table->min_reduction[4][3] = min_reduction_table[abm_config[set][3]]; + ram_table->max_reduction[0][3] = max_reduction_table[abm_config[set][3]]; + ram_table->max_reduction[1][3] = max_reduction_table[abm_config[set][3]]; + ram_table->max_reduction[2][3] = max_reduction_table[abm_config[set][3]]; + ram_table->max_reduction[3][3] = max_reduction_table[abm_config[set][3]]; + ram_table->max_reduction[4][3] = max_reduction_table[abm_config[set][3]]; + + ram_table->bright_pos_gain[0][0] = 0x20; + ram_table->bright_pos_gain[0][1] = 0x20; + ram_table->bright_pos_gain[0][2] = 0x20; + ram_table->bright_pos_gain[0][3] = 0x20; + ram_table->bright_pos_gain[1][0] = 0x20; + ram_table->bright_pos_gain[1][1] = 0x20; + ram_table->bright_pos_gain[1][2] = 0x20; + ram_table->bright_pos_gain[1][3] = 0x20; + ram_table->bright_pos_gain[2][0] = 0x20; + ram_table->bright_pos_gain[2][1] = 0x20; + ram_table->bright_pos_gain[2][2] = 0x20; + ram_table->bright_pos_gain[2][3] = 0x20; + ram_table->bright_pos_gain[3][0] = 0x20; + ram_table->bright_pos_gain[3][1] = 0x20; + ram_table->bright_pos_gain[3][2] = 0x20; + ram_table->bright_pos_gain[3][3] = 0x20; + ram_table->bright_pos_gain[4][0] = 0x20; + ram_table->bright_pos_gain[4][1] = 0x20; + ram_table->bright_pos_gain[4][2] = 0x20; + ram_table->bright_pos_gain[4][3] = 0x20; + ram_table->bright_neg_gain[0][0] = 0x00; + ram_table->bright_neg_gain[0][1] = 0x00; + ram_table->bright_neg_gain[0][2] = 0x00; + ram_table->bright_neg_gain[0][3] = 0x00; + ram_table->bright_neg_gain[1][0] = 0x00; + ram_table->bright_neg_gain[1][1] = 0x00; + ram_table->bright_neg_gain[1][2] = 0x00; + ram_table->bright_neg_gain[1][3] = 0x00; + ram_table->bright_neg_gain[2][0] = 0x00; + ram_table->bright_neg_gain[2][1] = 0x00; + ram_table->bright_neg_gain[2][2] = 0x00; + ram_table->bright_neg_gain[2][3] = 0x00; + ram_table->bright_neg_gain[3][0] = 0x00; + ram_table->bright_neg_gain[3][1] = 0x00; + ram_table->bright_neg_gain[3][2] = 0x00; + ram_table->bright_neg_gain[3][3] = 0x00; + ram_table->bright_neg_gain[4][0] = 0x00; + ram_table->bright_neg_gain[4][1] = 0x00; + ram_table->bright_neg_gain[4][2] = 0x00; + ram_table->bright_neg_gain[4][3] = 0x00; + ram_table->dark_pos_gain[0][0] = 0x00; + ram_table->dark_pos_gain[0][1] = 0x00; + ram_table->dark_pos_gain[0][2] = 0x00; + ram_table->dark_pos_gain[0][3] = 0x00; + ram_table->dark_pos_gain[1][0] = 0x00; + ram_table->dark_pos_gain[1][1] = 0x00; + ram_table->dark_pos_gain[1][2] = 0x00; + ram_table->dark_pos_gain[1][3] = 0x00; + ram_table->dark_pos_gain[2][0] = 0x00; + ram_table->dark_pos_gain[2][1] = 0x00; + ram_table->dark_pos_gain[2][2] = 0x00; + ram_table->dark_pos_gain[2][3] = 0x00; + ram_table->dark_pos_gain[3][0] = 0x00; + ram_table->dark_pos_gain[3][1] = 0x00; + ram_table->dark_pos_gain[3][2] = 0x00; + ram_table->dark_pos_gain[3][3] = 0x00; + ram_table->dark_pos_gain[4][0] = 0x00; + ram_table->dark_pos_gain[4][1] = 0x00; + ram_table->dark_pos_gain[4][2] = 0x00; + ram_table->dark_pos_gain[4][3] = 0x00; + ram_table->dark_neg_gain[0][0] = 0x00; + ram_table->dark_neg_gain[0][1] = 0x00; + ram_table->dark_neg_gain[0][2] = 0x00; + ram_table->dark_neg_gain[0][3] = 0x00; + ram_table->dark_neg_gain[1][0] = 0x00; + ram_table->dark_neg_gain[1][1] = 0x00; + ram_table->dark_neg_gain[1][2] = 0x00; + ram_table->dark_neg_gain[1][3] = 0x00; + ram_table->dark_neg_gain[2][0] = 0x00; + ram_table->dark_neg_gain[2][1] = 0x00; + ram_table->dark_neg_gain[2][2] = 0x00; + ram_table->dark_neg_gain[2][3] = 0x00; + ram_table->dark_neg_gain[3][0] = 0x00; + ram_table->dark_neg_gain[3][1] = 0x00; + ram_table->dark_neg_gain[3][2] = 0x00; + ram_table->dark_neg_gain[3][3] = 0x00; + ram_table->dark_neg_gain[4][0] = 0x00; + ram_table->dark_neg_gain[4][1] = 0x00; + ram_table->dark_neg_gain[4][2] = 0x00; + ram_table->dark_neg_gain[4][3] = 0x00; + + ram_table->iir_curve[0] = 0x65; + ram_table->iir_curve[1] = 0x65; + ram_table->iir_curve[2] = 0x65; + ram_table->iir_curve[3] = 0x65; + ram_table->iir_curve[4] = 0x65; + + //Gamma 2.4 + ram_table->crgb_thresh[0] = cpu_to_be16(0x13b6); + ram_table->crgb_thresh[1] = cpu_to_be16(0x1648); + ram_table->crgb_thresh[2] = cpu_to_be16(0x18e3); + ram_table->crgb_thresh[3] = cpu_to_be16(0x1b41); + ram_table->crgb_thresh[4] = cpu_to_be16(0x1d46); + ram_table->crgb_thresh[5] = cpu_to_be16(0x1f21); + ram_table->crgb_thresh[6] = cpu_to_be16(0x2167); + ram_table->crgb_thresh[7] = cpu_to_be16(0x2384); + ram_table->crgb_offset[0] = cpu_to_be16(0x2999); + ram_table->crgb_offset[1] = cpu_to_be16(0x3999); + ram_table->crgb_offset[2] = cpu_to_be16(0x4666); + ram_table->crgb_offset[3] = cpu_to_be16(0x5999); + ram_table->crgb_offset[4] = cpu_to_be16(0x6333); + ram_table->crgb_offset[5] = cpu_to_be16(0x7800); + ram_table->crgb_offset[6] = cpu_to_be16(0x8c00); + ram_table->crgb_offset[7] = cpu_to_be16(0xa000); + ram_table->crgb_slope[0] = cpu_to_be16(0x3147); + ram_table->crgb_slope[1] = cpu_to_be16(0x2978); + ram_table->crgb_slope[2] = cpu_to_be16(0x23a2); + ram_table->crgb_slope[3] = cpu_to_be16(0x1f55); + ram_table->crgb_slope[4] = cpu_to_be16(0x1c63); + ram_table->crgb_slope[5] = cpu_to_be16(0x1a0f); + ram_table->crgb_slope[6] = cpu_to_be16(0x178d); + ram_table->crgb_slope[7] = cpu_to_be16(0x15ab); + + fill_backlight_transform_table( + params, ram_table); +} + +static void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params) +{ + unsigned int set = params.set; + + ram_table->flags = 0x0; + + ram_table->min_abm_backlight = + cpu_to_be16(params.min_abm_backlight); + + ram_table->deviation_gain[0] = 0xb3; + ram_table->deviation_gain[1] = 0xa8; + ram_table->deviation_gain[2] = 0x98; + ram_table->deviation_gain[3] = 0x68; + + ram_table->min_reduction[0][0] = min_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->min_reduction[1][0] = min_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->min_reduction[2][0] = min_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->min_reduction[3][0] = min_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->min_reduction[4][0] = min_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->max_reduction[0][0] = max_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->max_reduction[1][0] = max_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->max_reduction[2][0] = max_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->max_reduction[3][0] = max_reduction_table_v_2_2[abm_config[set][0]]; + ram_table->max_reduction[4][0] = max_reduction_table_v_2_2[abm_config[set][0]]; + + ram_table->min_reduction[0][1] = min_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->min_reduction[1][1] = min_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->min_reduction[2][1] = min_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->min_reduction[3][1] = min_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->min_reduction[4][1] = min_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->max_reduction[0][1] = max_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->max_reduction[1][1] = max_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->max_reduction[2][1] = max_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->max_reduction[3][1] = max_reduction_table_v_2_2[abm_config[set][1]]; + ram_table->max_reduction[4][1] = max_reduction_table_v_2_2[abm_config[set][1]]; + + ram_table->min_reduction[0][2] = min_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->min_reduction[1][2] = min_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->min_reduction[2][2] = min_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->min_reduction[3][2] = min_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->min_reduction[4][2] = min_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->max_reduction[0][2] = max_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->max_reduction[1][2] = max_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->max_reduction[2][2] = max_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->max_reduction[3][2] = max_reduction_table_v_2_2[abm_config[set][2]]; + ram_table->max_reduction[4][2] = max_reduction_table_v_2_2[abm_config[set][2]]; + + ram_table->min_reduction[0][3] = min_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->min_reduction[1][3] = min_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->min_reduction[2][3] = min_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->min_reduction[3][3] = min_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->min_reduction[4][3] = min_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->max_reduction[0][3] = max_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->max_reduction[1][3] = max_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->max_reduction[2][3] = max_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->max_reduction[3][3] = max_reduction_table_v_2_2[abm_config[set][3]]; + ram_table->max_reduction[4][3] = max_reduction_table_v_2_2[abm_config[set][3]]; + + ram_table->bright_pos_gain[0][0] = 0x20; + ram_table->bright_pos_gain[0][1] = 0x20; + ram_table->bright_pos_gain[0][2] = 0x20; + ram_table->bright_pos_gain[0][3] = 0x20; + ram_table->bright_pos_gain[1][0] = 0x20; + ram_table->bright_pos_gain[1][1] = 0x20; + ram_table->bright_pos_gain[1][2] = 0x20; + ram_table->bright_pos_gain[1][3] = 0x20; + ram_table->bright_pos_gain[2][0] = 0x20; + ram_table->bright_pos_gain[2][1] = 0x20; + ram_table->bright_pos_gain[2][2] = 0x20; + ram_table->bright_pos_gain[2][3] = 0x20; + ram_table->bright_pos_gain[3][0] = 0x20; + ram_table->bright_pos_gain[3][1] = 0x20; + ram_table->bright_pos_gain[3][2] = 0x20; + ram_table->bright_pos_gain[3][3] = 0x20; + ram_table->bright_pos_gain[4][0] = 0x20; + ram_table->bright_pos_gain[4][1] = 0x20; + ram_table->bright_pos_gain[4][2] = 0x20; + ram_table->bright_pos_gain[4][3] = 0x20; + + ram_table->dark_pos_gain[0][0] = 0x00; + ram_table->dark_pos_gain[0][1] = 0x00; + ram_table->dark_pos_gain[0][2] = 0x00; + ram_table->dark_pos_gain[0][3] = 0x00; + ram_table->dark_pos_gain[1][0] = 0x00; + ram_table->dark_pos_gain[1][1] = 0x00; + ram_table->dark_pos_gain[1][2] = 0x00; + ram_table->dark_pos_gain[1][3] = 0x00; + ram_table->dark_pos_gain[2][0] = 0x00; + ram_table->dark_pos_gain[2][1] = 0x00; + ram_table->dark_pos_gain[2][2] = 0x00; + ram_table->dark_pos_gain[2][3] = 0x00; + ram_table->dark_pos_gain[3][0] = 0x00; + ram_table->dark_pos_gain[3][1] = 0x00; + ram_table->dark_pos_gain[3][2] = 0x00; + ram_table->dark_pos_gain[3][3] = 0x00; + ram_table->dark_pos_gain[4][0] = 0x00; + ram_table->dark_pos_gain[4][1] = 0x00; + ram_table->dark_pos_gain[4][2] = 0x00; + ram_table->dark_pos_gain[4][3] = 0x00; + + ram_table->hybrid_factor[0] = 0xff; + ram_table->hybrid_factor[1] = 0xff; + ram_table->hybrid_factor[2] = 0xff; + ram_table->hybrid_factor[3] = 0xc0; + + ram_table->contrast_factor[0] = 0x99; + ram_table->contrast_factor[1] = 0x99; + ram_table->contrast_factor[2] = 0x90; + ram_table->contrast_factor[3] = 0x80; + + ram_table->iir_curve[0] = 0x65; + ram_table->iir_curve[1] = 0x65; + ram_table->iir_curve[2] = 0x65; + ram_table->iir_curve[3] = 0x65; + ram_table->iir_curve[4] = 0x65; + + //Gamma 2.2 + ram_table->crgb_thresh[0] = cpu_to_be16(0x127c); + ram_table->crgb_thresh[1] = cpu_to_be16(0x151b); + ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5); + ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56); + ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83); + ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72); + ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0); + ram_table->crgb_thresh[7] = cpu_to_be16(0x232b); + ram_table->crgb_offset[0] = cpu_to_be16(0x2999); + ram_table->crgb_offset[1] = cpu_to_be16(0x3999); + ram_table->crgb_offset[2] = cpu_to_be16(0x4666); + ram_table->crgb_offset[3] = cpu_to_be16(0x5999); + ram_table->crgb_offset[4] = cpu_to_be16(0x6333); + ram_table->crgb_offset[5] = cpu_to_be16(0x7800); + ram_table->crgb_offset[6] = cpu_to_be16(0x8c00); + ram_table->crgb_offset[7] = cpu_to_be16(0xa000); + ram_table->crgb_slope[0] = cpu_to_be16(0x3609); + ram_table->crgb_slope[1] = cpu_to_be16(0x2dfa); + ram_table->crgb_slope[2] = cpu_to_be16(0x27ea); + ram_table->crgb_slope[3] = cpu_to_be16(0x235d); + ram_table->crgb_slope[4] = cpu_to_be16(0x2042); + ram_table->crgb_slope[5] = cpu_to_be16(0x1dc3); + ram_table->crgb_slope[6] = cpu_to_be16(0x1b1a); + ram_table->crgb_slope[7] = cpu_to_be16(0x1910); + + fill_backlight_transform_table_v_2_2( + params, ram_table, true); +} + +static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params, bool big_endian) +{ + unsigned int i, j; + unsigned int set = params.set; + + ram_table->flags = 0x0; + ram_table->min_abm_backlight = (uint16_t)((big_endian) ? + cpu_to_be16(params.min_abm_backlight) : + cpu_to_le16(params.min_abm_backlight)); + + for (i = 0; i < NUM_AGGR_LEVEL; i++) { + ram_table->hybrid_factor[i] = (uint8_t)abm_settings[set][i].brightness_gain; + ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor; + ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain; + ram_table->min_knee[i] = abm_settings[set][i].min_knee; + ram_table->max_knee[i] = abm_settings[set][i].max_knee; + + for (j = 0; j < NUM_AMBI_LEVEL; j++) { + ram_table->min_reduction[j][i] = abm_settings[set][i].min_reduction; + ram_table->max_reduction[j][i] = abm_settings[set][i].max_reduction; + ram_table->bright_pos_gain[j][i] = abm_settings[set][i].bright_pos_gain; + ram_table->dark_pos_gain[j][i] = abm_settings[set][i].dark_pos_gain; + } + } + + ram_table->iir_curve[0] = 0x65; + ram_table->iir_curve[1] = 0x65; + ram_table->iir_curve[2] = 0x65; + ram_table->iir_curve[3] = 0x65; + ram_table->iir_curve[4] = 0x65; + + //Gamma 2.2 + ram_table->crgb_thresh[0] = bswap16_based_on_endian(big_endian, 0x127c); + ram_table->crgb_thresh[1] = bswap16_based_on_endian(big_endian, 0x151b); + ram_table->crgb_thresh[2] = bswap16_based_on_endian(big_endian, 0x17d5); + ram_table->crgb_thresh[3] = bswap16_based_on_endian(big_endian, 0x1a56); + ram_table->crgb_thresh[4] = bswap16_based_on_endian(big_endian, 0x1c83); + ram_table->crgb_thresh[5] = bswap16_based_on_endian(big_endian, 0x1e72); + ram_table->crgb_thresh[6] = bswap16_based_on_endian(big_endian, 0x20f0); + ram_table->crgb_thresh[7] = bswap16_based_on_endian(big_endian, 0x232b); + ram_table->crgb_offset[0] = bswap16_based_on_endian(big_endian, 0x2999); + ram_table->crgb_offset[1] = bswap16_based_on_endian(big_endian, 0x3999); + ram_table->crgb_offset[2] = bswap16_based_on_endian(big_endian, 0x4666); + ram_table->crgb_offset[3] = bswap16_based_on_endian(big_endian, 0x5999); + ram_table->crgb_offset[4] = bswap16_based_on_endian(big_endian, 0x6333); + ram_table->crgb_offset[5] = bswap16_based_on_endian(big_endian, 0x7800); + ram_table->crgb_offset[6] = bswap16_based_on_endian(big_endian, 0x8c00); + ram_table->crgb_offset[7] = bswap16_based_on_endian(big_endian, 0xa000); + ram_table->crgb_slope[0] = bswap16_based_on_endian(big_endian, 0x3609); + ram_table->crgb_slope[1] = bswap16_based_on_endian(big_endian, 0x2dfa); + ram_table->crgb_slope[2] = bswap16_based_on_endian(big_endian, 0x27ea); + ram_table->crgb_slope[3] = bswap16_based_on_endian(big_endian, 0x235d); + ram_table->crgb_slope[4] = bswap16_based_on_endian(big_endian, 0x2042); + ram_table->crgb_slope[5] = bswap16_based_on_endian(big_endian, 0x1dc3); + ram_table->crgb_slope[6] = bswap16_based_on_endian(big_endian, 0x1b1a); + ram_table->crgb_slope[7] = bswap16_based_on_endian(big_endian, 0x1910); + + fill_backlight_transform_table_v_2_2( + params, ram_table, big_endian); +} + +bool dmub_init_abm_config(struct resource_pool *res_pool, + struct dmcu_iram_parameters params, + unsigned int inst) +{ + struct iram_table_v_2_2 ram_table; + struct abm_config_table config; + unsigned int set = params.set; + bool result = false; + uint32_t i, j = 0; + + if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL) + return false; + + memset(&ram_table, 0, sizeof(ram_table)); + memset(&config, 0, sizeof(config)); + + fill_iram_v_2_3(&ram_table, params, false); + + // We must copy to structure that is aligned to 32-bit + for (i = 0; i < NUM_POWER_FN_SEGS; i++) { + config.crgb_thresh[i] = ram_table.crgb_thresh[i]; + config.crgb_offset[i] = ram_table.crgb_offset[i]; + config.crgb_slope[i] = ram_table.crgb_slope[i]; + } + + for (i = 0; i < NUM_BL_CURVE_SEGS; i++) { + config.backlight_thresholds[i] = ram_table.backlight_thresholds[i]; + config.backlight_offsets[i] = ram_table.backlight_offsets[i]; + } + + for (i = 0; i < NUM_AMBI_LEVEL; i++) + config.iir_curve[i] = ram_table.iir_curve[i]; + + for (i = 0; i < NUM_AMBI_LEVEL; i++) { + for (j = 0; j < NUM_AGGR_LEVEL; j++) { + config.min_reduction[i][j] = ram_table.min_reduction[i][j]; + config.max_reduction[i][j] = ram_table.max_reduction[i][j]; + config.bright_pos_gain[i][j] = ram_table.bright_pos_gain[i][j]; + config.dark_pos_gain[i][j] = ram_table.dark_pos_gain[i][j]; + } + } + + for (i = 0; i < NUM_AGGR_LEVEL; i++) { + config.hybrid_factor[i] = ram_table.hybrid_factor[i]; + config.contrast_factor[i] = ram_table.contrast_factor[i]; + config.deviation_gain[i] = ram_table.deviation_gain[i]; + config.min_knee[i] = ram_table.min_knee[i]; + config.max_knee[i] = ram_table.max_knee[i]; + } + + if (params.backlight_ramping_override) { + + ASSERT(params.backlight_ramping_reduction <= 0xFFFF); + ASSERT(params.backlight_ramping_start <= 0xFFFF); + for (i = 0; i < NUM_AGGR_LEVEL; i++) { + config.blRampReduction[i] = (uint16_t)params.backlight_ramping_reduction; + config.blRampStart[i] = (uint16_t)params.backlight_ramping_start; + } + } else { + for (i = 0; i < NUM_AGGR_LEVEL; i++) { + config.blRampReduction[i] = abm_settings[set][i].blRampReduction; + config.blRampStart[i] = abm_settings[set][i].blRampStart; + } + } + + config.min_abm_backlight = ram_table.min_abm_backlight; + + if (res_pool->multiple_abms[inst]) { + result = res_pool->multiple_abms[inst]->funcs->init_abm_config( + res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst); + } else + result = res_pool->abm->funcs->init_abm_config( + res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0); + + return result; +} + +bool dmcu_load_iram(struct dmcu *dmcu, + struct dmcu_iram_parameters params) +{ + unsigned char ram_table[IRAM_SIZE]; + bool result = false; + + if (dmcu == NULL) + return false; + + if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu)) + return true; + + memset(&ram_table, 0, sizeof(ram_table)); + + if (dmcu->dmcu_version.abm_version == 0x24) { + fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true); + result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table), + IRAM_RESERVE_AREA_START_V2_2); + } else if (dmcu->dmcu_version.abm_version == 0x23) { + fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true); + + result = dmcu->funcs->load_iram( + dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2); + } else if (dmcu->dmcu_version.abm_version == 0x22) { + fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params); + + result = dmcu->funcs->load_iram( + dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2); + } else { + fill_iram_v_2((struct iram_table_v_2 *)ram_table, params); + + result = dmcu->funcs->load_iram( + dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2); + + if (result) + result = dmcu->funcs->load_iram( + dmcu, IRAM_RESERVE_AREA_END_V2 + 1, + (char *)(&ram_table) + IRAM_RESERVE_AREA_END_V2 + 1, + sizeof(ram_table) - IRAM_RESERVE_AREA_END_V2 - 1); + } + + return result; +} + +bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_backlight_caps *caps) +{ + unsigned int data_points_size; + uint64_t caps_size; + + if (config_no >= ARRAY_SIZE(custom_backlight_profiles)) + return false; + + data_points_size = custom_backlight_profiles[config_no].num_data_points + * sizeof(custom_backlight_profiles[config_no].data_points[0]); + + caps_size = sizeof(struct dm_acpi_atif_backlight_caps) - sizeof(caps->data_points) + data_points_size; + ASSERT(caps_size <= 0xFFFF); + caps->size = (uint16_t)caps_size; + caps->flags = 0; + caps->error_code = 0; + caps->ac_level_percentage = custom_backlight_profiles[config_no].ac_level_percentage; + caps->dc_level_percentage = custom_backlight_profiles[config_no].dc_level_percentage; + caps->min_input_signal = custom_backlight_profiles[config_no].min_input_signal; + caps->max_input_signal = custom_backlight_profiles[config_no].max_input_signal; + caps->num_data_points = (uint8_t)custom_backlight_profiles[config_no].num_data_points; + memcpy(caps->data_points, custom_backlight_profiles[config_no].data_points, data_points_size); + return true; +} diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c index f55c15199fb4..1046fc35f8f9 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -33,796 +33,6 @@ #define bswap16_based_on_endian(big_endian, value) \ ((big_endian) ? cpu_to_be16(value) : cpu_to_le16(value)) -/* Possible Min Reduction config from least aggressive to most aggressive - * 0 1 2 3 4 5 6 7 8 9 10 11 12 - * 100 98.0 94.1 94.1 85.1 80.3 75.3 69.4 60.0 57.6 50.2 49.8 40.0 % - */ -static const unsigned char min_reduction_table[13] = { -0xff, 0xfa, 0xf0, 0xf0, 0xd9, 0xcd, 0xc0, 0xb1, 0x99, 0x93, 0x80, 0x82, 0x66}; - -/* Possible Max Reduction configs from least aggressive to most aggressive - * 0 1 2 3 4 5 6 7 8 9 10 11 12 - * 96.1 89.8 85.1 80.3 69.4 64.7 64.7 50.2 39.6 30.2 30.2 30.2 19.6 % - */ -static const unsigned char max_reduction_table[13] = { -0xf5, 0xe5, 0xd9, 0xcd, 0xb1, 0xa5, 0xa5, 0x80, 0x65, 0x4d, 0x4d, 0x4d, 0x32}; - -/* Possible ABM 2.2 Min Reduction configs from least aggressive to most aggressive - * 0 1 2 3 4 5 6 7 8 9 10 11 12 - * 100 100 100 100 100 100 100 100 100 92.2 83.1 75.3 75.3 % - */ -static const unsigned char min_reduction_table_v_2_2[13] = { -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xeb, 0xd4, 0xc0, 0xc0}; - -/* Possible ABM 2.2 Max Reduction configs from least aggressive to most aggressive - * 0 1 2 3 4 5 6 7 8 9 10 11 12 - * 96.1 89.8 74.9 69.4 64.7 52.2 48.6 39.6 30.2 25.1 19.6 12.5 12.5 % - */ -static const unsigned char max_reduction_table_v_2_2[13] = { -0xf5, 0xe5, 0xbf, 0xb1, 0xa5, 0x85, 0x7c, 0x65, 0x4d, 0x40, 0x32, 0x20, 0x20}; - -/* Predefined ABM configuration sets. We may have different configuration sets - * in order to satisfy different power/quality requirements. - */ -static const unsigned char abm_config[abm_defines_max_config][abm_defines_max_level] = { -/* ABM Level 1, ABM Level 2, ABM Level 3, ABM Level 4 */ -{ 2, 5, 7, 8 }, /* Default - Medium aggressiveness */ -{ 2, 5, 8, 11 }, /* Alt #1 - Increased aggressiveness */ -{ 0, 2, 4, 8 }, /* Alt #2 - Minimal aggressiveness */ -{ 3, 6, 10, 12 }, /* Alt #3 - Super aggressiveness */ -}; - -struct abm_parameters { - unsigned char min_reduction; - unsigned char max_reduction; - unsigned char bright_pos_gain; - unsigned char dark_pos_gain; - unsigned char brightness_gain; - unsigned char contrast_factor; - unsigned char deviation_gain; - unsigned char min_knee; - unsigned char max_knee; - unsigned short blRampReduction; - unsigned short blRampStart; -}; - -static const struct abm_parameters abm_settings_config0[abm_defines_max_level] = { -// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart - {0xff, 0xbf, 0x20, 0x00, 0xff, 0x99, 0xb3, 0x40, 0xe0, 0xf777, 0xcccc}, - {0xde, 0x85, 0x20, 0x00, 0xe0, 0x90, 0xa8, 0x40, 0xc8, 0xf777, 0xcccc}, - {0xb0, 0x50, 0x20, 0x00, 0xc0, 0x88, 0x78, 0x70, 0xa0, 0xeeee, 0x9999}, - {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xe333, 0xb333}, -}; - -static const struct abm_parameters abm_settings_config1[abm_defines_max_level] = { -// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart - {0xf0, 0xd9, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, - {0xcd, 0xa5, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, - {0x99, 0x65, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, - {0x82, 0x4d, 0x20, 0x00, 0x00, 0xff, 0xb3, 0x70, 0x70, 0xcccc, 0xcccc}, -}; - -static const struct abm_parameters abm_settings_config2[abm_defines_max_level] = { -// min_red max_red bright_pos dark_pos bright_gain contrast dev min_knee max_knee blRed blStart - {0xf0, 0xbf, 0x20, 0x00, 0x88, 0x99, 0xb3, 0x40, 0xe0, 0x0000, 0xcccc}, - {0xd8, 0x85, 0x20, 0x00, 0x70, 0x90, 0xa8, 0x40, 0xc8, 0x0700, 0xb333}, - {0xb8, 0x58, 0x20, 0x00, 0x64, 0x88, 0x78, 0x70, 0xa0, 0x7000, 0x9999}, - {0x82, 0x40, 0x20, 0x00, 0x00, 0xb8, 0xb3, 0x70, 0x70, 0xc333, 0xb333}, -}; - -static const struct abm_parameters * const abm_settings[] = { - abm_settings_config0, - abm_settings_config1, - abm_settings_config2, -}; - -static const struct dm_bl_data_point custom_backlight_curve0[] = { - {2, 14}, {4, 16}, {6, 18}, {8, 21}, {10, 23}, {12, 26}, {14, 29}, {16, 32}, {18, 35}, - {20, 38}, {22, 41}, {24, 44}, {26, 48}, {28, 52}, {30, 55}, {32, 59}, {34, 62}, - {36, 67}, {38, 71}, {40, 75}, {42, 80}, {44, 84}, {46, 88}, {48, 93}, {50, 98}, - {52, 103}, {54, 108}, {56, 113}, {58, 118}, {60, 123}, {62, 129}, {64, 135}, {66, 140}, - {68, 146}, {70, 152}, {72, 158}, {74, 164}, {76, 171}, {78, 177}, {80, 183}, {82, 190}, - {84, 197}, {86, 204}, {88, 211}, {90, 218}, {92, 225}, {94, 232}, {96, 240}, {98, 247}}; - -struct custom_backlight_profile { - uint8_t ac_level_percentage; - uint8_t dc_level_percentage; - uint8_t min_input_signal; - uint8_t max_input_signal; - uint8_t num_data_points; - const struct dm_bl_data_point *data_points; -}; - -static const struct custom_backlight_profile custom_backlight_profiles[] = { - {100, 32, 12, 255, ARRAY_SIZE(custom_backlight_curve0), custom_backlight_curve0}, -}; - -#define NUM_AMBI_LEVEL 5 -#define NUM_AGGR_LEVEL 4 -#define NUM_POWER_FN_SEGS 8 -#define NUM_BL_CURVE_SEGS 16 -#define IRAM_SIZE 256 - -#define IRAM_RESERVE_AREA_START_V2 0xF0 // reserve 0xF0~0xF6 are write by DMCU only -#define IRAM_RESERVE_AREA_END_V2 0xF6 // reserve 0xF0~0xF6 are write by DMCU only - -#define IRAM_RESERVE_AREA_START_V2_2 0xF0 // reserve 0xF0~0xFF are write by DMCU only -#define IRAM_RESERVE_AREA_END_V2_2 0xFF // reserve 0xF0~0xFF are write by DMCU only - -#pragma pack(push, 1) -/* NOTE: iRAM is 256B in size */ -struct iram_table_v_2 { - /* flags */ - uint16_t min_abm_backlight; /* 0x00 U16 */ - - /* parameters for ABM2.0 algorithm */ - uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */ - uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */ - uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */ - uint8_t bright_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */ - uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x52 U2.6 */ - uint8_t dark_neg_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x66 U2.6 */ - uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x7a U0.8 */ - uint8_t deviation_gain; /* 0x7f U0.8 */ - - /* parameters for crgb conversion */ - uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */ - uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */ - uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */ - - /* parameters for custom curve */ - /* thresholds for brightness --> backlight */ - uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */ - /* offsets for brightness --> backlight */ - uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */ - - /* For reading PSR State directly from IRAM */ - uint8_t psr_state; /* 0xf0 */ - uint8_t dmcu_mcp_interface_version; /* 0xf1 */ - uint8_t dmcu_abm_feature_version; /* 0xf2 */ - uint8_t dmcu_psr_feature_version; /* 0xf3 */ - uint16_t dmcu_version; /* 0xf4 */ - uint8_t dmcu_state; /* 0xf6 */ - - uint16_t blRampReduction; /* 0xf7 */ - uint16_t blRampStart; /* 0xf9 */ - uint8_t dummy5; /* 0xfb */ - uint8_t dummy6; /* 0xfc */ - uint8_t dummy7; /* 0xfd */ - uint8_t dummy8; /* 0xfe */ - uint8_t dummy9; /* 0xff */ -}; - -struct iram_table_v_2_2 { - /* flags */ - uint16_t flags; /* 0x00 U16 */ - - /* parameters for ABM2.2 algorithm */ - uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x02 U0.8 */ - uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x16 U0.8 */ - uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x2a U2.6 */ - uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; /* 0x3e U2.6 */ - uint8_t hybrid_factor[NUM_AGGR_LEVEL]; /* 0x52 U0.8 */ - uint8_t contrast_factor[NUM_AGGR_LEVEL]; /* 0x56 U0.8 */ - uint8_t deviation_gain[NUM_AGGR_LEVEL]; /* 0x5a U0.8 */ - uint8_t iir_curve[NUM_AMBI_LEVEL]; /* 0x5e U0.8 */ - uint8_t min_knee[NUM_AGGR_LEVEL]; /* 0x63 U0.8 */ - uint8_t max_knee[NUM_AGGR_LEVEL]; /* 0x67 U0.8 */ - uint16_t min_abm_backlight; /* 0x6b U16 */ - uint8_t pad[19]; /* 0x6d U0.8 */ - - /* parameters for crgb conversion */ - uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; /* 0x80 U3.13 */ - uint16_t crgb_offset[NUM_POWER_FN_SEGS]; /* 0x90 U1.15 */ - uint16_t crgb_slope[NUM_POWER_FN_SEGS]; /* 0xa0 U4.12 */ - - /* parameters for custom curve */ - /* thresholds for brightness --> backlight */ - uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; /* 0xb0 U16.0 */ - /* offsets for brightness --> backlight */ - uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; /* 0xd0 U16.0 */ - - /* For reading PSR State directly from IRAM */ - uint8_t psr_state; /* 0xf0 */ - uint8_t dmcu_mcp_interface_version; /* 0xf1 */ - uint8_t dmcu_abm_feature_version; /* 0xf2 */ - uint8_t dmcu_psr_feature_version; /* 0xf3 */ - uint16_t dmcu_version; /* 0xf4 */ - uint8_t dmcu_state; /* 0xf6 */ - - uint8_t dummy1; /* 0xf7 */ - uint8_t dummy2; /* 0xf8 */ - uint8_t dummy3; /* 0xf9 */ - uint8_t dummy4; /* 0xfa */ - uint8_t dummy5; /* 0xfb */ - uint8_t dummy6; /* 0xfc */ - uint8_t dummy7; /* 0xfd */ - uint8_t dummy8; /* 0xfe */ - uint8_t dummy9; /* 0xff */ -}; -#pragma pack(pop) - -static void fill_backlight_transform_table(struct dmcu_iram_parameters params, - struct iram_table_v_2 *table) -{ - unsigned int i; - unsigned int num_entries = NUM_BL_CURVE_SEGS; - unsigned int lut_index; - - table->backlight_thresholds[0] = 0; - ASSERT(params.backlight_lut_array[0] <= 0xFFFF); - table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0]; - table->backlight_thresholds[num_entries-1] = 0xFFFF; - ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF); - table->backlight_offsets[num_entries-1] = - (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1]; - - /* Setup all brightness levels between 0% and 100% exclusive - * Fills brightness-to-backlight transform table. Backlight custom curve - * describes transform from brightness to backlight. It will be defined - * as set of thresholds and set of offsets, together, implying - * extrapolation of custom curve into 16 uniformly spanned linear - * segments. Each threshold/offset represented by 16 bit entry in - * format U4.10. - */ - for (i = 1; i+1 < num_entries; i++) { - lut_index = (params.backlight_lut_array_size - 1) * i / (num_entries - 1); - - ASSERT(lut_index < params.backlight_lut_array_size); - - unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries); - unsigned int offset_val = params.backlight_lut_array[lut_index]; - - ASSERT(threshold_val <= 0xFFFF); - ASSERT(offset_val <= 0xFFFF); - - table->backlight_thresholds[i] = cpu_to_be16((uint16_t)threshold_val); - table->backlight_offsets[i] = cpu_to_be16((uint16_t)offset_val); - } -} - -static void fill_backlight_transform_table_v_2_2(struct dmcu_iram_parameters params, - struct iram_table_v_2_2 *table, bool big_endian) -{ - unsigned int i; - unsigned int num_entries = NUM_BL_CURVE_SEGS; - unsigned int lut_index; - - table->backlight_thresholds[0] = 0; - ASSERT(params.backlight_lut_array[0] <= 0xFFFF); - table->backlight_offsets[0] = (uint16_t)params.backlight_lut_array[0]; - table->backlight_thresholds[num_entries-1] = 0xFFFF; - ASSERT(params.backlight_lut_array[params.backlight_lut_array_size - 1] <= 0xFFFF); - table->backlight_offsets[num_entries-1] = - (uint16_t)params.backlight_lut_array[params.backlight_lut_array_size - 1]; - - /* Setup all brightness levels between 0% and 100% exclusive - * Fills brightness-to-backlight transform table. Backlight custom curve - * describes transform from brightness to backlight. It will be defined - * as set of thresholds and set of offsets, together, implying - * extrapolation of custom curve into 16 uniformly spanned linear - * segments. Each threshold/offset represented by 16 bit entry in - * format U4.10. - */ - for (i = 1; i+1 < num_entries; i++) { - lut_index = DIV_ROUNDUP((i * params.backlight_lut_array_size), num_entries); - ASSERT(lut_index < params.backlight_lut_array_size); - - unsigned int threshold_val = DIV_ROUNDUP((i * 65536), num_entries); - unsigned int offset_val = params.backlight_lut_array[lut_index]; - - ASSERT(threshold_val <= 0xFFFF); - ASSERT(offset_val <= 0xFFFF); - - table->backlight_thresholds[i] = (big_endian) ? - cpu_to_be16((uint16_t)threshold_val) : cpu_to_le16((uint16_t)threshold_val); - table->backlight_offsets[i] = (big_endian) ? - cpu_to_be16((uint16_t)offset_val) : cpu_to_le16((uint16_t)offset_val); - } -} - -static void fill_iram_v_2(struct iram_table_v_2 *ram_table, struct dmcu_iram_parameters params) -{ - unsigned int set = params.set; - - ram_table->min_abm_backlight = - cpu_to_be16(params.min_abm_backlight); - ram_table->deviation_gain = 0xb3; - - ram_table->blRampReduction = - cpu_to_be16(params.backlight_ramping_reduction); - ram_table->blRampStart = - cpu_to_be16(params.backlight_ramping_start); - - ram_table->min_reduction[0][0] = min_reduction_table[abm_config[set][0]]; - ram_table->min_reduction[1][0] = min_reduction_table[abm_config[set][0]]; - ram_table->min_reduction[2][0] = min_reduction_table[abm_config[set][0]]; - ram_table->min_reduction[3][0] = min_reduction_table[abm_config[set][0]]; - ram_table->min_reduction[4][0] = min_reduction_table[abm_config[set][0]]; - ram_table->max_reduction[0][0] = max_reduction_table[abm_config[set][0]]; - ram_table->max_reduction[1][0] = max_reduction_table[abm_config[set][0]]; - ram_table->max_reduction[2][0] = max_reduction_table[abm_config[set][0]]; - ram_table->max_reduction[3][0] = max_reduction_table[abm_config[set][0]]; - ram_table->max_reduction[4][0] = max_reduction_table[abm_config[set][0]]; - - ram_table->min_reduction[0][1] = min_reduction_table[abm_config[set][1]]; - ram_table->min_reduction[1][1] = min_reduction_table[abm_config[set][1]]; - ram_table->min_reduction[2][1] = min_reduction_table[abm_config[set][1]]; - ram_table->min_reduction[3][1] = min_reduction_table[abm_config[set][1]]; - ram_table->min_reduction[4][1] = min_reduction_table[abm_config[set][1]]; - ram_table->max_reduction[0][1] = max_reduction_table[abm_config[set][1]]; - ram_table->max_reduction[1][1] = max_reduction_table[abm_config[set][1]]; - ram_table->max_reduction[2][1] = max_reduction_table[abm_config[set][1]]; - ram_table->max_reduction[3][1] = max_reduction_table[abm_config[set][1]]; - ram_table->max_reduction[4][1] = max_reduction_table[abm_config[set][1]]; - - ram_table->min_reduction[0][2] = min_reduction_table[abm_config[set][2]]; - ram_table->min_reduction[1][2] = min_reduction_table[abm_config[set][2]]; - ram_table->min_reduction[2][2] = min_reduction_table[abm_config[set][2]]; - ram_table->min_reduction[3][2] = min_reduction_table[abm_config[set][2]]; - ram_table->min_reduction[4][2] = min_reduction_table[abm_config[set][2]]; - ram_table->max_reduction[0][2] = max_reduction_table[abm_config[set][2]]; - ram_table->max_reduction[1][2] = max_reduction_table[abm_config[set][2]]; - ram_table->max_reduction[2][2] = max_reduction_table[abm_config[set][2]]; - ram_table->max_reduction[3][2] = max_reduction_table[abm_config[set][2]]; - ram_table->max_reduction[4][2] = max_reduction_table[abm_config[set][2]]; - - ram_table->min_reduction[0][3] = min_reduction_table[abm_config[set][3]]; - ram_table->min_reduction[1][3] = min_reduction_table[abm_config[set][3]]; - ram_table->min_reduction[2][3] = min_reduction_table[abm_config[set][3]]; - ram_table->min_reduction[3][3] = min_reduction_table[abm_config[set][3]]; - ram_table->min_reduction[4][3] = min_reduction_table[abm_config[set][3]]; - ram_table->max_reduction[0][3] = max_reduction_table[abm_config[set][3]]; - ram_table->max_reduction[1][3] = max_reduction_table[abm_config[set][3]]; - ram_table->max_reduction[2][3] = max_reduction_table[abm_config[set][3]]; - ram_table->max_reduction[3][3] = max_reduction_table[abm_config[set][3]]; - ram_table->max_reduction[4][3] = max_reduction_table[abm_config[set][3]]; - - ram_table->bright_pos_gain[0][0] = 0x20; - ram_table->bright_pos_gain[0][1] = 0x20; - ram_table->bright_pos_gain[0][2] = 0x20; - ram_table->bright_pos_gain[0][3] = 0x20; - ram_table->bright_pos_gain[1][0] = 0x20; - ram_table->bright_pos_gain[1][1] = 0x20; - ram_table->bright_pos_gain[1][2] = 0x20; - ram_table->bright_pos_gain[1][3] = 0x20; - ram_table->bright_pos_gain[2][0] = 0x20; - ram_table->bright_pos_gain[2][1] = 0x20; - ram_table->bright_pos_gain[2][2] = 0x20; - ram_table->bright_pos_gain[2][3] = 0x20; - ram_table->bright_pos_gain[3][0] = 0x20; - ram_table->bright_pos_gain[3][1] = 0x20; - ram_table->bright_pos_gain[3][2] = 0x20; - ram_table->bright_pos_gain[3][3] = 0x20; - ram_table->bright_pos_gain[4][0] = 0x20; - ram_table->bright_pos_gain[4][1] = 0x20; - ram_table->bright_pos_gain[4][2] = 0x20; - ram_table->bright_pos_gain[4][3] = 0x20; - ram_table->bright_neg_gain[0][0] = 0x00; - ram_table->bright_neg_gain[0][1] = 0x00; - ram_table->bright_neg_gain[0][2] = 0x00; - ram_table->bright_neg_gain[0][3] = 0x00; - ram_table->bright_neg_gain[1][0] = 0x00; - ram_table->bright_neg_gain[1][1] = 0x00; - ram_table->bright_neg_gain[1][2] = 0x00; - ram_table->bright_neg_gain[1][3] = 0x00; - ram_table->bright_neg_gain[2][0] = 0x00; - ram_table->bright_neg_gain[2][1] = 0x00; - ram_table->bright_neg_gain[2][2] = 0x00; - ram_table->bright_neg_gain[2][3] = 0x00; - ram_table->bright_neg_gain[3][0] = 0x00; - ram_table->bright_neg_gain[3][1] = 0x00; - ram_table->bright_neg_gain[3][2] = 0x00; - ram_table->bright_neg_gain[3][3] = 0x00; - ram_table->bright_neg_gain[4][0] = 0x00; - ram_table->bright_neg_gain[4][1] = 0x00; - ram_table->bright_neg_gain[4][2] = 0x00; - ram_table->bright_neg_gain[4][3] = 0x00; - ram_table->dark_pos_gain[0][0] = 0x00; - ram_table->dark_pos_gain[0][1] = 0x00; - ram_table->dark_pos_gain[0][2] = 0x00; - ram_table->dark_pos_gain[0][3] = 0x00; - ram_table->dark_pos_gain[1][0] = 0x00; - ram_table->dark_pos_gain[1][1] = 0x00; - ram_table->dark_pos_gain[1][2] = 0x00; - ram_table->dark_pos_gain[1][3] = 0x00; - ram_table->dark_pos_gain[2][0] = 0x00; - ram_table->dark_pos_gain[2][1] = 0x00; - ram_table->dark_pos_gain[2][2] = 0x00; - ram_table->dark_pos_gain[2][3] = 0x00; - ram_table->dark_pos_gain[3][0] = 0x00; - ram_table->dark_pos_gain[3][1] = 0x00; - ram_table->dark_pos_gain[3][2] = 0x00; - ram_table->dark_pos_gain[3][3] = 0x00; - ram_table->dark_pos_gain[4][0] = 0x00; - ram_table->dark_pos_gain[4][1] = 0x00; - ram_table->dark_pos_gain[4][2] = 0x00; - ram_table->dark_pos_gain[4][3] = 0x00; - ram_table->dark_neg_gain[0][0] = 0x00; - ram_table->dark_neg_gain[0][1] = 0x00; - ram_table->dark_neg_gain[0][2] = 0x00; - ram_table->dark_neg_gain[0][3] = 0x00; - ram_table->dark_neg_gain[1][0] = 0x00; - ram_table->dark_neg_gain[1][1] = 0x00; - ram_table->dark_neg_gain[1][2] = 0x00; - ram_table->dark_neg_gain[1][3] = 0x00; - ram_table->dark_neg_gain[2][0] = 0x00; - ram_table->dark_neg_gain[2][1] = 0x00; - ram_table->dark_neg_gain[2][2] = 0x00; - ram_table->dark_neg_gain[2][3] = 0x00; - ram_table->dark_neg_gain[3][0] = 0x00; - ram_table->dark_neg_gain[3][1] = 0x00; - ram_table->dark_neg_gain[3][2] = 0x00; - ram_table->dark_neg_gain[3][3] = 0x00; - ram_table->dark_neg_gain[4][0] = 0x00; - ram_table->dark_neg_gain[4][1] = 0x00; - ram_table->dark_neg_gain[4][2] = 0x00; - ram_table->dark_neg_gain[4][3] = 0x00; - - ram_table->iir_curve[0] = 0x65; - ram_table->iir_curve[1] = 0x65; - ram_table->iir_curve[2] = 0x65; - ram_table->iir_curve[3] = 0x65; - ram_table->iir_curve[4] = 0x65; - - //Gamma 2.4 - ram_table->crgb_thresh[0] = cpu_to_be16(0x13b6); - ram_table->crgb_thresh[1] = cpu_to_be16(0x1648); - ram_table->crgb_thresh[2] = cpu_to_be16(0x18e3); - ram_table->crgb_thresh[3] = cpu_to_be16(0x1b41); - ram_table->crgb_thresh[4] = cpu_to_be16(0x1d46); - ram_table->crgb_thresh[5] = cpu_to_be16(0x1f21); - ram_table->crgb_thresh[6] = cpu_to_be16(0x2167); - ram_table->crgb_thresh[7] = cpu_to_be16(0x2384); - ram_table->crgb_offset[0] = cpu_to_be16(0x2999); - ram_table->crgb_offset[1] = cpu_to_be16(0x3999); - ram_table->crgb_offset[2] = cpu_to_be16(0x4666); - ram_table->crgb_offset[3] = cpu_to_be16(0x5999); - ram_table->crgb_offset[4] = cpu_to_be16(0x6333); - ram_table->crgb_offset[5] = cpu_to_be16(0x7800); - ram_table->crgb_offset[6] = cpu_to_be16(0x8c00); - ram_table->crgb_offset[7] = cpu_to_be16(0xa000); - ram_table->crgb_slope[0] = cpu_to_be16(0x3147); - ram_table->crgb_slope[1] = cpu_to_be16(0x2978); - ram_table->crgb_slope[2] = cpu_to_be16(0x23a2); - ram_table->crgb_slope[3] = cpu_to_be16(0x1f55); - ram_table->crgb_slope[4] = cpu_to_be16(0x1c63); - ram_table->crgb_slope[5] = cpu_to_be16(0x1a0f); - ram_table->crgb_slope[6] = cpu_to_be16(0x178d); - ram_table->crgb_slope[7] = cpu_to_be16(0x15ab); - - fill_backlight_transform_table( - params, ram_table); -} - -static void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params) -{ - unsigned int set = params.set; - - ram_table->flags = 0x0; - - ram_table->min_abm_backlight = - cpu_to_be16(params.min_abm_backlight); - - ram_table->deviation_gain[0] = 0xb3; - ram_table->deviation_gain[1] = 0xa8; - ram_table->deviation_gain[2] = 0x98; - ram_table->deviation_gain[3] = 0x68; - - ram_table->min_reduction[0][0] = min_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->min_reduction[1][0] = min_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->min_reduction[2][0] = min_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->min_reduction[3][0] = min_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->min_reduction[4][0] = min_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->max_reduction[0][0] = max_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->max_reduction[1][0] = max_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->max_reduction[2][0] = max_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->max_reduction[3][0] = max_reduction_table_v_2_2[abm_config[set][0]]; - ram_table->max_reduction[4][0] = max_reduction_table_v_2_2[abm_config[set][0]]; - - ram_table->min_reduction[0][1] = min_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->min_reduction[1][1] = min_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->min_reduction[2][1] = min_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->min_reduction[3][1] = min_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->min_reduction[4][1] = min_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->max_reduction[0][1] = max_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->max_reduction[1][1] = max_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->max_reduction[2][1] = max_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->max_reduction[3][1] = max_reduction_table_v_2_2[abm_config[set][1]]; - ram_table->max_reduction[4][1] = max_reduction_table_v_2_2[abm_config[set][1]]; - - ram_table->min_reduction[0][2] = min_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->min_reduction[1][2] = min_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->min_reduction[2][2] = min_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->min_reduction[3][2] = min_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->min_reduction[4][2] = min_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->max_reduction[0][2] = max_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->max_reduction[1][2] = max_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->max_reduction[2][2] = max_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->max_reduction[3][2] = max_reduction_table_v_2_2[abm_config[set][2]]; - ram_table->max_reduction[4][2] = max_reduction_table_v_2_2[abm_config[set][2]]; - - ram_table->min_reduction[0][3] = min_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->min_reduction[1][3] = min_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->min_reduction[2][3] = min_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->min_reduction[3][3] = min_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->min_reduction[4][3] = min_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->max_reduction[0][3] = max_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->max_reduction[1][3] = max_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->max_reduction[2][3] = max_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->max_reduction[3][3] = max_reduction_table_v_2_2[abm_config[set][3]]; - ram_table->max_reduction[4][3] = max_reduction_table_v_2_2[abm_config[set][3]]; - - ram_table->bright_pos_gain[0][0] = 0x20; - ram_table->bright_pos_gain[0][1] = 0x20; - ram_table->bright_pos_gain[0][2] = 0x20; - ram_table->bright_pos_gain[0][3] = 0x20; - ram_table->bright_pos_gain[1][0] = 0x20; - ram_table->bright_pos_gain[1][1] = 0x20; - ram_table->bright_pos_gain[1][2] = 0x20; - ram_table->bright_pos_gain[1][3] = 0x20; - ram_table->bright_pos_gain[2][0] = 0x20; - ram_table->bright_pos_gain[2][1] = 0x20; - ram_table->bright_pos_gain[2][2] = 0x20; - ram_table->bright_pos_gain[2][3] = 0x20; - ram_table->bright_pos_gain[3][0] = 0x20; - ram_table->bright_pos_gain[3][1] = 0x20; - ram_table->bright_pos_gain[3][2] = 0x20; - ram_table->bright_pos_gain[3][3] = 0x20; - ram_table->bright_pos_gain[4][0] = 0x20; - ram_table->bright_pos_gain[4][1] = 0x20; - ram_table->bright_pos_gain[4][2] = 0x20; - ram_table->bright_pos_gain[4][3] = 0x20; - - ram_table->dark_pos_gain[0][0] = 0x00; - ram_table->dark_pos_gain[0][1] = 0x00; - ram_table->dark_pos_gain[0][2] = 0x00; - ram_table->dark_pos_gain[0][3] = 0x00; - ram_table->dark_pos_gain[1][0] = 0x00; - ram_table->dark_pos_gain[1][1] = 0x00; - ram_table->dark_pos_gain[1][2] = 0x00; - ram_table->dark_pos_gain[1][3] = 0x00; - ram_table->dark_pos_gain[2][0] = 0x00; - ram_table->dark_pos_gain[2][1] = 0x00; - ram_table->dark_pos_gain[2][2] = 0x00; - ram_table->dark_pos_gain[2][3] = 0x00; - ram_table->dark_pos_gain[3][0] = 0x00; - ram_table->dark_pos_gain[3][1] = 0x00; - ram_table->dark_pos_gain[3][2] = 0x00; - ram_table->dark_pos_gain[3][3] = 0x00; - ram_table->dark_pos_gain[4][0] = 0x00; - ram_table->dark_pos_gain[4][1] = 0x00; - ram_table->dark_pos_gain[4][2] = 0x00; - ram_table->dark_pos_gain[4][3] = 0x00; - - ram_table->hybrid_factor[0] = 0xff; - ram_table->hybrid_factor[1] = 0xff; - ram_table->hybrid_factor[2] = 0xff; - ram_table->hybrid_factor[3] = 0xc0; - - ram_table->contrast_factor[0] = 0x99; - ram_table->contrast_factor[1] = 0x99; - ram_table->contrast_factor[2] = 0x90; - ram_table->contrast_factor[3] = 0x80; - - ram_table->iir_curve[0] = 0x65; - ram_table->iir_curve[1] = 0x65; - ram_table->iir_curve[2] = 0x65; - ram_table->iir_curve[3] = 0x65; - ram_table->iir_curve[4] = 0x65; - - //Gamma 2.2 - ram_table->crgb_thresh[0] = cpu_to_be16(0x127c); - ram_table->crgb_thresh[1] = cpu_to_be16(0x151b); - ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5); - ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56); - ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83); - ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72); - ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0); - ram_table->crgb_thresh[7] = cpu_to_be16(0x232b); - ram_table->crgb_offset[0] = cpu_to_be16(0x2999); - ram_table->crgb_offset[1] = cpu_to_be16(0x3999); - ram_table->crgb_offset[2] = cpu_to_be16(0x4666); - ram_table->crgb_offset[3] = cpu_to_be16(0x5999); - ram_table->crgb_offset[4] = cpu_to_be16(0x6333); - ram_table->crgb_offset[5] = cpu_to_be16(0x7800); - ram_table->crgb_offset[6] = cpu_to_be16(0x8c00); - ram_table->crgb_offset[7] = cpu_to_be16(0xa000); - ram_table->crgb_slope[0] = cpu_to_be16(0x3609); - ram_table->crgb_slope[1] = cpu_to_be16(0x2dfa); - ram_table->crgb_slope[2] = cpu_to_be16(0x27ea); - ram_table->crgb_slope[3] = cpu_to_be16(0x235d); - ram_table->crgb_slope[4] = cpu_to_be16(0x2042); - ram_table->crgb_slope[5] = cpu_to_be16(0x1dc3); - ram_table->crgb_slope[6] = cpu_to_be16(0x1b1a); - ram_table->crgb_slope[7] = cpu_to_be16(0x1910); - - fill_backlight_transform_table_v_2_2( - params, ram_table, true); -} - -static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parameters params, bool big_endian) -{ - unsigned int i, j; - unsigned int set = params.set; - - ram_table->flags = 0x0; - ram_table->min_abm_backlight = (uint16_t)((big_endian) ? - cpu_to_be16(params.min_abm_backlight) : - cpu_to_le16(params.min_abm_backlight)); - - for (i = 0; i < NUM_AGGR_LEVEL; i++) { - ram_table->hybrid_factor[i] = (uint8_t)abm_settings[set][i].brightness_gain; - ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor; - ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain; - ram_table->min_knee[i] = abm_settings[set][i].min_knee; - ram_table->max_knee[i] = abm_settings[set][i].max_knee; - - for (j = 0; j < NUM_AMBI_LEVEL; j++) { - ram_table->min_reduction[j][i] = abm_settings[set][i].min_reduction; - ram_table->max_reduction[j][i] = abm_settings[set][i].max_reduction; - ram_table->bright_pos_gain[j][i] = abm_settings[set][i].bright_pos_gain; - ram_table->dark_pos_gain[j][i] = abm_settings[set][i].dark_pos_gain; - } - } - - ram_table->iir_curve[0] = 0x65; - ram_table->iir_curve[1] = 0x65; - ram_table->iir_curve[2] = 0x65; - ram_table->iir_curve[3] = 0x65; - ram_table->iir_curve[4] = 0x65; - - //Gamma 2.2 - ram_table->crgb_thresh[0] = bswap16_based_on_endian(big_endian, 0x127c); - ram_table->crgb_thresh[1] = bswap16_based_on_endian(big_endian, 0x151b); - ram_table->crgb_thresh[2] = bswap16_based_on_endian(big_endian, 0x17d5); - ram_table->crgb_thresh[3] = bswap16_based_on_endian(big_endian, 0x1a56); - ram_table->crgb_thresh[4] = bswap16_based_on_endian(big_endian, 0x1c83); - ram_table->crgb_thresh[5] = bswap16_based_on_endian(big_endian, 0x1e72); - ram_table->crgb_thresh[6] = bswap16_based_on_endian(big_endian, 0x20f0); - ram_table->crgb_thresh[7] = bswap16_based_on_endian(big_endian, 0x232b); - ram_table->crgb_offset[0] = bswap16_based_on_endian(big_endian, 0x2999); - ram_table->crgb_offset[1] = bswap16_based_on_endian(big_endian, 0x3999); - ram_table->crgb_offset[2] = bswap16_based_on_endian(big_endian, 0x4666); - ram_table->crgb_offset[3] = bswap16_based_on_endian(big_endian, 0x5999); - ram_table->crgb_offset[4] = bswap16_based_on_endian(big_endian, 0x6333); - ram_table->crgb_offset[5] = bswap16_based_on_endian(big_endian, 0x7800); - ram_table->crgb_offset[6] = bswap16_based_on_endian(big_endian, 0x8c00); - ram_table->crgb_offset[7] = bswap16_based_on_endian(big_endian, 0xa000); - ram_table->crgb_slope[0] = bswap16_based_on_endian(big_endian, 0x3609); - ram_table->crgb_slope[1] = bswap16_based_on_endian(big_endian, 0x2dfa); - ram_table->crgb_slope[2] = bswap16_based_on_endian(big_endian, 0x27ea); - ram_table->crgb_slope[3] = bswap16_based_on_endian(big_endian, 0x235d); - ram_table->crgb_slope[4] = bswap16_based_on_endian(big_endian, 0x2042); - ram_table->crgb_slope[5] = bswap16_based_on_endian(big_endian, 0x1dc3); - ram_table->crgb_slope[6] = bswap16_based_on_endian(big_endian, 0x1b1a); - ram_table->crgb_slope[7] = bswap16_based_on_endian(big_endian, 0x1910); - - fill_backlight_transform_table_v_2_2( - params, ram_table, big_endian); -} - -bool dmub_init_abm_config(struct resource_pool *res_pool, - struct dmcu_iram_parameters params, - unsigned int inst) -{ - struct iram_table_v_2_2 ram_table; - struct abm_config_table config; - unsigned int set = params.set; - bool result = false; - uint32_t i, j = 0; - - if (res_pool->abm == NULL && res_pool->multiple_abms[inst] == NULL) - return false; - - memset(&ram_table, 0, sizeof(ram_table)); - memset(&config, 0, sizeof(config)); - - fill_iram_v_2_3(&ram_table, params, false); - - // We must copy to structure that is aligned to 32-bit - for (i = 0; i < NUM_POWER_FN_SEGS; i++) { - config.crgb_thresh[i] = ram_table.crgb_thresh[i]; - config.crgb_offset[i] = ram_table.crgb_offset[i]; - config.crgb_slope[i] = ram_table.crgb_slope[i]; - } - - for (i = 0; i < NUM_BL_CURVE_SEGS; i++) { - config.backlight_thresholds[i] = ram_table.backlight_thresholds[i]; - config.backlight_offsets[i] = ram_table.backlight_offsets[i]; - } - - for (i = 0; i < NUM_AMBI_LEVEL; i++) - config.iir_curve[i] = ram_table.iir_curve[i]; - - for (i = 0; i < NUM_AMBI_LEVEL; i++) { - for (j = 0; j < NUM_AGGR_LEVEL; j++) { - config.min_reduction[i][j] = ram_table.min_reduction[i][j]; - config.max_reduction[i][j] = ram_table.max_reduction[i][j]; - config.bright_pos_gain[i][j] = ram_table.bright_pos_gain[i][j]; - config.dark_pos_gain[i][j] = ram_table.dark_pos_gain[i][j]; - } - } - - for (i = 0; i < NUM_AGGR_LEVEL; i++) { - config.hybrid_factor[i] = ram_table.hybrid_factor[i]; - config.contrast_factor[i] = ram_table.contrast_factor[i]; - config.deviation_gain[i] = ram_table.deviation_gain[i]; - config.min_knee[i] = ram_table.min_knee[i]; - config.max_knee[i] = ram_table.max_knee[i]; - } - - if (params.backlight_ramping_override) { - - ASSERT(params.backlight_ramping_reduction <= 0xFFFF); - ASSERT(params.backlight_ramping_start <= 0xFFFF); - for (i = 0; i < NUM_AGGR_LEVEL; i++) { - config.blRampReduction[i] = (uint16_t)params.backlight_ramping_reduction; - config.blRampStart[i] = (uint16_t)params.backlight_ramping_start; - } - } else { - for (i = 0; i < NUM_AGGR_LEVEL; i++) { - config.blRampReduction[i] = abm_settings[set][i].blRampReduction; - config.blRampStart[i] = abm_settings[set][i].blRampStart; - } - } - - config.min_abm_backlight = ram_table.min_abm_backlight; - - if (res_pool->multiple_abms[inst]) { - result = res_pool->multiple_abms[inst]->funcs->init_abm_config( - res_pool->multiple_abms[inst], (char *)(&config), sizeof(struct abm_config_table), inst); - } else - result = res_pool->abm->funcs->init_abm_config( - res_pool->abm, (char *)(&config), sizeof(struct abm_config_table), 0); - - return result; -} - -bool dmcu_load_iram(struct dmcu *dmcu, - struct dmcu_iram_parameters params) -{ - unsigned char ram_table[IRAM_SIZE]; - bool result = false; - - if (dmcu == NULL) - return false; - - if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu)) - return true; - - memset(&ram_table, 0, sizeof(ram_table)); - - if (dmcu->dmcu_version.abm_version == 0x24) { - fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true); - result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table), - IRAM_RESERVE_AREA_START_V2_2); - } else if (dmcu->dmcu_version.abm_version == 0x23) { - fill_iram_v_2_3((struct iram_table_v_2_2 *)ram_table, params, true); - - result = dmcu->funcs->load_iram( - dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2); - } else if (dmcu->dmcu_version.abm_version == 0x22) { - fill_iram_v_2_2((struct iram_table_v_2_2 *)ram_table, params); - - result = dmcu->funcs->load_iram( - dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2); - } else { - fill_iram_v_2((struct iram_table_v_2 *)ram_table, params); - - result = dmcu->funcs->load_iram( - dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2); - - if (result) - result = dmcu->funcs->load_iram( - dmcu, IRAM_RESERVE_AREA_END_V2 + 1, - (char *)(&ram_table) + IRAM_RESERVE_AREA_END_V2 + 1, - sizeof(ram_table) - IRAM_RESERVE_AREA_END_V2 - 1); - } - - return result; -} - /* * is_psr_su_specific_panel() - check if sink is AMD vendor-specific PSR-SU * supported eDP device. @@ -1073,31 +283,6 @@ void calculate_replay_link_off_frame_count(struct dc_link *link, link->replay_settings.link_off_frame_count = max_link_off_frame_count; } -bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_backlight_caps *caps) -{ - unsigned int data_points_size; - uint64_t caps_size; - - if (config_no >= ARRAY_SIZE(custom_backlight_profiles)) - return false; - - data_points_size = custom_backlight_profiles[config_no].num_data_points - * sizeof(custom_backlight_profiles[config_no].data_points[0]); - - caps_size = sizeof(struct dm_acpi_atif_backlight_caps) - sizeof(caps->data_points) + data_points_size; - ASSERT(caps_size <= 0xFFFF); - caps->size = (uint16_t)caps_size; - caps->flags = 0; - caps->error_code = 0; - caps->ac_level_percentage = custom_backlight_profiles[config_no].ac_level_percentage; - caps->dc_level_percentage = custom_backlight_profiles[config_no].dc_level_percentage; - caps->min_input_signal = custom_backlight_profiles[config_no].min_input_signal; - caps->max_input_signal = custom_backlight_profiles[config_no].max_input_signal; - caps->num_data_points = (uint8_t)custom_backlight_profiles[config_no].num_data_points; - memcpy(caps->data_points, custom_backlight_profiles[config_no].data_points, data_points_size); - return true; -} - void reset_replay_dsync_error_count(struct dc_link *link) { link->replay_settings.replay_desync_error_fail_count = 0; diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h index 87d31d9dce5a..94d2521355ce 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h @@ -28,6 +28,7 @@ #include "dc/inc/hw/dmcu.h" #include "dc/inc/hw/abm.h" #include "dc/inc/core_types.h" +#include "mod_power.h" struct resource_pool; From 17d0aeff8b72289e5e438ba1a2bb542cc780dddc Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Wed, 29 Apr 2026 19:05:20 -0400 Subject: [PATCH 44/71] drm/amd/display: Add additional IPS entry/exit for PSR/Replay [Why] Multiple paths issue DMUB commands without managing IPS state, causing dc_wake_and_execute_gpint/dmub_cmd to internally wake from IPS and reallow idle. This flips idle_allowed back to true while idle_optimizations_allowed remains false during in-flight commits, desynchronizing the two flags. Affected paths: - amdgpu_dm_psr_set_event() and amdgpu_dm_replay_set_event() calls from amdgpu_dm_handle_vrr_transition(), amdgpu_dm_commit_planes() and amdgpu_dm_mod_power_update_streams(), that are invoked on atomic commits. - debugfs psr_get(), psr_read_residency(), replay_get_state(), replay_set_residency() access hardware without holding dc_lock or disabling IPS. [How] - Explicitly exit IPS before PSR/Replay set_event w/ hw_programming, called within atomic commit. - Wrap debugfs PSR/Replay state getters and setters with IPS exit/entry + dc_lock. Reviewed-by: Sunpeng Li Signed-off-by: Ivan Lipski Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 + .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 77 +++++++++++++++++++ 2 files changed, 81 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index efb1ae1f66a0..ee10a9eb8713 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9941,6 +9941,7 @@ static void amdgpu_dm_handle_vrr_transition(struct amdgpu_display_manager *dm, __func__, new_state->base.crtc->base.id); scoped_guard(mutex, &dm->dc_lock) { + dc_exit_ips_for_hw_access(dm->dc); amdgpu_dm_psr_set_event(dm, new_state->stream, true, psr_event_vrr_transition, true); amdgpu_dm_replay_set_event(dm, new_state->stream, true, @@ -9956,6 +9957,7 @@ static void amdgpu_dm_handle_vrr_transition(struct amdgpu_display_manager *dm, __func__, new_state->base.crtc->base.id); scoped_guard(mutex, &dm->dc_lock) { + dc_exit_ips_for_hw_access(dm->dc); amdgpu_dm_psr_set_event(dm, new_state->stream, false, psr_event_vrr_transition, false); amdgpu_dm_replay_set_event(dm, new_state->stream, false, @@ -10257,6 +10259,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_commit *state, mutex_lock(&dm->dc_lock); acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns = timestamp_ns; + dc_exit_ips_for_hw_access(dm->dc); amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true, psr_event_hw_programming, true); mutex_unlock(&dm->dc_lock); @@ -10614,6 +10617,7 @@ static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_commit *state, */ if (old_crtc_state->active) { scoped_guard(mutex, &dm->dc_lock) { + dc_exit_ips_for_hw_access(dm->dc); amdgpu_dm_psr_set_event(dm, dm_old_crtc_state->stream, true, psr_event_hw_programming, true); amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 011ae1980f80..4b09a740f205 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3163,10 +3163,25 @@ static int replay_get_state(void *data, u64 *val) { struct amdgpu_dm_connector *connector = data; struct dc_link *link = connector->dc_link; + struct amdgpu_device *adev = drm_to_adev(connector->base.dev); + struct dc *dc = adev->dm.dc; uint64_t state = REPLAY_STATE_INVALID; + bool reallow_idle = false; + + mutex_lock(&adev->dm.dc_lock); + + if (dc->idle_optimizations_allowed) { + dc_allow_idle_optimizations(dc, false); + reallow_idle = true; + } dc_link_get_replay_state(link, &state); + if (reallow_idle) + dc_allow_idle_optimizations(dc, true); + + mutex_unlock(&adev->dm.dc_lock); + *val = state; return 0; @@ -3179,10 +3194,26 @@ static int replay_set_residency(void *data, u64 val) { struct amdgpu_dm_connector *connector = data; struct dc_link *link = connector->dc_link; + struct amdgpu_device *adev = drm_to_adev(connector->base.dev); + struct dc *dc = adev->dm.dc; bool is_start = (val != 0); u32 residency = 0; + bool reallow_idle = false; + + mutex_lock(&adev->dm.dc_lock); + + if (dc->idle_optimizations_allowed) { + dc_allow_idle_optimizations(dc, false); + reallow_idle = true; + } link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY); + + if (reallow_idle) + dc_allow_idle_optimizations(dc, true); + + mutex_unlock(&adev->dm.dc_lock); + return 0; } @@ -3193,9 +3224,25 @@ static int replay_get_residency(void *data, u64 *val) { struct amdgpu_dm_connector *connector = data; struct dc_link *link = connector->dc_link; + struct amdgpu_device *adev = drm_to_adev(connector->base.dev); + struct dc *dc = adev->dm.dc; u32 residency = 0; + bool reallow_idle = false; + + mutex_lock(&adev->dm.dc_lock); + + if (dc->idle_optimizations_allowed) { + dc_allow_idle_optimizations(dc, false); + reallow_idle = true; + } link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY); + + if (reallow_idle) + dc_allow_idle_optimizations(dc, true); + + mutex_unlock(&adev->dm.dc_lock); + *val = (u64)residency; return 0; @@ -3208,10 +3255,25 @@ static int psr_get(void *data, u64 *val) { struct amdgpu_dm_connector *connector = data; struct dc_link *link = connector->dc_link; + struct amdgpu_device *adev = drm_to_adev(connector->base.dev); + struct dc *dc = adev->dm.dc; enum dc_psr_state state = PSR_STATE0; + bool reallow_idle = false; + + mutex_lock(&adev->dm.dc_lock); + + if (dc->idle_optimizations_allowed) { + dc_allow_idle_optimizations(dc, false); + reallow_idle = true; + } dc_link_get_psr_state(link, &state); + if (reallow_idle) + dc_allow_idle_optimizations(dc, true); + + mutex_unlock(&adev->dm.dc_lock); + *val = state; return 0; @@ -3224,10 +3286,25 @@ static int psr_read_residency(void *data, u64 *val) { struct amdgpu_dm_connector *connector = data; struct dc_link *link = connector->dc_link; + struct amdgpu_device *adev = drm_to_adev(connector->base.dev); + struct dc *dc = adev->dm.dc; u32 residency = 0; + bool reallow_idle = false; + + mutex_lock(&adev->dm.dc_lock); + + if (dc->idle_optimizations_allowed) { + dc_allow_idle_optimizations(dc, false); + reallow_idle = true; + } link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY); + if (reallow_idle) + dc_allow_idle_optimizations(dc, true); + + mutex_unlock(&adev->dm.dc_lock); + *val = (u64)residency; return 0; From d359986a2e06684846ee3c2037405ef1fc130f2d Mon Sep 17 00:00:00 2001 From: Ivan Lipski Date: Wed, 29 Apr 2026 14:21:46 -0400 Subject: [PATCH 45/71] drm/amd/display: Enable IPS on DCN42 [Why & How] Fully enable IPS to achieve higher power savings. Reviewed-by: Sunpeng Li Signed-off-by: Ivan Lipski Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ee10a9eb8713..3ae2f330c6b4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1870,7 +1870,7 @@ static enum dmub_ips_disable_type dm_get_default_ips_mode( ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; break; case IP_VERSION(4, 2, 0): - ret = DMUB_IPS_DISABLE_ALL; + ret = DMUB_IPS_ENABLE; break; default: /* ASICs older than DCN35 do not have IPSs */ From e13d7181625d71c8e00360b68aba945e2f628693 Mon Sep 17 00:00:00 2001 From: Gaghik Khachatrian Date: Wed, 29 Apr 2026 22:59:42 -0400 Subject: [PATCH 46/71] drm/amd/display: Fix enum decl warnings [Why] warnings were triggered by enum forward declarations that are not valid in C++ without an explicit underlying type. [How] - Replace problematic enum forward declarations with C++-safe forms where applicable. - Use plain integer types for interface-only declarations that do not require strong enum typing. - Update dependent winterface signatures and related type usage consistently. - Add required include and type-visibility fixes to avoid follow-on parse and type-resolution issues. Reviewed-by: Aric Cyr Signed-off-by: Gaghik Khachatrian Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dm_helpers.h | 1 + .../amd/display/modules/inc/mod_color_types.h | 47 +++++++++++++++++++ .../amd/display/modules/inc/mod_info_packet.h | 9 +--- .../modules/inc/mod_info_packet_types.h | 37 +++++++++++++++ 4 files changed, 86 insertions(+), 8 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h create mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_info_packet_types.h diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index 107aec6a1265..63704d21a0b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -30,6 +30,7 @@ #ifndef __DM_HELPERS__ #define __DM_HELPERS__ +#include "modules/inc/mod_info_packet_types.h" #include "dc_types.h" #include "dc.h" diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h b/drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h new file mode 100644 index 000000000000..bf7313df585b --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_color_types.h @@ -0,0 +1,47 @@ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef MOD_COLOR_TYPES_H_ +#define MOD_COLOR_TYPES_H_ + +enum predefined_gamut_type { + gamut_type_bt709, + gamut_type_bt601, + gamut_type_adobe_rgb, + gamut_type_srgb, + gamut_type_bt2020, + gamut_type_dcip3, + gamut_type_unknown, +}; + +enum predefined_white_point_type { + white_point_type_5000k_horizon, + white_point_type_6500k_noon, + white_point_type_7500k_north_sky, + white_point_type_9300k, + white_point_type_unknown, +}; + +#endif /* MOD_COLOR_TYPES_H_ */ \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h index ddd64b7e4c04..11b127eb13d8 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h @@ -27,6 +27,7 @@ #define MOD_INFO_PACKET_H_ #include "dm_services.h" +#include "mod_info_packet_types.h" #include "mod_shared.h" //Forward Declarations struct dc_stream_state; @@ -47,14 +48,6 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream, void mod_build_hf_vsif_infopacket(const struct dc_stream_state *stream, struct dc_info_packet *info_packet); -enum adaptive_sync_type { - ADAPTIVE_SYNC_TYPE_NONE = 0, - ADAPTIVE_SYNC_TYPE_DP = 1, - FREESYNC_TYPE_PCON_IN_WHITELIST = 2, - FREESYNC_TYPE_PCON_NOT_IN_WHITELIST = 3, - ADAPTIVE_SYNC_TYPE_EDP = 4, -}; - enum adaptive_sync_sdp_version { AS_SDP_VER_0 = 0x0, AS_SDP_VER_1 = 0x1, diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet_types.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet_types.h new file mode 100644 index 000000000000..30a5259ef36b --- /dev/null +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet_types.h @@ -0,0 +1,37 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef MOD_INFO_PACKET_TYPES_H_ +#define MOD_INFO_PACKET_TYPES_H_ + +enum adaptive_sync_type { + ADAPTIVE_SYNC_TYPE_NONE = 0, + ADAPTIVE_SYNC_TYPE_DP = 1, + FREESYNC_TYPE_PCON_IN_WHITELIST = 2, + FREESYNC_TYPE_PCON_NOT_IN_WHITELIST = 3, + ADAPTIVE_SYNC_TYPE_EDP = 4, +}; + +#endif /* MOD_INFO_PACKET_TYPES_H_ */ From 58deba8c80a082f28c18a59fc9bb9614d04fe980 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 30 Apr 2026 17:24:38 -0400 Subject: [PATCH 47/71] drm/amd/display: enable ODM 2:1 on single eDP based on pixel clock [Why & How] this is to force ODM 2:1 on single eDP to lower dispclk/dppclk. Reviewed-by: Dillon Varone Signed-off-by: Charlene Liu Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../dc/resource/dcn42/dcn42_resource.c | 4 ++++ .../dc/resource/dcn42/dcn42_resource_fpu.c | 22 +++++++++++++++++++ .../dc/resource/dcn42/dcn42_resource_fpu.h | 2 +- 4 files changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e5933e3a8206..30ff7f1b9513 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1219,6 +1219,7 @@ struct dc_debug_options { unsigned int force_vmin_threshold; bool enable_otg_frame_sync_pwa; unsigned int min_deep_sleep_dcfclk_khz; + unsigned int force_odm2to1_for_edp_pixclk_mhz; }; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index 57c6e81280bc..01a7639da80b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -765,6 +765,7 @@ static const struct dc_debug_options debug_defaults_drv = { .min_deep_sleep_dcfclk_khz = 8000, .replay_skip_crtc_disabled = true, .psr_skip_crtc_disable = true, + .force_odm2to1_for_edp_pixclk_mhz = 550, // Force ODM 2to1 for eDP when pixel clock is above 550MHz }; static const struct dc_check_config config_defaults = { @@ -1721,9 +1722,12 @@ enum dc_status dcn42_validate_bandwidth(struct dc *dc, DC_FP_START(); + dcn42_decide_odm_override(dc, context); + out = dml2_validate(dc, context, context->bw_ctx.dml2, validate_mode); + if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) { /*not required for mode enumeration*/ dcn42_decide_zstate_support(dc, context); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c index 33b9775420d3..ee330559c233 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c @@ -45,3 +45,25 @@ void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context) context->bw_ctx.bw.dcn.clk.zstate_support = support; } + +bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context) +{ + bool odm_override = false; + + DC_LOGGER_INIT(dc->ctx->logger); + if (dc->ctx->dce_environment == DCE_ENV_DIAG) + return false; + + if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { + + if (dc->debug.force_odm2to1_for_edp_pixclk_mhz != 0 && + context->streams[0]->timing.pix_clk_100hz > dc->debug.force_odm2to1_for_edp_pixclk_mhz * 10000) { + odm_override = true; + context->streams[0]->debug.force_odm_combine_segments = 2; + } + DC_LOG_SMU("odm_override: %d, eDP pixelclock: %d, force_odm2to1_for_edp_pixclk_mhz: %d\n", + odm_override, context->streams[0]->timing.pix_clk_100hz / 10000, dc->debug.force_odm2to1_for_edp_pixclk_mhz); + } + return odm_override; +} + diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h index e32103220507..aff7be777681 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h @@ -29,5 +29,5 @@ #include "core_types.h" void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context); - +bool dcn42_decide_odm_override(struct dc *dc, struct dc_state *context); #endif /* _DCN42_RESOURCE_FPU_H_ */ From 018686f9fc13d716f5b2b587f2d8033f95c8991f Mon Sep 17 00:00:00 2001 From: Ovidiu Bunea Date: Fri, 1 May 2026 16:18:36 -0400 Subject: [PATCH 48/71] drm/amd/display: Revert "Unify fast update classification paths" [why & how] This change causes regressions in ACPI and display off/on testing. Revert the change to unblock testing. This reverts commit 5f6937c1afb151c85af721fad180d588060430d7. Reviewed-by: Aric Cyr Signed-off-by: Ovidiu Bunea Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 242 ++++++++++++++++-- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 12 - drivers/gpu/drm/amd/display/dc/dc.h | 34 ++- drivers/gpu/drm/amd/display/dc/dc_stream.h | 3 - .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 - 5 files changed, 252 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 4a601bf8c9d3..dc9b7959d548 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3011,8 +3011,7 @@ static struct surface_update_descriptor det_surface_update( update_flags->bits.gamut_remap_change || update_flags->bits.input_csc_change || update_flags->bits.cm_hist_change || - update_flags->bits.coeff_reduction_change || - update_flags->bits.cursor_csc_color_matrix_change)) { + update_flags->bits.coeff_reduction_change)) { elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } return overall_type; @@ -3102,10 +3101,8 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( stream_update->vrr_active_variable || stream_update->vrr_active_fixed)) su_flags->bits.fams_changed = 1; - if (stream_update->scaler_sharpener_update) { + if (stream_update->scaler_sharpener_update) su_flags->bits.scaler_sharpener = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM); - } if (stream_update->sharpening_required) su_flags->bits.sharpening_required = 1; @@ -3170,16 +3167,6 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( su_flags->bits.cursor_pos = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } - - if (stream_update->func_shaper) { - su_flags->bits.func_shaper = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM); - } - - if (stream_update->lut3d_func) { - su_flags->bits.lut3d_func = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM); - } } for (int i = 0 ; i < surface_count; i++) { @@ -4549,7 +4536,7 @@ static void build_dmub_update_dirty_rect( } } -bool dc_check_address_only_update(union surface_update_flags update_flags) +static bool check_address_only_update(union surface_update_flags update_flags) { union surface_update_flags addr_only_update_flags; addr_only_update_flags.raw = 0; @@ -4655,7 +4642,7 @@ static void commit_planes_for_stream_fast(struct dc *dc, for (i = 0; i < surface_count; i++) { if (srf_updates[i].surface && srf_updates[i].surface->update_flags.raw && - !dc_check_address_only_update(srf_updates[i].surface->update_flags)) { + !check_address_only_update(srf_updates[i].surface->update_flags)) { /* more than address update, need to acquire FAMS2 lock */ should_offload_fams2_flip = false; break; @@ -5623,6 +5610,127 @@ static bool commit_minimal_transition_state(struct dc *dc, return true; } +void populate_fast_updates(struct dc_fast_update *fast_update, + struct dc_surface_update *srf_updates, + int surface_count, + struct dc_stream_update *stream_update) +{ + int i = 0; + + if (stream_update) { + fast_update[0].out_transfer_func = stream_update->out_transfer_func; + fast_update[0].output_csc_transform = stream_update->output_csc_transform; + fast_update[0].cursor_attributes = stream_update->cursor_attributes; + fast_update[0].cursor_position = stream_update->cursor_position; + fast_update[0].periodic_interrupt = stream_update->periodic_interrupt; + fast_update[0].dither_option = stream_update->dither_option; + fast_update[0].gamut_remap = stream_update->gamut_remap; + fast_update[0].vrr_infopacket = stream_update->vrr_infopacket; + fast_update[0].vsc_infopacket = stream_update->vsc_infopacket; + fast_update[0].vsp_infopacket = stream_update->vsp_infopacket; + fast_update[0].hfvsif_infopacket = stream_update->hfvsif_infopacket; + fast_update[0].vtem_infopacket = stream_update->vtem_infopacket; + fast_update[0].adaptive_sync_infopacket = stream_update->adaptive_sync_infopacket; + fast_update[0].avi_infopacket = stream_update->avi_infopacket; + fast_update[0].hdr_static_metadata = stream_update->hdr_static_metadata; + } else { + fast_update[0].out_transfer_func = NULL; + fast_update[0].output_csc_transform = NULL; + fast_update[0].cursor_attributes = NULL; + fast_update[0].cursor_position = NULL; + fast_update[0].periodic_interrupt = NULL; + fast_update[0].dither_option = NULL; + fast_update[0].gamut_remap = NULL; + fast_update[0].vrr_infopacket = NULL; + fast_update[0].vsc_infopacket = NULL; + fast_update[0].vsp_infopacket = NULL; + fast_update[0].hfvsif_infopacket = NULL; + fast_update[0].vtem_infopacket = NULL; + fast_update[0].adaptive_sync_infopacket = NULL; + fast_update[0].avi_infopacket = NULL; + fast_update[0].hdr_static_metadata = NULL; + } + + for (i = 0; i < surface_count; i++) { + fast_update[i].flip_addr = srf_updates[i].flip_addr; + fast_update[i].gamma = srf_updates[i].gamma; + fast_update[i].gamut_remap_matrix = srf_updates[i].gamut_remap_matrix; + fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix; + fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor; + fast_update[i].cursor_csc_color_matrix = srf_updates[i].cursor_csc_color_matrix; + fast_update[i].cm_hist_control = srf_updates[i].cm_hist_control; + } +} + +static bool fast_updates_exist(const struct dc_fast_update *fast_update, int surface_count) +{ + int i; + + if (fast_update[0].out_transfer_func || + fast_update[0].output_csc_transform || + fast_update[0].cursor_attributes || + fast_update[0].cursor_position || + fast_update[0].periodic_interrupt || + fast_update[0].dither_option || + fast_update[0].gamut_remap || + fast_update[0].vrr_infopacket || + fast_update[0].vsc_infopacket || + fast_update[0].vsp_infopacket || + fast_update[0].hfvsif_infopacket || + fast_update[0].vtem_infopacket || + fast_update[0].adaptive_sync_infopacket || + fast_update[0].avi_infopacket || + fast_update[0].hdr_static_metadata) + return true; + + for (i = 0; i < surface_count; i++) { + if (fast_update[i].flip_addr || + fast_update[i].gamma || + fast_update[i].gamut_remap_matrix || + fast_update[i].input_csc_color_matrix || + fast_update[i].cursor_csc_color_matrix || + fast_update[i].cm_hist_control || + fast_update[i].coeff_reduction_factor) + return true; + } + + return false; +} + +bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count) +{ + int i; + + if (fast_update[0].out_transfer_func || + fast_update[0].output_csc_transform || + fast_update[0].gamut_remap || + fast_update[0].cursor_attributes || + fast_update[0].cursor_position || + fast_update[0].periodic_interrupt || + fast_update[0].dither_option || + fast_update[0].vrr_infopacket || + fast_update[0].vsc_infopacket || + fast_update[0].vsp_infopacket || + fast_update[0].hfvsif_infopacket || + fast_update[0].vtem_infopacket || + fast_update[0].adaptive_sync_infopacket || + fast_update[0].avi_infopacket || + fast_update[0].hdr_static_metadata) + return true; + + for (i = 0; i < surface_count; i++) { + if (fast_update[i].input_csc_color_matrix || + fast_update[i].gamma || + fast_update[i].gamut_remap_matrix || + fast_update[i].coeff_reduction_factor || + fast_update[i].cm_hist_control || + fast_update[i].cursor_csc_color_matrix) + return true; + } + + return false; +} + static bool full_update_required_weak( const struct dc *dc, const struct dc_surface_update *srf_updates, @@ -5651,6 +5759,72 @@ static bool full_update_required_weak( return false; } +static bool full_update_required( + const struct dc *dc, + const struct dc_surface_update *srf_updates, + int surface_count, + const struct dc_stream_update *stream_update, + const struct dc_stream_state *stream) +{ + if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) + return true; + + for (int i = 0; i < surface_count; i++) { + if (srf_updates && + (srf_updates[i].plane_info || + srf_updates[i].scaling_info || + (srf_updates[i].hdr_mult.value && + srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) || + (srf_updates[i].sdr_white_level_nits && + srf_updates[i].sdr_white_level_nits != srf_updates->surface->sdr_white_level_nits) || + srf_updates[i].in_transfer_func || + srf_updates[i].func_shaper || + srf_updates[i].lut3d_func || + srf_updates[i].surface->force_full_update || + (srf_updates[i].flip_addr && + srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface) || + (srf_updates[i].cm2_params && + (srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting != srf_updates[i].surface->mcm_shaper_3dlut_setting || + srf_updates[i].cm2_params->component_settings.lut1d_enable != srf_updates[i].surface->mcm_lut1d_enable)))) + return true; + } + + if (stream_update && + (((stream_update->src.height != 0 && stream_update->src.width != 0) || + (stream_update->dst.height != 0 && stream_update->dst.width != 0) || + stream_update->integer_scaling_update) || + stream_update->abm_level || + stream_update->dpms_off || + stream_update->allow_freesync || + stream_update->vrr_active_variable || + stream_update->vrr_active_fixed || + stream_update->output_color_space || + stream_update->wb_update || + stream_update->dsc_config || + stream_update->mst_bw_update || + stream_update->func_shaper || + stream_update->lut3d_func || + stream_update->pending_test_pattern || + stream_update->crtc_timing_adjust || + stream_update->scaler_sharpener_update || + stream_update->hw_cursor_req)) + return true; + + return false; +} + +static bool fast_update_only( + const struct dc *dc, + const struct dc_fast_update *fast_update, + const struct dc_surface_update *srf_updates, + int surface_count, + const struct dc_stream_update *stream_update, + const struct dc_stream_state *stream) +{ + return fast_updates_exist(fast_update, surface_count) + && !full_update_required(dc, srf_updates, surface_count, stream_update, stream); +} + static bool update_planes_and_stream_v2(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_state *stream, @@ -5658,6 +5832,7 @@ static bool update_planes_and_stream_v2(struct dc *dc, { struct dc_state *context; enum surface_update_type update_type; + struct dc_fast_update fast_update[MAX_SURFACES] = {0}; /* In cases where MPO and split or ODM are used transitions can * cause underflow. Apply stream configuration with minimal pipe @@ -5665,7 +5840,11 @@ static bool update_planes_and_stream_v2(struct dc *dc, */ bool force_minimal_pipe_splitting = 0; bool is_plane_addition = 0; + bool is_fast_update_only; + populate_fast_updates(fast_update, srf_updates, surface_count, stream_update); + is_fast_update_only = fast_update_only(dc, fast_update, srf_updates, + surface_count, stream_update, stream); force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes( dc, stream, @@ -5703,7 +5882,7 @@ static bool update_planes_and_stream_v2(struct dc *dc, commit_minimal_transition_state_in_dc_update(dc, context, stream, srf_updates, surface_count); - if (update_type == UPDATE_TYPE_FAST && !dc->check_config.enable_legacy_fast_update) { + if (is_fast_update_only && !dc->check_config.enable_legacy_fast_update) { commit_planes_for_stream_fast(dc, srf_updates, surface_count, @@ -5739,8 +5918,13 @@ static void commit_planes_and_stream_update_on_current_context(struct dc *dc, struct dc_stream_update *stream_update, enum surface_update_type update_type) { + struct dc_fast_update fast_update[MAX_SURFACES] = {0}; + ASSERT(update_type < UPDATE_TYPE_FULL); - if (update_type == UPDATE_TYPE_FAST && + populate_fast_updates(fast_update, srf_updates, surface_count, + stream_update); + if (fast_update_only(dc, fast_update, srf_updates, surface_count, + stream_update, stream) && !dc->check_config.enable_legacy_fast_update) commit_planes_for_stream_fast(dc, srf_updates, @@ -7743,6 +7927,23 @@ static bool update_planes_and_stream_prepare_v3( ASSERT(scratch->flow == UPDATE_V3_FLOW_INVALID); dc_exit_ips_for_hw_access(scratch->dc); + /* HWSS path determination needs to be done prior to updating the surface and stream states. */ + struct dc_fast_update fast_update[MAX_SURFACES] = { 0 }; + + populate_fast_updates(fast_update, + scratch->surface_updates, + scratch->surface_count, + scratch->stream_update); + + const bool is_hwss_fast_path_only = + fast_update_only(scratch->dc, + fast_update, + scratch->surface_updates, + scratch->surface_count, + scratch->stream_update, + scratch->stream) && + !scratch->dc->check_config.enable_legacy_fast_update; + if (!update_planes_and_stream_state( scratch->dc, scratch->surface_updates, @@ -7758,8 +7959,7 @@ static bool update_planes_and_stream_prepare_v3( if (scratch->new_context == scratch->dc->current_state) { ASSERT(scratch->update_type < UPDATE_TYPE_FULL); - scratch->flow = (scratch->update_type == UPDATE_TYPE_FAST && - !scratch->dc->check_config.enable_legacy_fast_update) + scratch->flow = is_hwss_fast_path_only ? UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST : UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL; return true; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index ffa3130853c2..1916aa3ebaea 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1057,18 +1057,6 @@ void hwss_build_fast_sequence(struct dc *dc, (*num_steps)++; } - if (current_mpc_pipe->plane_state->update_flags.bits.lut_3d && - current_mpc_pipe->plane_state->mcm_luts.lut3d_data.lut3d_src == - DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM && - current_mpc_pipe->plane_state->mcm_shaper_3dlut_setting == - DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT && - current_mpc_pipe->plane_res.hubp->funcs->hubp_enable_3dlut_fl) { - block_sequence[*num_steps].params.hubp_enable_3dlut_fl_params.hubp = - current_mpc_pipe->plane_res.hubp; - block_sequence[*num_steps].func = HUBP_ENABLE_3DLUT_FL; - (*num_steps)++; - } - if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) { block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc; block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 30ff7f1b9513..d87bf8f4f56e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1467,14 +1467,11 @@ union surface_update_flags { uint32_t full_update:1; uint32_t sdr_white_level_nits:1; uint32_t cm_hist_change:1; - uint32_t reserved:2; /* adjust when adding new flags */ } bits; uint32_t raw; }; -bool dc_check_address_only_update(union surface_update_flags update_flags); - #define DC_REMOVE_PLANE_POINTERS 1 struct dc_plane_state { @@ -1854,6 +1851,32 @@ struct dc_scaling_info { struct scaling_taps scaling_quality; }; +struct dc_fast_update { + const struct dc_flip_addrs *flip_addr; + const struct dc_gamma *gamma; + const struct colorspace_transform *gamut_remap_matrix; + const struct dc_csc_transform *input_csc_color_matrix; + const struct fixed31_32 *coeff_reduction_factor; + struct dc_transfer_func *out_transfer_func; + struct dc_csc_transform *output_csc_transform; + const struct dc_csc_transform *cursor_csc_color_matrix; + struct cm_hist_control *cm_hist_control; + /* stream-level fast updates */ + const struct colorspace_transform *gamut_remap; + const struct dc_cursor_attributes *cursor_attributes; + const struct dc_cursor_position *cursor_position; + const struct periodic_interrupt_config *periodic_interrupt; + const enum dc_dither_option *dither_option; + struct dc_info_packet *vrr_infopacket; + struct dc_info_packet *vsc_infopacket; + struct dc_info_packet *vsp_infopacket; + struct dc_info_packet *hfvsif_infopacket; + struct dc_info_packet *vtem_infopacket; + struct dc_info_packet *adaptive_sync_infopacket; + struct dc_info_packet *avi_infopacket; + struct dc_info_packet *hdr_static_metadata; +}; + struct dc_surface_update { struct dc_plane_state *surface; @@ -1988,6 +2011,11 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); void get_audio_check(struct audio_info *aud_modes, struct audio_check *aud_chk); +bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); +void populate_fast_updates(struct dc_fast_update *fast_update, + struct dc_surface_update *srf_updates, + int surface_count, + struct dc_stream_update *stream_update); /* * Set up streams and links associated to drive sinks * The streams parameter is an absolute set of all active streams. diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 1649fbab08aa..4154cd059562 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -123,9 +123,6 @@ union stream_update_flags { uint32_t info_frame : 1; uint32_t dmdata : 1; uint32_t dither : 1; - uint32_t func_shaper : 1; - uint32_t lut3d_func : 1; - uint32_t reserved : 11; /* adjust when adding new flags */ } bits; uint32_t raw; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index c6ec58367678..c6b62870c46e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -493,12 +493,10 @@ void dcn401_populate_mcm_luts(struct dc *dc, break; case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: switch (mcm_luts.lut3d_data.gpu_mem_params.size) { -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) case DC_CM2_GPU_MEM_SIZE_333333: if (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33) width = hubp_3dlut_fl_width_33; break; -#endif case DC_CM2_GPU_MEM_SIZE_171717: width = hubp_3dlut_fl_width_17; break; From 4a333c8d9b70f42834614fd815a13e0f4f968f8a Mon Sep 17 00:00:00 2001 From: Leo Chen Date: Fri, 1 May 2026 14:34:02 -0400 Subject: [PATCH 49/71] drm/amd/display: Revert "Enable HUBP/OPTC/DPP power gating" [why & how] Pipe power gating is causing regressions. Revert to unblock testing and promotion This reverts commit 2eb0681ea7604880ade2d715e4212132c393c132. Reviewed-by: Ovidiu Bunea Signed-off-by: Leo Chen Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c index 01a7639da80b..52a1996a654f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -694,9 +694,9 @@ static const struct dc_debug_options debug_defaults_drv = { .clock_trace = true, .disable_pplib_clock_request = false, .ignore_pg = false, - .disable_dpp_power_gate = false, - .disable_hubp_power_gate = false, - .disable_optc_power_gate = false, + .disable_dpp_power_gate = true, + .disable_hubp_power_gate = true, + .disable_optc_power_gate = true, .disable_dsc_power_gate = false, .disable_dio_power_gate = true, .disable_hpo_power_gate = true, From 885ccbef7b94a8b38f69c4211c679021aa27ad11 Mon Sep 17 00:00:00 2001 From: Mikhail Gavrilov Date: Tue, 5 May 2026 09:05:37 +0800 Subject: [PATCH 50/71] drm/amd/display: Wrap DCN32 phantom-plane allocation in DC_RUN_WITH_PREEMPTION_ENABLED [Why] dcn32_validate_bandwidth() wraps dcn32_internal_validate_bw() with DC_FP_START()/DC_FP_END(). In x86 non-RT, DC_FP_START takes fpregs_lock(), which disables local softirqs. The DML1 path through dcn32_enable_phantom_plane() calls kvzalloc() to allocate ~335 KiB for dc_plane_state. This triggers the vmalloc path, which calls BUG_ON(in_interrupt()) because it's invoked within the FPU-enabled (softirq disabled) region, leading to a kernel crash. [How] Wrap the dc_state_create_phantom_plane() call with the DC_RUN_WITH_PREEMPTION_ENABLED() macro to allow preemption during this memory allocation. Fixes: 235c67634230 ("drm/amd/display: add DCN32/321 specific files for Display Core") Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/4470 Reviewed-by: Aurabindo Pillai Signed-off-by: Mikhail Gavrilov Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index bc9523f55eb1..a6985742c950 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -92,9 +92,14 @@ #include "dml/dcn32/dcn32_fpu.h" #include "dc_state_priv.h" +#include "dc_fpu.h" #include "dml2_0/dml2_wrapper.h" +#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) +#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code +#endif + #define DC_LOGGER_INIT(logger) enum dcn32_clk_src_array_id { @@ -1684,7 +1689,8 @@ static void dcn32_enable_phantom_plane(struct dc *dc, if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state) phantom_plane = prev_phantom_plane; else - phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state); + DC_RUN_WITH_PREEMPTION_ENABLED(phantom_plane = + dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state)); if (!phantom_plane) continue; From 458673922368858b8af4c774a8e3d972fd3210e0 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Fri, 1 May 2026 19:19:13 -0400 Subject: [PATCH 51/71] drm/amd/display: [FW Promotion] Release 0.1.59.0 [Why & How] Update DMUB related command structure. Acked-by: Tom Chung Signed-off-by: Taimur Hassan Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 32 +++++++++++-------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 300bbfe3c98d..c1becd664cb9 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -2378,24 +2378,24 @@ struct dmub_cmd_lsdma_data { uint32_t dst_mip_max : 5; uint32_t dst_swizzle_mode : 5; uint32_t dst_mip_id : 5; - uint32_t tmz : 1; uint32_t dcc : 1; + uint32_t padding1 : 1; uint32_t data_format : 6; - uint32_t padding1 : 4; + uint32_t tmz : 4; uint32_t dst_element_size : 3; uint32_t num_type : 3; uint32_t src_element_size : 3; uint32_t write_compress : 2; - uint32_t cache_policy_dst : 2; - uint32_t cache_policy_src : 2; + uint32_t cache_policy_dst : 3; + uint32_t cache_policy_src : 3; uint32_t read_compress : 2; - uint32_t src_dim : 2; - uint32_t dst_dim : 2; + uint32_t max_com : 2; uint32_t max_uncom : 1; - uint32_t max_com : 2; - uint32_t padding : 30; + uint32_t dst_dim : 2; + uint32_t src_dim : 2; + uint32_t padding : 28; } tiled_copy_data; struct lsdma_linear_copy_data { uint32_t src_lo; @@ -2405,11 +2405,13 @@ struct dmub_cmd_lsdma_data { uint32_t dst_hi; uint32_t count : 30; - uint32_t cache_policy_dst : 2; + uint32_t pad0 : 2; - uint32_t tmz : 1; - uint32_t cache_policy_src : 2; - uint32_t padding : 29; + uint32_t tmz : 4; + uint32_t cache_policy_src : 3; + uint32_t cache_policy_dst : 3; + uint32_t pad1 : 22; + // DCC fields not included because linear mode on display does not support DCC } linear_copy_data; struct lsdma_linear_sub_window_copy_data { uint32_t src_lo; @@ -2433,11 +2435,13 @@ struct dmub_cmd_lsdma_data { uint32_t src_slice_pitch; uint32_t dst_slice_pitch; - uint32_t tmz : 1; + uint32_t tmz : 4; uint32_t element_size : 3; uint32_t src_cache_policy : 3; uint32_t dst_cache_policy : 3; - uint32_t reserved0 : 22; + uint32_t reserved0 : 19; + // Linear mode on display does not support compression so DCC related fields are not included. + // The DCC fields in the command packet will be zero'd at the time of constructing the packet. } linear_sub_window_copy_data; struct lsdma_reg_write_data { uint32_t reg_addr; From 1bd506e812332b30b6902c0563106731ba8664e4 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Sat, 2 May 2026 04:39:37 -0500 Subject: [PATCH 52/71] drm/amd/display: Promote DC to 3.2.382 This version brings along following update: -Revert "Enable HUBP/OPTC/DPP power gating" -Revert "Unify fast update classification paths" -enable ODM 2:1 on single eDP based on pixel clock -Enable IPS on DCN42 -Add additional IPS entry/exit for PSR/Replay -Separate ABM functions into dedicated power_abm.c file -Fix always-true lower-bound assert -Refactor dc_link_aux_transfer_raw -only call pmfw if smu present flags true -Fix multiple compiler warnings -Fix CRC open failure during active rendering -Fix white screen on boot with OLED panel -Fix refresh rate round up case Acked-by: Tom Chung Signed-off-by: Taimur Hassan Signed-off-by: James Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d87bf8f4f56e..d0b6fad65bc0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.381" +#define DC_VER "3.2.382" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC From d69051b4549f3fe0ee5cb11f0c2c78eb51f7b6f8 Mon Sep 17 00:00:00 2001 From: chong li Date: Wed, 6 May 2026 17:20:55 +0800 Subject: [PATCH 53/71] drm/amdgpu: Sync the pf2vf structure between guest and host There are gaps in the pf2vf message structure between the guest driver and the host driver. The pf2vf message info structure must be kept in sync between both sides to ensure correct interpretation of fields. Signed-off-by: chong li Reviewed-by: Emily Deng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 13 +++++++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 9da0c6e9b869..d563deec0916 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -163,6 +163,8 @@ enum AMDGIM_FEATURE_FLAG { AMDGIM_FEATURE_RAS_CPER = (1 << 11), AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 << 12), AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU = (1 << 13), + AMDGIM_FEATURE_PTL_SUPPORT = (1 << 14), + AMDGIM_FEATURE_UNITID_SUPPORT = (1 << 15), }; enum AMDGIM_REG_ACCESS_FLAG { @@ -441,6 +443,8 @@ static inline bool is_virtual_machine(void) ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE) #define amdgpu_sriov_is_mes_info_enable(adev) \ ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE) +#define amdgpu_sriov_is_unitid_support(adev) \ + ((adev)->virt.gim_feature & AMDGIM_FEATURE_UNITID_SUPPORT) #define amdgpu_virt_xgmi_migrate_enabled(adev) \ ((adev)->virt.is_xgmi_node_migrate_enabled && (adev)->gmc.xgmi.node_segment_size != 0) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index 847cfd1fd004..9dcf0b07d513 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -162,7 +162,9 @@ union amd_sriov_msg_feature_flags { uint32_t ras_cper : 1; uint32_t xgmi_ta_ext_peer_link : 1; uint32_t xgmi_connected_to_cpu : 1; - uint32_t reserved : 18; + uint32_t ptl_support : 1; + uint32_t unitid_support : 1; + uint32_t reserved : 16; } flags; uint32_t all; }; @@ -256,7 +258,7 @@ struct amd_sriov_msg_pf2vf_info_header { uint32_t reserved[2]; }; -#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (55) +#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (59) struct amd_sriov_msg_pf2vf_info { /* header contains size and version */ struct amd_sriov_msg_pf2vf_info_header header; @@ -314,6 +316,13 @@ struct amd_sriov_msg_pf2vf_info { uint32_t more_bp; //Reserved for future use. union amd_sriov_ras_caps ras_en_caps; union amd_sriov_ras_caps ras_telemetry_en_caps; + /* PTL status response for guest */ + uint32_t ptl_enabled; // PTL enable status: 0=disabled, 1=enabled + uint32_t ptl_pref_format1; // Current preferred format 1 + uint32_t ptl_pref_format2; // Current preferred format 2 + /* unit ID assigned by host; vf_idx [0..254] maps to unitid [1..255] (0 = pf) */ + uint8_t unitid; + uint8_t padding[3]; //use the 3 bytes to align /* reserved */ uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE]; From 1e40ef87ffdc291e05ccdade8b9170cc9c1c4249 Mon Sep 17 00:00:00 2001 From: Xiang Liu Date: Thu, 7 May 2026 20:56:15 +0800 Subject: [PATCH 54/71] drm/amd/ras: Fix CPER ring debugfs read overflow The legacy CPER debugfs reader can reach the payload path without a valid pointer snapshot. The remaining user byte count is also treated as the ring occupancy in dwords, so reads past the header can copy more than requested. Take the CPER lock before sampling pointers. Resample rptr/wptr for payload reads, bound the payload copy by available dwords and the remaining user size, and advance the file position for each dword copied. Signed-off-by: Xiang Liu Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 29 +++++++++++++++++------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 66e8a2f7afcf..d6bee5c30073 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -552,8 +552,9 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { struct amdgpu_ring *ring = file_inode(f)->i_private; - uint32_t value, result, early[3]; + u32 value, result, early[3] = { 0 }; uint64_t p; + u32 avail_dw, start_dw, read_dw; loff_t i; int r; @@ -565,10 +566,10 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, result = 0; - if (*pos < 12) { - if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) - mutex_lock(&ring->adev->cper.ring_lock); + if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) + mutex_lock(&ring->adev->cper.ring_lock); + if (*pos < 12) { early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; early[2] = ring->wptr & ring->buf_mask; @@ -600,13 +601,24 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, *pos += 4; } } else { + early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; + early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; + p = early[0]; if (early[0] <= early[1]) - size = (early[1] - early[0]); + avail_dw = early[1] - early[0]; else - size = ring->ring_size - (early[0] - early[1]); + avail_dw = ring->buf_mask + 1 - (early[0] - early[1]); - while (size) { + start_dw = (*pos > 12) ? ((*pos - 12) >> 2) : 0; + if (start_dw >= avail_dw) + goto out; + + p = (p + start_dw) & ring->ptr_mask; + avail_dw -= start_dw; + read_dw = min_t(u32, avail_dw, size >> 2); + + while (read_dw) { if (p == early[1]) goto out; @@ -619,9 +631,10 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, buf += 4; result += 4; - size--; + read_dw--; p++; p &= ring->ptr_mask; + *pos += 4; } } From 4305b6e9705d1500fe7186aa27e764dc5d7b7871 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Tue, 16 May 2023 18:40:20 -0600 Subject: [PATCH 55/71] drm/amd/display: Add FRL registers for DCN30 Introduce the stream creation function, which requires the FRL registers for DCN30. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../include/asic_reg/dcn/dcn_3_0_0_offset.h | 129 ++++ .../include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 600 ++++++++++++++++++ 2 files changed, 729 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h index f32649047374..904518791b62 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h @@ -15871,6 +15871,113 @@ #define mmDC_PERFMON28_PERFMON_LOW 0x08cf #define mmDC_PERFMON28_PERFMON_LOW_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL 0x08d4 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL 0x08d4 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define mmHDMI_TB_ENC_CONTROL 0x08df +#define mmHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define mmHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define mmHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define mmHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define mmHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define mmHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define mmHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_32_0 0x08f2 +#define mmHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_32_1 0x08f3 +#define mmHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_44_0 0x08f4 +#define mmHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_44_1 0x08f5 +#define mmHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_48_0 0x08f6 +#define mmHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_48_1 0x08f7 +#define mmHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define mmHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define mmHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define mmHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_MEM_CTRL 0x08fe +#define mmHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define mmHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_CNTL 0x0903 +#define mmHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define mmHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_MODE 0x0908 +#define mmHDMI_TB_ENC_MODE_BASE_IDX 3 +#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define mmHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + // base address: 0x2646c #define mmAFMT6_AFMT_VBI_PACKET_CONTROL 0x091c #define mmAFMT6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 @@ -15934,6 +16041,28 @@ #define mmVPG6_VPG_MPEG_INFO1 0x093a #define mmVPG6_VPG_MPEG_INFO1_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define mmHDMI_LINK_ENC_CONTROL 0x095b +#define mmHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define mmHDMI_LINK_ENC_CLK_CTRL 0x095c +#define mmHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define mmHDMI_FRL_ENC_CONFIG 0x0965 +#define mmHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define mmHDMI_FRL_ENC_CONFIG2 0x0966 +#define mmHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define mmHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define mmHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +// base address: 0x0 +#define mmHPO_TOP_CLOCK_CONTROL 0x0e43 +#define mmHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 // base address: 0x264f0 #define mmDME6_DME_CONTROL 0x093c diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h index 4005c73c2c9f..92c3ba54effa 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h @@ -60370,6 +60370,496 @@ #define DC_PERFMON28_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 #define DC_PERFMON28_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_INCREMENT__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_MODULO__SHIFT 0x8 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_INCREMENT_MASK 0x000000FFL +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_MODULO_MASK 0x0000FF00L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + + //AFMT6_AFMT_VBI_PACKET_CONTROL #define AFMT6_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 #define AFMT6_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 @@ -60736,10 +61226,120 @@ #define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L #define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_hdcp2_hdcp2_dispdec +//HDCP2_6_HDCP2_CONTROL +#define HDCP2_6_HDCP2_CONTROL__HDCP2_RESET__SHIFT 0x4 +#define HDCP2_6_HDCP2_CONTROL__HDCP2_TYPE__SHIFT 0x8 +#define HDCP2_6_HDCP2_CONTROL__HDCP2_EESS_WHEN_AVMUTE__SHIFT 0x10 +#define HDCP2_6_HDCP2_CONTROL__HDCP2_ESS_ENABLE__SHIFT 0x14 +#define HDCP2_6_HDCP2_CONTROL__HDCP2_ESS_TYPE__SHIFT 0x18 +#define HDCP2_6_HDCP2_CONTROL__HDCP2_RESET_MASK 0x00000010L +#define HDCP2_6_HDCP2_CONTROL__HDCP2_TYPE_MASK 0x00000300L +#define HDCP2_6_HDCP2_CONTROL__HDCP2_EESS_WHEN_AVMUTE_MASK 0x00010000L +#define HDCP2_6_HDCP2_CONTROL__HDCP2_ESS_ENABLE_MASK 0x00100000L +#define HDCP2_6_HDCP2_CONTROL__HDCP2_ESS_TYPE_MASK 0x01000000L +//HDCP2_6_HDCP2_ENABLE_DELAY +#define HDCP2_6_HDCP2_ENABLE_DELAY__HDCP2_ENABLE_DELAY__SHIFT 0x0 +#define HDCP2_6_HDCP2_ENABLE_DELAY__HDCP2_ENABLE_DELAY_MASK 0x000003FFL +//HDCP2_6_HDCP2_RIV0 +#define HDCP2_6_HDCP2_RIV0__HDCP2_RIV0__SHIFT 0x0 +#define HDCP2_6_HDCP2_RIV0__HDCP2_RIV0_MASK 0xFFFFFFFFL +//HDCP2_6_HDCP2_RIV1 +#define HDCP2_6_HDCP2_RIV1__HDCP2_RIV1__SHIFT 0x0 +#define HDCP2_6_HDCP2_RIV1__HDCP2_RIV1_MASK 0xFFFFFFFFL +//HDCP2_6_HDCP2_KS_XOR_LC128_0 +#define HDCP2_6_HDCP2_KS_XOR_LC128_0__HDCP2_KS_XOR_LC128_0__SHIFT 0x0 +#define HDCP2_6_HDCP2_KS_XOR_LC128_0__HDCP2_KS_XOR_LC128_0_MASK 0xFFFFFFFFL +//HDCP2_6_HDCP2_KS_XOR_LC128_1 +#define HDCP2_6_HDCP2_KS_XOR_LC128_1__HDCP2_KS_XOR_LC128_1__SHIFT 0x0 +#define HDCP2_6_HDCP2_KS_XOR_LC128_1__HDCP2_KS_XOR_LC128_1_MASK 0xFFFFFFFFL +//HDCP2_6_HDCP2_KS_XOR_LC128_2 +#define HDCP2_6_HDCP2_KS_XOR_LC128_2__HDCP2_KS_XOR_LC128_2__SHIFT 0x0 +#define HDCP2_6_HDCP2_KS_XOR_LC128_2__HDCP2_KS_XOR_LC128_2_MASK 0xFFFFFFFFL +//HDCP2_6_HDCP2_KS_XOR_LC128_3 +#define HDCP2_6_HDCP2_KS_XOR_LC128_3__HDCP2_KS_XOR_LC128_3__SHIFT 0x0 +#define HDCP2_6_HDCP2_KS_XOR_LC128_3__HDCP2_KS_XOR_LC128_3_MASK 0xFFFFFFFFL + +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + // addressBlock: dce_dc_hpo_hpo_top_dispdec //HPO_TOP_CLOCK_CONTROL +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT 0x1 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT 0x4 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT 0x5 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT 0x8 #define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS__SHIFT 0x9 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT 0xc +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS__SHIFT 0xd +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT 0x10 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK 0x00000002L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK 0x00000010L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK 0x00000020L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK 0x00000100L #define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS_MASK 0x00000200L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK 0x00001000L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS_MASK 0x00002000L +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK 0x003F0000L // addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec //DC_PERFMON29_PERFCOUNTER_CNTL From 5dfcaecc7e1f7cd54134b093993aa3449e79afae Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Thu, 18 May 2023 13:49:27 -0600 Subject: [PATCH 56/71] drm/amd/display: Add required FRL registers for DCN31 This commit introduces multiple hardware registers necessary to enable FRL on AMD devices. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../include/asic_reg/dcn/dcn_3_1_2_offset.h | 109 ++++ .../include/asic_reg/dcn/dcn_3_1_2_sh_mask.h | 548 ++++++++++++++++++ 2 files changed, 657 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h index 7fd906f10803..ad8c2dd480f2 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h @@ -12907,9 +12907,41 @@ #define regDC_PERFMON22_PERFMON_LOW 0x0e6e #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c +#define regAFMT5_AFMT_ACP 0x091b +#define regAFMT5_AFMT_ACP_BASE_IDX 3 #define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c #define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d @@ -12981,6 +13013,83 @@ #define regVPG5_VPG_MPEG_INFO1 0x093a #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec // base address: 0x1ab8c diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h index 07fbfafe6056..9c570d781c52 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h @@ -48391,6 +48391,124 @@ #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec //AFMT5_AFMT_VBI_PACKET_CONTROL @@ -48765,6 +48883,436 @@ #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_DEBUG_DATA +#define HDMI_TB_ENC_DEBUG_DATA__HDMI_DEBUG_DATA__SHIFT 0x0 +#define HDMI_TB_ENC_DEBUG_DATA__HDMI_DEBUG_DATA_MASK 0xFFFFFFFFL +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec //DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL From 5bad9d8a1e70667be030dceb06257f472407777a Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Thu, 18 May 2023 18:24:02 -0600 Subject: [PATCH 57/71] drm/amd/display: Add FRL registers for DCN321 Add the required DCN3.2.1 registers to enable FRL in this ASIC. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../include/asic_reg/dcn/dcn_3_2_1_offset.h | 124 +++- .../include/asic_reg/dcn/dcn_3_2_1_sh_mask.h | 548 ++++++++++++++++++ 2 files changed, 671 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h index a04b8c32c564..20deafe52a07 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h @@ -11814,7 +11814,6 @@ #define regDSCC0_DSCC_TEST_DEBUG_DATA0 0x303b #define regDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 - // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec // base address: 0x0 #define regDSCCIF0_DSCCIF_CONFIG0 0x3005 @@ -12173,6 +12172,19 @@ #define regHPO_TOP_HW_CONTROL 0x0e4a #define regHPO_TOP_HW_CONTROL_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + // addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec // base address: 0x27958 @@ -12185,6 +12197,39 @@ #define regDP_STREAM_MAPPER_CONTROL3 0x0e59 #define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c @@ -12259,6 +12304,83 @@ #define regVPG5_VPG_MPEG_INFO1 0x093a #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec // base address: 0x1ab8c diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h index ce773fca621f..c22929134196 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h @@ -43576,6 +43576,125 @@ #define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT 0x0 #define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK 0x00000007L +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec //AFMT5_AFMT_VBI_PACKET_CONTROL @@ -43952,6 +44071,435 @@ #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec //DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL From 332b9fe92cdd1251a94c560870dad96ee319b368 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Thu, 18 May 2023 14:43:39 -0600 Subject: [PATCH 58/71] drm/amd/display: Introduce FRL registers for DCN32 This commit add the basic set of FRL registers associated with DCN32. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../include/asic_reg/dcn/dcn_3_2_0_offset.h | 109 ++++ .../include/asic_reg/dcn/dcn_3_2_0_sh_mask.h | 544 ++++++++++++++++++ 2 files changed, 653 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h index 78cb61d5800a..bc4524f9b462 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_offset.h @@ -12201,6 +12201,38 @@ #define regDP_STREAM_MAPPER_CONTROL3 0x0e59 #define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 +// addressBlock: dcn_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + + +// addressBlock: dcn_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + + +// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 // addressBlock: dcn_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c @@ -12275,6 +12307,83 @@ #define regVPG5_VPG_MPEG_INFO1 0x093a #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 +// addressBlock: dcn_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + // addressBlock: dcn_dc_hpo_dp_stream_enc0_dispdec // base address: 0x1ab8c diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h index c20bf730dc55..a89fe19c4c84 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_0_sh_mask.h @@ -43567,6 +43567,124 @@ #define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT 0x0 #define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK 0x00000007L +// addressBlock: dcn_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + +// addressBlock: dcn_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +// addressBlock: dcn_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + // addressBlock: dcn_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec //AFMT5_AFMT_VBI_PACKET_CONTROL @@ -43943,6 +44061,432 @@ #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L +// addressBlock: dcn_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL // addressBlock: dcn_dc_hpo_dp_stream_enc0_dispdec //DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL From 8a03fad66224a38839322d27436e41aadf8f0874 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 7 Jun 2023 13:33:03 -0600 Subject: [PATCH 59/71] drm/amd/display: Add the necessary FRL registers for DCN314 Add all the required registers to support FRL on DCN314. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../include/asic_reg/dcn/dcn_3_1_4_offset.h | 108 ++++ .../include/asic_reg/dcn/dcn_3_1_4_sh_mask.h | 544 ++++++++++++++++++ 2 files changed, 652 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h index 20a6ee7adeef..3aeb01346c12 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h @@ -14560,6 +14560,96 @@ #define regDC_PERFMON22_PERFMON_LOW 0x08cf #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c @@ -14634,6 +14724,24 @@ #define regDME9_DME_MEMORY_CONTROL 0x093d #define regDME9_DME_MEMORY_CONTROL_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hpo_top_dispdec // base address: 0x2790c diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h index d3d98d43287c..4fd16249a2db 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_sh_mask.h @@ -59876,6 +59876,489 @@ #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec //AFMT5_AFMT_VBI_PACKET_CONTROL @@ -60252,6 +60735,67 @@ #define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L #define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + // addressBlock: dce_dc_hpo_hpo_top_dispdec //HPO_TOP_CLOCK_CONTROL From bcd7f8081d8bd69cdfd9bf039a0c5fe31742f589 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 7 Jun 2023 13:53:28 -0600 Subject: [PATCH 60/71] drm/amd/display: Add FRL register for DCN302 Add the required FRL registers for DCN302. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../include/asic_reg/dcn/dcn_3_0_2_offset.h | 112 + .../include/asic_reg/dcn/dcn_3_0_2_sh_mask.h | 1907 +++++++++++++++++ 2 files changed, 2019 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h index b2962b5ce31e..47f09e233f47 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_offset.h @@ -14303,12 +14303,124 @@ #define mmDC_PERFMON25_PERFMON_HI_BASE_IDX 3 #define mmDC_PERFMON25_PERFMON_LOW 0x08cf #define mmDC_PERFMON25_PERFMON_LOW_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL 0x08d4 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define mmHDMI_TB_ENC_CONTROL 0x08df +#define mmHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define mmHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define mmHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define mmHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define mmHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define mmHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define mmHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_32_0 0x08f2 +#define mmHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_32_1 0x08f3 +#define mmHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_44_0 0x08f4 +#define mmHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_44_1 0x08f5 +#define mmHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_48_0 0x08f6 +#define mmHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_48_1 0x08f7 +#define mmHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define mmHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define mmHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define mmHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_MEM_CTRL 0x08fe +#define mmHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define mmHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_CNTL 0x0903 +#define mmHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define mmHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_MODE 0x0908 +#define mmHDMI_TB_ENC_MODE_BASE_IDX 3 +#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define mmHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + + // base address: 0x264f0 #define mmDME5_DME_CONTROL 0x093c #define mmDME5_DME_CONTROL_BASE_IDX 3 #define mmDME5_DME_MEMORY_CONTROL 0x093d #define mmDME5_DME_MEMORY_CONTROL_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define mmHDMI_LINK_ENC_CONTROL 0x095b +#define mmHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define mmHDMI_LINK_ENC_CLK_CTRL 0x095c +#define mmHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define mmHDMI_FRL_ENC_CONFIG 0x0965 +#define mmHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define mmHDMI_FRL_ENC_CONFIG2 0x0966 +#define mmHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define mmHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define mmHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_hdcp2_hdcp2_dispdec // base address: 0x264f8 diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h index 7f8f0a646422..e6e0d1bb9614 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_2_sh_mask.h @@ -52453,10 +52453,1917 @@ #define DC_PERFMON25_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 #define DC_PERFMON25_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +//AFMT5_AFMT_ACP +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE__SHIFT 0x0 +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_MASK 0x00000003L +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +//AFMT5_AFMT_VBI_PACKET_CONTROL +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT 0xd +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK 0x00002000L +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT5_AFMT_AUDIO_INFO0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT5_AFMT_AUDIO_INFO1 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT5_AFMT_60958_0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT5_AFMT_60958_1 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_CONTROL +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT5_AFMT_RAMP_CONTROL0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT5_AFMT_RAMP_CONTROL1 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT5_AFMT_RAMP_CONTROL2 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_RAMP_CONTROL3 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_60958_2 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_RESULT +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT5_AFMT_STATUS +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT5_AFMT_INFOFRAME_CONTROL0 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT5_AFMT_AUDIO_SRC_CONTROL +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT5_AFMT_AUDIO_DBG_DTO_CNTL +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L +//AFMT5_AFMT_MEM_PWR +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG5_VPG_GENERIC_PACKET_DATA +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GENERIC_STATUS +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG5_VPG_MEM_PWR +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG5_VPG_ISRC1_2_ACCESS_CTRL +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG5_VPG_ISRC1_2_DATA +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO1 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +//DME5_DME_CONTROL +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DME5_DME_MEMORY_CONTROL +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + // addressBlock: dce_dc_hpo_hpo_top_dispdec //HPO_TOP_CLOCK_CONTROL +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT 0x1 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT 0x4 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT 0x5 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT 0x8 #define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS__SHIFT 0x9 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT 0xc +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS__SHIFT 0xd +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT 0x10 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK 0x00000002L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK 0x00000010L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK 0x00000020L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK 0x00000100L #define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS_MASK 0x00000200L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK 0x00001000L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS_MASK 0x00002000L +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK 0x003F0000L + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_INCREMENT__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_MODULO__SHIFT 0x8 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_INCREMENT_MASK 0x000000FFL +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_MODULO_MASK 0x0000FF00L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +//AFMT5_AFMT_ACP +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE__SHIFT 0x0 +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_MASK 0x00000003L +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define AFMT5_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +//AFMT5_AFMT_VBI_PACKET_CONTROL +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT 0xd +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK 0x00002000L +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT5_AFMT_AUDIO_INFO0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT5_AFMT_AUDIO_INFO1 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT5_AFMT_60958_0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT5_AFMT_60958_1 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_CONTROL +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT5_AFMT_RAMP_CONTROL0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT5_AFMT_RAMP_CONTROL1 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT5_AFMT_RAMP_CONTROL2 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_RAMP_CONTROL3 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT5_AFMT_60958_2 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT5_AFMT_AUDIO_CRC_RESULT +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT5_AFMT_STATUS +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT5_AFMT_AUDIO_PACKET_CONTROL +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT5_AFMT_INFOFRAME_CONTROL0 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT5_AFMT_AUDIO_SRC_CONTROL +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT5_AFMT_AUDIO_DBG_DTO_CNTL +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L +#define AFMT5_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L +//AFMT5_AFMT_MEM_PWR +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG5_VPG_GENERIC_PACKET_DATA +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GENERIC_STATUS +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG5_VPG_MEM_PWR +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG5_VPG_ISRC1_2_ACCESS_CTRL +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG5_VPG_ISRC1_2_DATA +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG5_VPG_MPEG_INFO1 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +//DME5_DME_CONTROL +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DME5_DME_MEMORY_CONTROL +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +//HPO_TOP_CLOCK_CONTROL +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT 0x1 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT 0x4 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT 0x5 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT 0x8 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS__SHIFT 0x9 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT 0xc +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS__SHIFT 0xd +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT 0x10 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK 0x00000002L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK 0x00000010L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK 0x00000020L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK 0x00000100L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_GATE_DIS_MASK 0x00000200L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK 0x00001000L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_GATE_DIS_MASK 0x00002000L +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK 0x003F0000L + // addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec //DC_PERFMON26_PERFCOUNTER_CNTL From 26e4c6b0622683e26130ab9ccbc18f28d52187ac Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 7 Jun 2023 14:11:10 -0600 Subject: [PATCH 61/71] drm/amd/display: Add FRL register for DCN303 Add all the required registers to support FRL on DCN303. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../include/asic_reg/dcn/dcn_3_0_3_offset.h | 111 +++ .../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h | 941 ++++++++++++++++++ 2 files changed, 1052 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h index a3373d1e1736..9b1132bbab07 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_offset.h @@ -6838,6 +6838,98 @@ #define mmDC_PERFMON15_PERFMON_LOW 0x08cf #define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define mmHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL 0x08d4 +#define mmHDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define mmHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define mmHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define mmHDMI_TB_ENC_CONTROL 0x08df +#define mmHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define mmHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define mmHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define mmHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define mmHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define mmHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define mmHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define mmHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define mmHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define mmHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define mmHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define mmHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define mmHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define mmHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define mmHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define mmHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define mmHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define mmHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define mmHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_32_0 0x08f2 +#define mmHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_32_1 0x08f3 +#define mmHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_44_0 0x08f4 +#define mmHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_44_1 0x08f5 +#define mmHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_48_0 0x08f6 +#define mmHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_48_1 0x08f7 +#define mmHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define mmHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define mmHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define mmHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define mmHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_MEM_CTRL 0x08fe +#define mmHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define mmHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define mmHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define mmHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define mmHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_CNTL 0x0903 +#define mmHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define mmHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define mmHDMI_TB_ENC_MODE 0x0908 +#define mmHDMI_TB_ENC_MODE_BASE_IDX 3 +#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define mmHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define mmHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define mmHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c @@ -6882,6 +6974,25 @@ #define mmDME2_DME_MEMORY_CONTROL 0x093d #define mmDME2_DME_MEMORY_CONTROL_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define mmHDMI_LINK_ENC_CONTROL 0x095b +#define mmHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define mmHDMI_LINK_ENC_CLK_CTRL 0x095c +#define mmHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define mmHDMI_FRL_ENC_CONFIG 0x0965 +#define mmHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define mmHDMI_FRL_ENC_CONFIG2 0x0966 +#define mmHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define mmHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define mmHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define mmHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hpo_top_dispdec // base address: 0x0 diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h index 9549494b65b5..0326604ea9a7 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_3_sh_mask.h @@ -26316,6 +26316,947 @@ #define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 #define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_INCREMENT__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_MODULO__SHIFT 0x8 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_INCREMENT_MASK 0x000000FFL +#define HDMI_STREAM_ENC_HDMISTREAMCLK_CONTROL__HDMI_STREAM_ENC_HDMISTREAMCLK_MODULO_MASK 0x0000FF00L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec +//AFMT2_AFMT_ACP +#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE__SHIFT 0x0 +#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_MASK 0x00000003L +#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define AFMT2_AFMT_ACP__AFMT_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +//AFMT2_AFMT_VBI_PACKET_CONTROL +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT 0xd +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x18 +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE_MASK 0x00002000L +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001F0000L +#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x01000000L +//AFMT2_AFMT_AUDIO_PACKET_CONTROL2 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00FF0000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L +//AFMT2_AFMT_AUDIO_INFO0 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000FFL +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00FF0000L +#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1F000000L +//AFMT2_AFMT_AUDIO_INFO1 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000FFL +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//AFMT2_AFMT_60958_0 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000C0L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//AFMT2_AFMT_60958_1 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L +#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L +#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//AFMT2_AFMT_AUDIO_CRC_CONTROL +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000F000L +#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//AFMT2_AFMT_RAMP_CONTROL0 +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L +//AFMT2_AFMT_RAMP_CONTROL1 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//AFMT2_AFMT_RAMP_CONTROL2 +#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//AFMT2_AFMT_RAMP_CONTROL3 +#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 +#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//AFMT2_AFMT_60958_2 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//AFMT2_AFMT_AUDIO_CRC_RESULT +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xFFFFFF00L +//AFMT2_AFMT_STATUS +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 +#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 +#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L +#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L +#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L +#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L +//AFMT2_AFMT_AUDIO_PACKET_CONTROL +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L +#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L +//AFMT2_AFMT_INFOFRAME_CONTROL0 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L +#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L +//AFMT2_AFMT_AUDIO_SRC_CONTROL +#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L +//AFMT2_AFMT_AUDIO_DBG_DTO_CNTL +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L +#define AFMT2_AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L +//AFMT2_AFMT_MEM_PWR +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT 0x0 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT 0x4 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT 0x8 +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK 0x00000001L +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK 0x00000030L +#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG2_VPG_GENERIC_PACKET_DATA +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG2_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GENERIC_STATUS +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG2_VPG_MEM_PWR +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG2_VPG_ISRC1_2_ACCESS_CTRL +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG2_VPG_ISRC1_2_DATA +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L +//VPG2_VPG_MPEG_INFO0 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT 0x0 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT 0x8 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT 0x10 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT 0x18 +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK 0x000000FFL +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK 0x0000FF00L +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK 0x00FF0000L +#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK 0xFF000000L +//VPG2_VPG_MPEG_INFO1 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT 0x0 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT 0x8 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT 0xc +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT 0x10 +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK 0x000000FFL +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK 0x00000300L +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L +#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +//DME2_DME_CONTROL +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +//DME2_DME_MEMORY_CONTROL +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + // addressBlock: dce_dc_hpo_hpo_top_dispdec //HPO_TOP_CLOCK_CONTROL From 14c6da24af6a049c733ef315a5308448b9520f2c Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 7 Jun 2023 14:38:26 -0600 Subject: [PATCH 62/71] drm/amd/display: Add FRL registers for DCN315 Add the required FRL registers for DCN315. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../include/asic_reg/dcn/dcn_3_1_5_offset.h | 111 ++++ .../include/asic_reg/dcn/dcn_3_1_5_sh_mask.h | 548 ++++++++++++++++++ 2 files changed, 659 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h index 16a69d17bb1e..45ec5cb0f90c 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h @@ -12773,6 +12773,39 @@ #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c #define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c @@ -12845,6 +12878,84 @@ #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec // base address: 0x1ab8c #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h index 6473362e39a8..6bc91ae44682 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h @@ -46664,6 +46664,126 @@ #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec //AFMT5_AFMT_VBI_PACKET_CONTROL #define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_ACP_SOURCE__SHIFT 0xd @@ -47041,6 +47161,434 @@ #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec //DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL #define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 From b0054327595767aec4726929e6ddb94b5d31334f Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Wed, 7 Jun 2023 15:22:45 -0600 Subject: [PATCH 63/71] drm/amd/display: Add FRL registers for DCN316 Add the required FRL registers for DCN316. Signed-off-by: Rodrigo Siqueira Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- .../include/asic_reg/dcn/dcn_3_1_6_offset.h | 111 ++++ .../include/asic_reg/dcn/dcn_3_1_6_sh_mask.h | 546 ++++++++++++++++++ 2 files changed, 657 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h index a05bf8e4f58d..d289d8356adf 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_offset.h @@ -13503,6 +13503,39 @@ #define regDC_PERFMON22_PERFMON_LOW 0x0e6e #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec // base address: 0x2646c @@ -13578,6 +13611,84 @@ #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec // base address: 0x1ab8c #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h index df84941bbe5b..dd98cd5582cf 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h @@ -50009,6 +50009,125 @@ #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 #define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_SOCCLK_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_MASK 0x00000300L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ODM_COMBINE_MODE_MASK 0x00003000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_DSC_MODE_MASK 0x00030000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x5 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000001FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000020L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_PENDING_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_DB_DISABLE_MASK 0x00001000L + // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec //AFMT5_AFMT_VBI_PACKET_CONTROL @@ -50386,6 +50505,433 @@ #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK 0x00001000L #define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK 0x00010000L +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT__SHIFT 0xd +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec //DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL From c184df870db1e328691ea0fbb7d0e59efd9d3f9f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 1 Jan 2026 17:20:18 -0500 Subject: [PATCH 64/71] drm/amdgpu: plumb timedout fence through to force completion MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When we do a full adapter reset, if we know the timedout fence mark the fence with -ETIME rather than -ECANCELED so it gets properly handled by userspace. v2: rebase Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 26 +++++++++++++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 21 ++++++++++------- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 2 +- 9 files changed, 48 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 092fd3309099..b951b42d66bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -2049,7 +2049,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) /* swap out the old fences */ amdgpu_ib_preempt_fences_swap(ring, fences); - amdgpu_fence_driver_force_completion(ring); + amdgpu_fence_driver_force_completion(ring, NULL); /* resubmit unfinished jobs */ amdgpu_ib_preempt_job_recovery(&ring->sched); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 34f933350ccf..be42e8f01def 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5093,6 +5093,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, { int i, r = 0; struct amdgpu_job *job = NULL; + struct dma_fence *fence = NULL; struct amdgpu_device *tmp_adev = reset_context->reset_req_dev; bool need_full_reset = test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); @@ -5105,6 +5106,9 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, amdgpu_fence_driver_isr_toggle(adev, true); + if (job) + fence = &job->hw_fence->base; + /* block all schedulers and reset given job's ring */ for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; @@ -5113,7 +5117,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, continue; /* after all hw jobs are reset, hw fence is meaningless, so force_completion */ - amdgpu_fence_driver_force_completion(ring); + amdgpu_fence_driver_force_completion(ring, fence); } amdgpu_fence_driver_isr_toggle(adev, false); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 8048a4c04b47..ea69b1bac7c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -547,7 +547,7 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev) r = -ENODEV; /* no need to trigger GPU reset as we are unloading */ if (r) - amdgpu_fence_driver_force_completion(ring); + amdgpu_fence_driver_force_completion(ring, NULL); if (!drm_dev_is_unplugged(adev_to_drm(adev)) && ring->fence_drv.irq_src && @@ -662,16 +662,34 @@ void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error) * amdgpu_fence_driver_force_completion - force signal latest fence of ring * * @ring: fence of the ring to signal + * @timedout_fence: fence of the timedout job * */ -void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) +void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring, + struct dma_fence *timedout_fence) { - amdgpu_fence_driver_set_error(ring, -ECANCELED); + struct amdgpu_fence_driver *drv = &ring->fence_drv; + unsigned long flags; + + spin_lock_irqsave(&drv->lock, flags); + for (unsigned int i = 0; i <= drv->num_fences_mask; ++i) { + struct dma_fence *fence; + + fence = rcu_dereference_protected(drv->fences[i], + lockdep_is_held(&drv->lock)); + if (fence && !dma_fence_is_signaled_locked(fence)) { + if (fence == timedout_fence) + dma_fence_set_error(fence, -ETIME); + else + dma_fence_set_error(fence, -ECANCELED); + } + } + spin_unlock_irqrestore(&drv->lock, flags); + amdgpu_fence_write(ring, ring->fence_drv.sync_seq); amdgpu_fence_process(ring); } - /* * Kernel queue reset handling * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 715c9e43e13a..8f28b3bd7010 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -159,7 +159,8 @@ struct amdgpu_fence { extern const struct drm_sched_backend_ops amdgpu_sched_ops; void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); -void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); +void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring, + struct dma_fence *timedout_fence); void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring, struct amdgpu_fence *guilty_fence); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index 321310ba2c08..fcd81242059e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -600,10 +600,10 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id, * to be submitted to the queues after the reset is complete. */ if (!ret) { - amdgpu_fence_driver_force_completion(gfx_ring); + amdgpu_fence_driver_force_completion(gfx_ring, NULL); drm_sched_wqueue_start(&gfx_ring->sched); if (adev->sdma.has_page_queue) { - amdgpu_fence_driver_force_completion(page_ring); + amdgpu_fence_driver_force_completion(page_ring, NULL); drm_sched_wqueue_start(&page_ring->sched); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 9d5cca7da1d9..3a3bc0d370fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -512,7 +512,7 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev) } memset_io(ptr, 0, size); /* to restore uvd fence seq */ - amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); + amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring, NULL); } } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index debb82a2e031..7cbd330643cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -1487,15 +1487,16 @@ int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block, /** * amdgpu_vcn_reset_engine - Reset a specific VCN engine - * @adev: Pointer to the AMDGPU device - * @instance_id: VCN engine instance to reset + * @ring: Pointer to the VCN ring + * @timedout_fence: fence that timed out * * Returns: 0 on success, or a negative error code on failure. */ -static int amdgpu_vcn_reset_engine(struct amdgpu_device *adev, - uint32_t instance_id) +static int amdgpu_vcn_reset_engine(struct amdgpu_ring *ring, + struct amdgpu_fence *timedout_fence) { - struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[instance_id]; + struct amdgpu_device *adev = ring->adev; + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; int r, i; mutex_lock(&vinst->engine_reset_mutex); @@ -1519,9 +1520,13 @@ static int amdgpu_vcn_reset_engine(struct amdgpu_device *adev, if (r) goto unlock; } - amdgpu_fence_driver_force_completion(&vinst->ring_dec); + amdgpu_fence_driver_force_completion(&vinst->ring_dec, + (&vinst->ring_dec == ring) ? + &timedout_fence->base : NULL); for (i = 0; i < vinst->num_enc_rings; i++) - amdgpu_fence_driver_force_completion(&vinst->ring_enc[i]); + amdgpu_fence_driver_force_completion(&vinst->ring_enc[i], + (&vinst->ring_enc[i] == ring) ? + &timedout_fence->base : NULL); /* Restart the scheduler's work queue for the dec and enc rings * if they were stopped by this function. This allows new tasks @@ -1557,7 +1562,7 @@ int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring, if (adev->vcn.inst[ring->me].using_unified_queue) return -EINVAL; - return amdgpu_vcn_reset_engine(adev, ring->me); + return amdgpu_vcn_reset_engine(ring, timedout_fence); } int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 10e8fc2821f3..7f001c32e911 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1686,7 +1686,7 @@ static int vcn_v4_0_3_reset_jpeg_post_helper(struct amdgpu_device *adev, int ins for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { ring = &adev->jpeg.inst[inst].ring_dec[i]; /* Force completion of any remaining jobs */ - amdgpu_fence_driver_force_completion(ring); + amdgpu_fence_driver_force_completion(ring, NULL); if (ring->use_doorbell) WREG32_SOC15_OFFSET( diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 54fbf8d73ca6..d3db0494341e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -1332,7 +1332,7 @@ static int vcn_v5_0_1_reset_jpeg_post_helper(struct amdgpu_device *adev, int ins for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { ring = &adev->jpeg.inst[inst].ring_dec[i]; /* Force completion of any remaining jobs */ - amdgpu_fence_driver_force_completion(ring); + amdgpu_fence_driver_force_completion(ring, NULL); if (ring->use_doorbell) WREG32_SOC15_OFFSET( From e614d6054b15599dcc3f2edd03d7fd8ccd8513bd Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 13 Jan 2026 15:25:10 -0500 Subject: [PATCH 65/71] drm/amdgpu: simplify VCN reset helper Remove the wrapper function. Reviewed-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 41 ++++++++----------------- 1 file changed, 13 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 7cbd330643cd..616967519869 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -1486,19 +1486,27 @@ int vcn_set_powergating_state(struct amdgpu_ip_block *ip_block, } /** - * amdgpu_vcn_reset_engine - Reset a specific VCN engine - * @ring: Pointer to the VCN ring - * @timedout_fence: fence that timed out + * amdgpu_vcn_ring_reset - Reset a VCN ring + * @ring: ring to reset + * @vmid: vmid of guilty job + * @timedout_fence: fence of timed out job * + * This helper is for VCN blocks without unified queues because + * resetting the engine resets all queues in that case. With + * unified queues we have one queue per engine. * Returns: 0 on success, or a negative error code on failure. */ -static int amdgpu_vcn_reset_engine(struct amdgpu_ring *ring, - struct amdgpu_fence *timedout_fence) +int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring, + unsigned int vmid, + struct amdgpu_fence *timedout_fence) { struct amdgpu_device *adev = ring->adev; struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; int r, i; + if (adev->vcn.inst[ring->me].using_unified_queue) + return -EINVAL; + mutex_lock(&vinst->engine_reset_mutex); /* Stop the scheduler's work queue for the dec and enc rings if they are running. * This ensures that no new tasks are submitted to the queues while @@ -1542,29 +1550,6 @@ static int amdgpu_vcn_reset_engine(struct amdgpu_ring *ring, return r; } -/** - * amdgpu_vcn_ring_reset - Reset a VCN ring - * @ring: ring to reset - * @vmid: vmid of guilty job - * @timedout_fence: fence of timed out job - * - * This helper is for VCN blocks without unified queues because - * resetting the engine resets all queues in that case. With - * unified queues we have one queue per engine. - * Returns: 0 on success, or a negative error code on failure. - */ -int amdgpu_vcn_ring_reset(struct amdgpu_ring *ring, - unsigned int vmid, - struct amdgpu_fence *timedout_fence) -{ - struct amdgpu_device *adev = ring->adev; - - if (adev->vcn.inst[ring->me].using_unified_queue) - return -EINVAL; - - return amdgpu_vcn_reset_engine(ring, timedout_fence); -} - int amdgpu_vcn_reg_dump_init(struct amdgpu_device *adev, const struct amdgpu_hwip_reg_entry *reg, u32 count) { From 014385d7222d7bc10f6da6335b1e09ca262dd415 Mon Sep 17 00:00:00 2001 From: Caden Chien Date: Tue, 21 Apr 2026 17:26:34 +0800 Subject: [PATCH 66/71] drm/amdgpu/nbio: remove doorbell entry5 for vcn on 7.11.4 S2A doorbell entry 5 on nbio 7.11.4 is used by vpe 2.0 Signed-off-by: Caden Chien Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c index b6f832c53860..375d5ff42a63 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c @@ -144,10 +144,13 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, { u32 doorbell_range; - if (instance) + if (instance) { + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) + return; doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); - else + } else { doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL); + } if (use_doorbell) { doorbell_range = REG_SET_FIELD(doorbell_range, @@ -177,10 +180,7 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, 0); if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { - if (instance) - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range); - else - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, doorbell_range); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, doorbell_range); } else { if (instance) WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); From 802aaee0f903560cea726d3f5f090660cc2d9ab8 Mon Sep 17 00:00:00 2001 From: Caden Chien Date: Tue, 21 Apr 2026 17:28:07 +0800 Subject: [PATCH 67/71] drm/amdgpu/nbio: add doorbell range init for vpe on 7.11.4 A callback function is added to setup doorbell range during vpe hw queue initialization on nbio 7.11.4. Signed-off-by: Caden Chien Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 46 ++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c index 375d5ff42a63..28a99b52f59f 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c @@ -189,6 +189,51 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, } } +static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev, + int instance, bool use_doorbell, + int doorbell_index, + int doorbell_size) +{ + if (instance) + return; + + u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); + + if (use_doorbell) { + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, + S2A_DOORBELL_PORT5_ENABLE, + 0x1); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, + S2A_DOORBELL_PORT5_AWID, + 0xf); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, + S2A_DOORBELL_PORT5_RANGE_OFFSET, + doorbell_index); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, + S2A_DOORBELL_PORT5_RANGE_SIZE, + doorbell_size); + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, + S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE, + 0xf); + } else { + doorbell_range = REG_SET_FIELD(doorbell_range, + GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, + S2A_DOORBELL_PORT5_RANGE_SIZE, + 0); + } + + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range); + else + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); + +} + static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev) { if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { @@ -517,6 +562,7 @@ const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs = { .get_memsize = nbif_v6_3_1_get_memsize, .sdma_doorbell_range = nbif_v6_3_1_sdma_doorbell_range, .vcn_doorbell_range = nbif_v6_3_1_vcn_doorbell_range, + .vpe_doorbell_range = nbif_v6_3_1_vpe_doorbell_range, .gc_doorbell_init = nbif_v6_3_1_gc_doorbell_init, .enable_doorbell_aperture = nbif_v6_3_1_enable_doorbell_aperture, .enable_doorbell_selfring_aperture = nbif_v6_3_1_enable_doorbell_selfring_aperture, From dad6fe3f7c4e6af5875e8d0710afff2b4a0f2c6a Mon Sep 17 00:00:00 2001 From: Caden Chien Date: Wed, 22 Apr 2026 18:02:25 +0800 Subject: [PATCH 68/71] drm/amdgpu/vpe: add new vpe v2.0.0 register offset and sh/mask New offset and sh/mask are added for vpe v2.0.0 Acked-by: Roy Chan Signed-off-by: Caden Chien Signed-off-by: Alex Deucher --- .../include/asic_reg/vpe/vpe_2_0_0_offset.h | 1041 ++++++ .../include/asic_reg/vpe/vpe_2_0_0_sh_mask.h | 3162 +++++++++++++++++ 2 files changed, 4203 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_sh_mask.h diff --git a/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_offset.h new file mode 100644 index 000000000000..d815f560dacc --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_offset.h @@ -0,0 +1,1041 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _vpe_2_0_0_OFFSET_HEADER +#define _vpe_2_0_0_OFFSET_HEADER + + + +// addressBlock: vpe_vpec_vpecdec +// base address: 0x46000 +#define regVPEC_DEC_START 0x0000 +#define regVPEC_DEC_START_BASE_IDX 0 +#define regVPEC_UCODE_ADDR 0x0001 +#define regVPEC_UCODE_ADDR_BASE_IDX 0 +#define regVPEC_UCODE_DATA 0x0002 +#define regVPEC_UCODE_DATA_BASE_IDX 0 +#define regVPEC_F32_CNTL 0x0003 +#define regVPEC_F32_CNTL_BASE_IDX 0 +#define regVPEC_MMHUB_CNTL 0x0004 +#define regVPEC_MMHUB_CNTL_BASE_IDX 0 +#define regVPEC_MMHUB_TRUSTLVL 0x0005 +#define regVPEC_MMHUB_TRUSTLVL_BASE_IDX 0 +#define regVPEC_VPEP_CTRL 0x0010 +#define regVPEC_VPEP_CTRL_BASE_IDX 0 +#define regVPEC_CLK_CTRL 0x0011 +#define regVPEC_CLK_CTRL_BASE_IDX 0 +#define regVPEC_COLLABORATE_CNTL 0x0012 +#define regVPEC_COLLABORATE_CNTL_BASE_IDX 0 +#define regVPEC_COLLABORATE_CFG 0x0013 +#define regVPEC_COLLABORATE_CFG_BASE_IDX 0 +#define regVPEC_POWER_CNTL 0x0014 +#define regVPEC_POWER_CNTL_BASE_IDX 0 +#define regVPEC_ZPR_CNTL 0x0015 +#define regVPEC_ZPR_CNTL_BASE_IDX 0 +#define regVPEC_CNTL 0x0016 +#define regVPEC_CNTL_BASE_IDX 0 +#define regVPEC_CNTL_DCC 0x0017 +#define regVPEC_CNTL_DCC_BASE_IDX 0 +#define regVPEC_CE_OP_MULTI_64B_BURST 0x0018 +#define regVPEC_CE_OP_MULTI_64B_BURST_BASE_IDX 0 +#define regVPEC_CNTL1 0x0019 +#define regVPEC_CNTL1_BASE_IDX 0 +#define regVPEC_CNTL2 0x001a +#define regVPEC_CNTL2_BASE_IDX 0 +#define regVPEC_GB_ADDR_CONFIG 0x001b +#define regVPEC_GB_ADDR_CONFIG_BASE_IDX 0 +#define regVPEC_GB_ADDR_CONFIG_READ 0x001c +#define regVPEC_GB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regVPEC_GB_ADDR_CONFIG_META 0x001d +#define regVPEC_GB_ADDR_CONFIG_META_BASE_IDX 0 +#define regVPEC_PROCESS_QUANTUM0 0x001e +#define regVPEC_PROCESS_QUANTUM0_BASE_IDX 0 +#define regVPEC_PROCESS_QUANTUM1 0x001f +#define regVPEC_PROCESS_QUANTUM1_BASE_IDX 0 +#define regVPEC_CONTEXT_SWITCH_THRESHOLD 0x0020 +#define regVPEC_CONTEXT_SWITCH_THRESHOLD_BASE_IDX 0 +#define regVPEC_GLOBAL_QUANTUM 0x0021 +#define regVPEC_GLOBAL_QUANTUM_BASE_IDX 0 +#define regVPEC_WATCHDOG_CNTL 0x0025 +#define regVPEC_WATCHDOG_CNTL_BASE_IDX 0 +#define regVPEC_ATOMIC_CNTL 0x0026 +#define regVPEC_ATOMIC_CNTL_BASE_IDX 0 +#define regVPEC_UCODE_VERSION 0x0027 +#define regVPEC_UCODE_VERSION_BASE_IDX 0 +#define regVPEC_MEMREQ_BURST_CNTL 0x0028 +#define regVPEC_MEMREQ_BURST_CNTL_BASE_IDX 0 +#define regVPEC_TIMESTAMP_CNTL 0x0029 +#define regVPEC_TIMESTAMP_CNTL_BASE_IDX 0 +#define regVPEC_GLOBAL_TIMESTAMP_LO 0x002a +#define regVPEC_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 +#define regVPEC_GLOBAL_TIMESTAMP_HI 0x002b +#define regVPEC_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 +#define regVPEC_FREEZE 0x002c +#define regVPEC_FREEZE_BASE_IDX 0 +#define regVPEC_CE_CTRL 0x002d +#define regVPEC_CE_CTRL_BASE_IDX 0 +#define regVPEC_RELAX_ORDERING_LUT 0x002e +#define regVPEC_RELAX_ORDERING_LUT_BASE_IDX 0 +#define regVPEC_CREDIT_CNTL 0x002f +#define regVPEC_CREDIT_CNTL_BASE_IDX 0 +#define regVPEC_SCRATCH_RAM_DATA 0x0030 +#define regVPEC_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regVPEC_SCRATCH_RAM_ADDR 0x0031 +#define regVPEC_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regVPEC_QUEUE_RESET_REQ 0x0032 +#define regVPEC_QUEUE_RESET_REQ_BASE_IDX 0 +#define regVPEC_MAILBOX0 0x0040 +#define regVPEC_MAILBOX0_BASE_IDX 0 +#define regVPEC_MAILBOX1 0x0041 +#define regVPEC_MAILBOX1_BASE_IDX 0 +#define regVPEC_MAILBOX2 0x0042 +#define regVPEC_MAILBOX2_BASE_IDX 0 +#define regVPEC_MAILBOX3 0x0043 +#define regVPEC_MAILBOX3_BASE_IDX 0 +#define regVPEC_MAILBOX4 0x0044 +#define regVPEC_MAILBOX4_BASE_IDX 0 +#define regVPEC_MAILBOX5 0x0045 +#define regVPEC_MAILBOX5_BASE_IDX 0 +#define regVPEC_MAILBOX6 0x0046 +#define regVPEC_MAILBOX6_BASE_IDX 0 +#define regVPEC_MAILBOX7 0x0047 +#define regVPEC_MAILBOX7_BASE_IDX 0 +#define regVPEC_MAILBOX8 0x0048 +#define regVPEC_MAILBOX8_BASE_IDX 0 +#define regVPEC_MAILBOX9 0x0049 +#define regVPEC_MAILBOX9_BASE_IDX 0 +#define regVPEC_MAILBOX10 0x004a +#define regVPEC_MAILBOX10_BASE_IDX 0 +#define regVPEC_MAILBOX11 0x004b +#define regVPEC_MAILBOX11_BASE_IDX 0 +#define regVPEC_MAILBOX12 0x004c +#define regVPEC_MAILBOX12_BASE_IDX 0 +#define regVPEC_MAILBOX13 0x004d +#define regVPEC_MAILBOX13_BASE_IDX 0 +#define regVPEC_MAILBOX14 0x004e +#define regVPEC_MAILBOX14_BASE_IDX 0 +#define regVPEC_MAILBOX15 0x004f +#define regVPEC_MAILBOX15_BASE_IDX 0 +#define regVPEC_PUB_DUMMY0 0x0050 +#define regVPEC_PUB_DUMMY0_BASE_IDX 0 +#define regVPEC_PUB_DUMMY1 0x0051 +#define regVPEC_PUB_DUMMY1_BASE_IDX 0 +#define regVPEC_PUB_DUMMY2 0x0052 +#define regVPEC_PUB_DUMMY2_BASE_IDX 0 +#define regVPEC_PUB_DUMMY3 0x0053 +#define regVPEC_PUB_DUMMY3_BASE_IDX 0 +#define regVPEC_PUB_DUMMY4 0x0054 +#define regVPEC_PUB_DUMMY4_BASE_IDX 0 +#define regVPEC_PUB_DUMMY5 0x0055 +#define regVPEC_PUB_DUMMY5_BASE_IDX 0 +#define regVPEC_PUB_DUMMY6 0x0056 +#define regVPEC_PUB_DUMMY6_BASE_IDX 0 +#define regVPEC_PUB_DUMMY7 0x0057 +#define regVPEC_PUB_DUMMY7_BASE_IDX 0 +#define regVPEC_PUB_DUMMY8 0x0058 +#define regVPEC_PUB_DUMMY8_BASE_IDX 0 +#define regVPEC_PUB_DUMMY9 0x0059 +#define regVPEC_PUB_DUMMY9_BASE_IDX 0 +#define regVPEC_PUB_DUMMY10 0x005a +#define regVPEC_PUB_DUMMY10_BASE_IDX 0 +#define regVPEC_PUB_DUMMY11 0x005b +#define regVPEC_PUB_DUMMY11_BASE_IDX 0 +#define regVPEC_UCODE1_CHECKSUM 0x005c +#define regVPEC_UCODE1_CHECKSUM_BASE_IDX 0 +#define regVPEC_VERSION 0x005d +#define regVPEC_VERSION_BASE_IDX 0 +#define regVPEC_UCODE_CHECKSUM 0x005e +#define regVPEC_UCODE_CHECKSUM_BASE_IDX 0 +#define regVPEC_RB_RPTR_FETCH 0x005f +#define regVPEC_RB_RPTR_FETCH_BASE_IDX 0 +#define regVPEC_RB_RPTR_FETCH_HI 0x0060 +#define regVPEC_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regVPEC_IB_OFFSET_FETCH 0x0061 +#define regVPEC_IB_OFFSET_FETCH_BASE_IDX 0 +#define regVPEC_CMDIB_OFFSET_FETCH 0x0062 +#define regVPEC_CMDIB_OFFSET_FETCH_BASE_IDX 0 +#define regVPEC_3DLUTIB_OFFSET_FETCH 0x0063 +#define regVPEC_3DLUTIB_OFFSET_FETCH_BASE_IDX 0 +#define regVPEC_ATOMIC_PREOP_LO 0x0064 +#define regVPEC_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regVPEC_ATOMIC_PREOP_HI 0x0065 +#define regVPEC_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regVPEC_CE_BUSY 0x0066 +#define regVPEC_CE_BUSY_BASE_IDX 0 +#define regVPEC_F32_COUNTER 0x0067 +#define regVPEC_F32_COUNTER_BASE_IDX 0 +#define regVPEC_HOLE_ADDR_LO 0x0068 +#define regVPEC_HOLE_ADDR_LO_BASE_IDX 0 +#define regVPEC_HOLE_ADDR_HI 0x0069 +#define regVPEC_HOLE_ADDR_HI_BASE_IDX 0 +#define regVPEC_ERROR_LOG 0x006a +#define regVPEC_ERROR_LOG_BASE_IDX 0 +#define regVPEC_INT_STATUS 0x006b +#define regVPEC_INT_STATUS_BASE_IDX 0 +#define regVPEC_STATUS 0x006c +#define regVPEC_STATUS_BASE_IDX 0 +#define regVPEC_STATUS1 0x006d +#define regVPEC_STATUS1_BASE_IDX 0 +#define regVPEC_STATUS2 0x006e +#define regVPEC_STATUS2_BASE_IDX 0 +#define regVPEC_STATUS3 0x006f +#define regVPEC_STATUS3_BASE_IDX 0 +#define regVPEC_STATUS4 0x0070 +#define regVPEC_STATUS4_BASE_IDX 0 +#define regVPEC_STATUS5 0x0071 +#define regVPEC_STATUS5_BASE_IDX 0 +#define regVPEC_STATUS6 0x0072 +#define regVPEC_STATUS6_BASE_IDX 0 +#define regVPEC_STATUS7 0x0073 +#define regVPEC_STATUS7_BASE_IDX 0 +#define regVPEC_STATUS8 0x0074 +#define regVPEC_STATUS8_BASE_IDX 0 +#define regVPEC_STATUS9 0x0075 +#define regVPEC_STATUS9_BASE_IDX 0 +#define regVPEC_STATUS10 0x0076 +#define regVPEC_STATUS10_BASE_IDX 0 +#define regVPEC_STATUS_DCC 0x0077 +#define regVPEC_STATUS_DCC_BASE_IDX 0 +#define regVPEC_STATUS11 0x0078 +#define regVPEC_STATUS11_BASE_IDX 0 +#define regVPEC_INST 0x0079 +#define regVPEC_INST_BASE_IDX 0 +#define regVPEC_QUEUE_STATUS0 0x007a +#define regVPEC_QUEUE_STATUS0_BASE_IDX 0 +#define regVPEC_QUEUE_HANG_STATUS 0x007b +#define regVPEC_QUEUE_HANG_STATUS_BASE_IDX 0 +#define regVPEC_DPM_IDLE_TIME 0x007c +#define regVPEC_DPM_IDLE_TIME_BASE_IDX 0 +#define regVPEC_DPM_BUSY_TIME 0x007d +#define regVPEC_DPM_BUSY_TIME_BASE_IDX 0 +#define regVPEC_DPM_IDLE_START_LO 0x007e +#define regVPEC_DPM_IDLE_START_LO_BASE_IDX 0 +#define regVPEC_DPM_IDLE_START_HI 0x007f +#define regVPEC_DPM_IDLE_START_HI_BASE_IDX 0 +#define regVPEC_DPM_BUSY_START_LO 0x0080 +#define regVPEC_DPM_BUSY_START_LO_BASE_IDX 0 +#define regVPEC_DPM_BUSY_START_HI 0x0081 +#define regVPEC_DPM_BUSY_START_HI_BASE_IDX 0 +#define regVPEC_DPM_LAST_REQ_TIMESTAMP 0x0082 +#define regVPEC_DPM_LAST_REQ_TIMESTAMP_BASE_IDX 0 +#define regVPEC_DPM_NEW_JOB_DUMMY3 0x0083 +#define regVPEC_DPM_NEW_JOB_DUMMY3_BASE_IDX 0 +#define regVPEC_DPM_STATE 0x0084 +#define regVPEC_DPM_STATE_BASE_IDX 0 +#define regVPEC_DPM0_FREQ 0x0085 +#define regVPEC_DPM0_FREQ_BASE_IDX 0 +#define regVPEC_DPM1_FREQ 0x0086 +#define regVPEC_DPM1_FREQ_BASE_IDX 0 +#define regVPEC_DPM2_FREQ 0x0087 +#define regVPEC_DPM2_FREQ_BASE_IDX 0 +#define regVPEC_DPM3_FREQ 0x0088 +#define regVPEC_DPM3_FREQ_BASE_IDX 0 +#define regVPEC_DPM_THRESHOLD_SKIP 0x0089 +#define regVPEC_DPM_THRESHOLD_SKIP_BASE_IDX 0 +#define regVPEC_DPM_THRESHOLD_BUSY_OVERFLOW 0x008a +#define regVPEC_DPM_THRESHOLD_BUSY_OVERFLOW_BASE_IDX 0 +#define regVPEC_DPM_CALC_BUSY_IN_POSTPROCESS 0x008b +#define regVPEC_DPM_CALC_BUSY_IN_POSTPROCESS_BASE_IDX 0 +#define regVPEC_DPM_IN_CHECKIDLE_LOOP 0x008c +#define regVPEC_DPM_IN_CHECKIDLE_LOOP_BASE_IDX 0 +#define regVPEC_DPM_THRESHOLD_IDLE_OVERFLOW 0x008d +#define regVPEC_DPM_THRESHOLD_IDLE_OVERFLOW_BASE_IDX 0 +#define regVPEC_DPM_BUSY_CLAMP_COUNT 0x008e +#define regVPEC_DPM_BUSY_CLAMP_COUNT_BASE_IDX 0 +#define regVPEC_DPM_IDLE_CLAMP_COUNT 0x008f +#define regVPEC_DPM_IDLE_CLAMP_COUNT_BASE_IDX 0 +#define regVPEC_PG_CNTL 0x00b8 +#define regVPEC_PG_CNTL_BASE_IDX 0 +#define regVPEC_PG_STATUS 0x00b9 +#define regVPEC_PG_STATUS_BASE_IDX 0 +#define regVPEC_CLOCK_GATING_STATUS 0x00ba +#define regVPEC_CLOCK_GATING_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_CNTL 0x00c0 +#define regVPEC_QUEUE0_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_SCHEDULE_CNTL 0x00c1 +#define regVPEC_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_BASE 0x00c2 +#define regVPEC_QUEUE0_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_BASE_HI 0x00c3 +#define regVPEC_QUEUE0_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_RPTR 0x00c4 +#define regVPEC_QUEUE0_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_RPTR_HI 0x00c5 +#define regVPEC_QUEUE0_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_WPTR 0x00c6 +#define regVPEC_QUEUE0_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_WPTR_HI 0x00c7 +#define regVPEC_QUEUE0_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_HI 0x00c8 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_LO 0x00c9 +#define regVPEC_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_AQL_CNTL 0x00ca +#define regVPEC_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_MINOR_PTR_UPDATE 0x00cb +#define regVPEC_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE0_CD_INFO 0x00cc +#define regVPEC_QUEUE0_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE0_RB_PREEMPT 0x00cd +#define regVPEC_QUEUE0_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE0_SKIP_CNTL 0x00ce +#define regVPEC_QUEUE0_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_DOORBELL 0x00cf +#define regVPEC_QUEUE0_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE0_DOORBELL_OFFSET 0x00d0 +#define regVPEC_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY0 0x00d1 +#define regVPEC_QUEUE0_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY1 0x00d2 +#define regVPEC_QUEUE0_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY2 0x00d3 +#define regVPEC_QUEUE0_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY3 0x00d4 +#define regVPEC_QUEUE0_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE0_DUMMY4 0x00d5 +#define regVPEC_QUEUE0_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_CNTL 0x00ec +#define regVPEC_QUEUE0_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_RPTR 0x00ed +#define regVPEC_QUEUE0_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_OFFSET 0x00ee +#define regVPEC_QUEUE0_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_BASE_LO 0x00ef +#define regVPEC_QUEUE0_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_BASE_HI 0x00f0 +#define regVPEC_QUEUE0_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_SIZE 0x00f1 +#define regVPEC_QUEUE0_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_CNTL 0x00f2 +#define regVPEC_QUEUE0_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_RPTR 0x00f3 +#define regVPEC_QUEUE0_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_OFFSET 0x00f4 +#define regVPEC_QUEUE0_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_BASE_LO 0x00f5 +#define regVPEC_QUEUE0_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_BASE_HI 0x00f6 +#define regVPEC_QUEUE0_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_CMDIB_SIZE 0x00f7 +#define regVPEC_QUEUE0_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE0_3DLUTIB_CNTL 0x00f8 +#define regVPEC_QUEUE0_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE0_3DLUTIB_RPTR 0x00f9 +#define regVPEC_QUEUE0_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE0_3DLUTIB_OFFSET 0x00fa +#define regVPEC_QUEUE0_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE0_3DLUTIB_BASE_LO 0x00fb +#define regVPEC_QUEUE0_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_3DLUTIB_BASE_HI 0x00fc +#define regVPEC_QUEUE0_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_3DLUTIB_SIZE 0x00fd +#define regVPEC_QUEUE0_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE0_CSA_ADDR_LO 0x00fe +#define regVPEC_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE0_CSA_ADDR_HI 0x00ff +#define regVPEC_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE0_CONTEXT_STATUS 0x0100 +#define regVPEC_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE0_DOORBELL_LOG 0x0101 +#define regVPEC_QUEUE0_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE0_IB_SUB_REMAIN 0x0102 +#define regVPEC_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE0_PREEMPT 0x0103 +#define regVPEC_QUEUE0_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE0_LOG0BUFFER_CFG 0x0104 +#define regVPEC_QUEUE0_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE0_LOG1BUFFER_CFG 0x0105 +#define regVPEC_QUEUE0_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_CNTL 0x0118 +#define regVPEC_QUEUE1_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_SCHEDULE_CNTL 0x0119 +#define regVPEC_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_BASE 0x011a +#define regVPEC_QUEUE1_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_BASE_HI 0x011b +#define regVPEC_QUEUE1_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_RPTR 0x011c +#define regVPEC_QUEUE1_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_RPTR_HI 0x011d +#define regVPEC_QUEUE1_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_WPTR 0x011e +#define regVPEC_QUEUE1_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_WPTR_HI 0x011f +#define regVPEC_QUEUE1_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_HI 0x0120 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_LO 0x0121 +#define regVPEC_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_AQL_CNTL 0x0122 +#define regVPEC_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_MINOR_PTR_UPDATE 0x0123 +#define regVPEC_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE1_CD_INFO 0x0124 +#define regVPEC_QUEUE1_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE1_RB_PREEMPT 0x0125 +#define regVPEC_QUEUE1_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE1_SKIP_CNTL 0x0126 +#define regVPEC_QUEUE1_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_DOORBELL 0x0127 +#define regVPEC_QUEUE1_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE1_DOORBELL_OFFSET 0x0128 +#define regVPEC_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY0 0x0129 +#define regVPEC_QUEUE1_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY1 0x012a +#define regVPEC_QUEUE1_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY2 0x012b +#define regVPEC_QUEUE1_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY3 0x012c +#define regVPEC_QUEUE1_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE1_DUMMY4 0x012d +#define regVPEC_QUEUE1_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_CNTL 0x0144 +#define regVPEC_QUEUE1_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_RPTR 0x0145 +#define regVPEC_QUEUE1_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_OFFSET 0x0146 +#define regVPEC_QUEUE1_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_BASE_LO 0x0147 +#define regVPEC_QUEUE1_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_BASE_HI 0x0148 +#define regVPEC_QUEUE1_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_SIZE 0x0149 +#define regVPEC_QUEUE1_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_CNTL 0x014a +#define regVPEC_QUEUE1_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_RPTR 0x014b +#define regVPEC_QUEUE1_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_OFFSET 0x014c +#define regVPEC_QUEUE1_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_BASE_LO 0x014d +#define regVPEC_QUEUE1_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_BASE_HI 0x014e +#define regVPEC_QUEUE1_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_CMDIB_SIZE 0x014f +#define regVPEC_QUEUE1_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE1_3DLUTIB_CNTL 0x0150 +#define regVPEC_QUEUE1_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE1_3DLUTIB_RPTR 0x0151 +#define regVPEC_QUEUE1_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE1_3DLUTIB_OFFSET 0x0152 +#define regVPEC_QUEUE1_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE1_3DLUTIB_BASE_LO 0x0153 +#define regVPEC_QUEUE1_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_3DLUTIB_BASE_HI 0x0154 +#define regVPEC_QUEUE1_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_3DLUTIB_SIZE 0x0155 +#define regVPEC_QUEUE1_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE1_CSA_ADDR_LO 0x0156 +#define regVPEC_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE1_CSA_ADDR_HI 0x0157 +#define regVPEC_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE1_CONTEXT_STATUS 0x0158 +#define regVPEC_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE1_DOORBELL_LOG 0x0159 +#define regVPEC_QUEUE1_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE1_IB_SUB_REMAIN 0x015a +#define regVPEC_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE1_PREEMPT 0x015b +#define regVPEC_QUEUE1_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE1_LOG0BUFFER_CFG 0x015c +#define regVPEC_QUEUE1_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE1_LOG1BUFFER_CFG 0x015d +#define regVPEC_QUEUE1_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_CNTL 0x0170 +#define regVPEC_QUEUE2_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_SCHEDULE_CNTL 0x0171 +#define regVPEC_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_BASE 0x0172 +#define regVPEC_QUEUE2_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_BASE_HI 0x0173 +#define regVPEC_QUEUE2_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_RPTR 0x0174 +#define regVPEC_QUEUE2_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_RPTR_HI 0x0175 +#define regVPEC_QUEUE2_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_WPTR 0x0176 +#define regVPEC_QUEUE2_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_WPTR_HI 0x0177 +#define regVPEC_QUEUE2_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_HI 0x0178 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_LO 0x0179 +#define regVPEC_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_AQL_CNTL 0x017a +#define regVPEC_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_MINOR_PTR_UPDATE 0x017b +#define regVPEC_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE2_CD_INFO 0x017c +#define regVPEC_QUEUE2_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE2_RB_PREEMPT 0x017d +#define regVPEC_QUEUE2_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE2_SKIP_CNTL 0x017e +#define regVPEC_QUEUE2_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_DOORBELL 0x017f +#define regVPEC_QUEUE2_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE2_DOORBELL_OFFSET 0x0180 +#define regVPEC_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY0 0x0181 +#define regVPEC_QUEUE2_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY1 0x0182 +#define regVPEC_QUEUE2_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY2 0x0183 +#define regVPEC_QUEUE2_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY3 0x0184 +#define regVPEC_QUEUE2_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE2_DUMMY4 0x0185 +#define regVPEC_QUEUE2_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_CNTL 0x019c +#define regVPEC_QUEUE2_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_RPTR 0x019d +#define regVPEC_QUEUE2_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_OFFSET 0x019e +#define regVPEC_QUEUE2_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_BASE_LO 0x019f +#define regVPEC_QUEUE2_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_BASE_HI 0x01a0 +#define regVPEC_QUEUE2_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_SIZE 0x01a1 +#define regVPEC_QUEUE2_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_CNTL 0x01a2 +#define regVPEC_QUEUE2_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_RPTR 0x01a3 +#define regVPEC_QUEUE2_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_OFFSET 0x01a4 +#define regVPEC_QUEUE2_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_BASE_LO 0x01a5 +#define regVPEC_QUEUE2_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_BASE_HI 0x01a6 +#define regVPEC_QUEUE2_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_CMDIB_SIZE 0x01a7 +#define regVPEC_QUEUE2_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE2_3DLUTIB_CNTL 0x01a8 +#define regVPEC_QUEUE2_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE2_3DLUTIB_RPTR 0x01a9 +#define regVPEC_QUEUE2_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE2_3DLUTIB_OFFSET 0x01aa +#define regVPEC_QUEUE2_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE2_3DLUTIB_BASE_LO 0x01ab +#define regVPEC_QUEUE2_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_3DLUTIB_BASE_HI 0x01ac +#define regVPEC_QUEUE2_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_3DLUTIB_SIZE 0x01ad +#define regVPEC_QUEUE2_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE2_CSA_ADDR_LO 0x01ae +#define regVPEC_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE2_CSA_ADDR_HI 0x01af +#define regVPEC_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE2_CONTEXT_STATUS 0x01b0 +#define regVPEC_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE2_DOORBELL_LOG 0x01b1 +#define regVPEC_QUEUE2_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE2_IB_SUB_REMAIN 0x01b2 +#define regVPEC_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE2_PREEMPT 0x01b3 +#define regVPEC_QUEUE2_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE2_LOG0BUFFER_CFG 0x01b4 +#define regVPEC_QUEUE2_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE2_LOG1BUFFER_CFG 0x01b5 +#define regVPEC_QUEUE2_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_CNTL 0x01c8 +#define regVPEC_QUEUE3_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_SCHEDULE_CNTL 0x01c9 +#define regVPEC_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_BASE 0x01ca +#define regVPEC_QUEUE3_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_BASE_HI 0x01cb +#define regVPEC_QUEUE3_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_RPTR 0x01cc +#define regVPEC_QUEUE3_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_RPTR_HI 0x01cd +#define regVPEC_QUEUE3_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_WPTR 0x01ce +#define regVPEC_QUEUE3_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_WPTR_HI 0x01cf +#define regVPEC_QUEUE3_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_HI 0x01d0 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_LO 0x01d1 +#define regVPEC_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_AQL_CNTL 0x01d2 +#define regVPEC_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_MINOR_PTR_UPDATE 0x01d3 +#define regVPEC_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE3_CD_INFO 0x01d4 +#define regVPEC_QUEUE3_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE3_RB_PREEMPT 0x01d5 +#define regVPEC_QUEUE3_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE3_SKIP_CNTL 0x01d6 +#define regVPEC_QUEUE3_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_DOORBELL 0x01d7 +#define regVPEC_QUEUE3_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE3_DOORBELL_OFFSET 0x01d8 +#define regVPEC_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY0 0x01d9 +#define regVPEC_QUEUE3_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY1 0x01da +#define regVPEC_QUEUE3_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY2 0x01db +#define regVPEC_QUEUE3_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY3 0x01dc +#define regVPEC_QUEUE3_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE3_DUMMY4 0x01dd +#define regVPEC_QUEUE3_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_CNTL 0x01f4 +#define regVPEC_QUEUE3_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_RPTR 0x01f5 +#define regVPEC_QUEUE3_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_OFFSET 0x01f6 +#define regVPEC_QUEUE3_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_BASE_LO 0x01f7 +#define regVPEC_QUEUE3_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_BASE_HI 0x01f8 +#define regVPEC_QUEUE3_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_SIZE 0x01f9 +#define regVPEC_QUEUE3_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_CNTL 0x01fa +#define regVPEC_QUEUE3_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_RPTR 0x01fb +#define regVPEC_QUEUE3_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_OFFSET 0x01fc +#define regVPEC_QUEUE3_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_BASE_LO 0x01fd +#define regVPEC_QUEUE3_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_BASE_HI 0x01fe +#define regVPEC_QUEUE3_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_CMDIB_SIZE 0x01ff +#define regVPEC_QUEUE3_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE3_3DLUTIB_CNTL 0x0200 +#define regVPEC_QUEUE3_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE3_3DLUTIB_RPTR 0x0201 +#define regVPEC_QUEUE3_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE3_3DLUTIB_OFFSET 0x0202 +#define regVPEC_QUEUE3_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE3_3DLUTIB_BASE_LO 0x0203 +#define regVPEC_QUEUE3_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_3DLUTIB_BASE_HI 0x0204 +#define regVPEC_QUEUE3_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_3DLUTIB_SIZE 0x0205 +#define regVPEC_QUEUE3_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE3_CSA_ADDR_LO 0x0206 +#define regVPEC_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE3_CSA_ADDR_HI 0x0207 +#define regVPEC_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE3_CONTEXT_STATUS 0x0208 +#define regVPEC_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE3_DOORBELL_LOG 0x0209 +#define regVPEC_QUEUE3_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE3_IB_SUB_REMAIN 0x020a +#define regVPEC_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE3_PREEMPT 0x020b +#define regVPEC_QUEUE3_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE3_LOG0BUFFER_CFG 0x020c +#define regVPEC_QUEUE3_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE3_LOG1BUFFER_CFG 0x020d +#define regVPEC_QUEUE3_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_CNTL 0x0220 +#define regVPEC_QUEUE4_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_SCHEDULE_CNTL 0x0221 +#define regVPEC_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_BASE 0x0222 +#define regVPEC_QUEUE4_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_BASE_HI 0x0223 +#define regVPEC_QUEUE4_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_RPTR 0x0224 +#define regVPEC_QUEUE4_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_RPTR_HI 0x0225 +#define regVPEC_QUEUE4_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_WPTR 0x0226 +#define regVPEC_QUEUE4_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_WPTR_HI 0x0227 +#define regVPEC_QUEUE4_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_HI 0x0228 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_LO 0x0229 +#define regVPEC_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_AQL_CNTL 0x022a +#define regVPEC_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_MINOR_PTR_UPDATE 0x022b +#define regVPEC_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE4_CD_INFO 0x022c +#define regVPEC_QUEUE4_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE4_RB_PREEMPT 0x022d +#define regVPEC_QUEUE4_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE4_SKIP_CNTL 0x022e +#define regVPEC_QUEUE4_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_DOORBELL 0x022f +#define regVPEC_QUEUE4_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE4_DOORBELL_OFFSET 0x0230 +#define regVPEC_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY0 0x0231 +#define regVPEC_QUEUE4_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY1 0x0232 +#define regVPEC_QUEUE4_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY2 0x0233 +#define regVPEC_QUEUE4_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY3 0x0234 +#define regVPEC_QUEUE4_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE4_DUMMY4 0x0235 +#define regVPEC_QUEUE4_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_CNTL 0x024c +#define regVPEC_QUEUE4_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_RPTR 0x024d +#define regVPEC_QUEUE4_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_OFFSET 0x024e +#define regVPEC_QUEUE4_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_BASE_LO 0x024f +#define regVPEC_QUEUE4_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_BASE_HI 0x0250 +#define regVPEC_QUEUE4_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_SIZE 0x0251 +#define regVPEC_QUEUE4_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_CNTL 0x0252 +#define regVPEC_QUEUE4_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_RPTR 0x0253 +#define regVPEC_QUEUE4_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_OFFSET 0x0254 +#define regVPEC_QUEUE4_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_BASE_LO 0x0255 +#define regVPEC_QUEUE4_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_BASE_HI 0x0256 +#define regVPEC_QUEUE4_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_CMDIB_SIZE 0x0257 +#define regVPEC_QUEUE4_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE4_3DLUTIB_CNTL 0x0258 +#define regVPEC_QUEUE4_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE4_3DLUTIB_RPTR 0x0259 +#define regVPEC_QUEUE4_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE4_3DLUTIB_OFFSET 0x025a +#define regVPEC_QUEUE4_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE4_3DLUTIB_BASE_LO 0x025b +#define regVPEC_QUEUE4_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_3DLUTIB_BASE_HI 0x025c +#define regVPEC_QUEUE4_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_3DLUTIB_SIZE 0x025d +#define regVPEC_QUEUE4_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE4_CSA_ADDR_LO 0x025e +#define regVPEC_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE4_CSA_ADDR_HI 0x025f +#define regVPEC_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE4_CONTEXT_STATUS 0x0260 +#define regVPEC_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE4_DOORBELL_LOG 0x0261 +#define regVPEC_QUEUE4_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE4_IB_SUB_REMAIN 0x0262 +#define regVPEC_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE4_PREEMPT 0x0263 +#define regVPEC_QUEUE4_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE4_LOG0BUFFER_CFG 0x0264 +#define regVPEC_QUEUE4_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE4_LOG1BUFFER_CFG 0x0265 +#define regVPEC_QUEUE4_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_CNTL 0x0278 +#define regVPEC_QUEUE5_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_SCHEDULE_CNTL 0x0279 +#define regVPEC_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_BASE 0x027a +#define regVPEC_QUEUE5_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_BASE_HI 0x027b +#define regVPEC_QUEUE5_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_RPTR 0x027c +#define regVPEC_QUEUE5_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_RPTR_HI 0x027d +#define regVPEC_QUEUE5_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_WPTR 0x027e +#define regVPEC_QUEUE5_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_WPTR_HI 0x027f +#define regVPEC_QUEUE5_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_HI 0x0280 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_LO 0x0281 +#define regVPEC_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_AQL_CNTL 0x0282 +#define regVPEC_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_MINOR_PTR_UPDATE 0x0283 +#define regVPEC_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE5_CD_INFO 0x0284 +#define regVPEC_QUEUE5_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE5_RB_PREEMPT 0x0285 +#define regVPEC_QUEUE5_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE5_SKIP_CNTL 0x0286 +#define regVPEC_QUEUE5_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_DOORBELL 0x0287 +#define regVPEC_QUEUE5_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE5_DOORBELL_OFFSET 0x0288 +#define regVPEC_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY0 0x0289 +#define regVPEC_QUEUE5_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY1 0x028a +#define regVPEC_QUEUE5_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY2 0x028b +#define regVPEC_QUEUE5_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY3 0x028c +#define regVPEC_QUEUE5_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE5_DUMMY4 0x028d +#define regVPEC_QUEUE5_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_CNTL 0x02a4 +#define regVPEC_QUEUE5_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_RPTR 0x02a5 +#define regVPEC_QUEUE5_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_OFFSET 0x02a6 +#define regVPEC_QUEUE5_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_BASE_LO 0x02a7 +#define regVPEC_QUEUE5_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_BASE_HI 0x02a8 +#define regVPEC_QUEUE5_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_SIZE 0x02a9 +#define regVPEC_QUEUE5_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_CNTL 0x02aa +#define regVPEC_QUEUE5_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_RPTR 0x02ab +#define regVPEC_QUEUE5_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_OFFSET 0x02ac +#define regVPEC_QUEUE5_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_BASE_LO 0x02ad +#define regVPEC_QUEUE5_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_BASE_HI 0x02ae +#define regVPEC_QUEUE5_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_CMDIB_SIZE 0x02af +#define regVPEC_QUEUE5_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE5_3DLUTIB_CNTL 0x02b0 +#define regVPEC_QUEUE5_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE5_3DLUTIB_RPTR 0x02b1 +#define regVPEC_QUEUE5_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE5_3DLUTIB_OFFSET 0x02b2 +#define regVPEC_QUEUE5_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE5_3DLUTIB_BASE_LO 0x02b3 +#define regVPEC_QUEUE5_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_3DLUTIB_BASE_HI 0x02b4 +#define regVPEC_QUEUE5_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_3DLUTIB_SIZE 0x02b5 +#define regVPEC_QUEUE5_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE5_CSA_ADDR_LO 0x02b6 +#define regVPEC_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE5_CSA_ADDR_HI 0x02b7 +#define regVPEC_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE5_CONTEXT_STATUS 0x02b8 +#define regVPEC_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE5_DOORBELL_LOG 0x02b9 +#define regVPEC_QUEUE5_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE5_IB_SUB_REMAIN 0x02ba +#define regVPEC_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE5_PREEMPT 0x02bb +#define regVPEC_QUEUE5_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE5_LOG0BUFFER_CFG 0x02bc +#define regVPEC_QUEUE5_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE5_LOG1BUFFER_CFG 0x02bd +#define regVPEC_QUEUE5_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_CNTL 0x02d0 +#define regVPEC_QUEUE6_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_SCHEDULE_CNTL 0x02d1 +#define regVPEC_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_BASE 0x02d2 +#define regVPEC_QUEUE6_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_BASE_HI 0x02d3 +#define regVPEC_QUEUE6_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_RPTR 0x02d4 +#define regVPEC_QUEUE6_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_RPTR_HI 0x02d5 +#define regVPEC_QUEUE6_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_WPTR 0x02d6 +#define regVPEC_QUEUE6_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_WPTR_HI 0x02d7 +#define regVPEC_QUEUE6_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_HI 0x02d8 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_LO 0x02d9 +#define regVPEC_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_AQL_CNTL 0x02da +#define regVPEC_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_MINOR_PTR_UPDATE 0x02db +#define regVPEC_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE6_CD_INFO 0x02dc +#define regVPEC_QUEUE6_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE6_RB_PREEMPT 0x02dd +#define regVPEC_QUEUE6_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE6_SKIP_CNTL 0x02de +#define regVPEC_QUEUE6_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_DOORBELL 0x02df +#define regVPEC_QUEUE6_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE6_DOORBELL_OFFSET 0x02e0 +#define regVPEC_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY0 0x02e1 +#define regVPEC_QUEUE6_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY1 0x02e2 +#define regVPEC_QUEUE6_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY2 0x02e3 +#define regVPEC_QUEUE6_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY3 0x02e4 +#define regVPEC_QUEUE6_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE6_DUMMY4 0x02e5 +#define regVPEC_QUEUE6_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_CNTL 0x02fc +#define regVPEC_QUEUE6_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_RPTR 0x02fd +#define regVPEC_QUEUE6_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_OFFSET 0x02fe +#define regVPEC_QUEUE6_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_BASE_LO 0x02ff +#define regVPEC_QUEUE6_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_BASE_HI 0x0300 +#define regVPEC_QUEUE6_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_SIZE 0x0301 +#define regVPEC_QUEUE6_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_CNTL 0x0302 +#define regVPEC_QUEUE6_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_RPTR 0x0303 +#define regVPEC_QUEUE6_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_OFFSET 0x0304 +#define regVPEC_QUEUE6_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_BASE_LO 0x0305 +#define regVPEC_QUEUE6_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_BASE_HI 0x0306 +#define regVPEC_QUEUE6_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_CMDIB_SIZE 0x0307 +#define regVPEC_QUEUE6_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE6_3DLUTIB_CNTL 0x0308 +#define regVPEC_QUEUE6_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE6_3DLUTIB_RPTR 0x0309 +#define regVPEC_QUEUE6_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE6_3DLUTIB_OFFSET 0x030a +#define regVPEC_QUEUE6_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE6_3DLUTIB_BASE_LO 0x030b +#define regVPEC_QUEUE6_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_3DLUTIB_BASE_HI 0x030c +#define regVPEC_QUEUE6_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_3DLUTIB_SIZE 0x030d +#define regVPEC_QUEUE6_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE6_CSA_ADDR_LO 0x030e +#define regVPEC_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE6_CSA_ADDR_HI 0x030f +#define regVPEC_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE6_CONTEXT_STATUS 0x0310 +#define regVPEC_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE6_DOORBELL_LOG 0x0311 +#define regVPEC_QUEUE6_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE6_IB_SUB_REMAIN 0x0312 +#define regVPEC_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE6_PREEMPT 0x0313 +#define regVPEC_QUEUE6_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE6_LOG0BUFFER_CFG 0x0314 +#define regVPEC_QUEUE6_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE6_LOG1BUFFER_CFG 0x0315 +#define regVPEC_QUEUE6_LOG1BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_CNTL 0x0328 +#define regVPEC_QUEUE7_RB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_SCHEDULE_CNTL 0x0329 +#define regVPEC_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_BASE 0x032a +#define regVPEC_QUEUE7_RB_BASE_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_BASE_HI 0x032b +#define regVPEC_QUEUE7_RB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_RPTR 0x032c +#define regVPEC_QUEUE7_RB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_RPTR_HI 0x032d +#define regVPEC_QUEUE7_RB_RPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_WPTR 0x032e +#define regVPEC_QUEUE7_RB_WPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_WPTR_HI 0x032f +#define regVPEC_QUEUE7_RB_WPTR_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_HI 0x0330 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_LO 0x0331 +#define regVPEC_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_AQL_CNTL 0x0332 +#define regVPEC_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_MINOR_PTR_UPDATE 0x0333 +#define regVPEC_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regVPEC_QUEUE7_CD_INFO 0x0334 +#define regVPEC_QUEUE7_CD_INFO_BASE_IDX 0 +#define regVPEC_QUEUE7_RB_PREEMPT 0x0335 +#define regVPEC_QUEUE7_RB_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE7_SKIP_CNTL 0x0336 +#define regVPEC_QUEUE7_SKIP_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_DOORBELL 0x0337 +#define regVPEC_QUEUE7_DOORBELL_BASE_IDX 0 +#define regVPEC_QUEUE7_DOORBELL_OFFSET 0x0338 +#define regVPEC_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY0 0x0339 +#define regVPEC_QUEUE7_DUMMY0_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY1 0x033a +#define regVPEC_QUEUE7_DUMMY1_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY2 0x033b +#define regVPEC_QUEUE7_DUMMY2_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY3 0x033c +#define regVPEC_QUEUE7_DUMMY3_BASE_IDX 0 +#define regVPEC_QUEUE7_DUMMY4 0x033d +#define regVPEC_QUEUE7_DUMMY4_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_CNTL 0x0354 +#define regVPEC_QUEUE7_IB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_RPTR 0x0355 +#define regVPEC_QUEUE7_IB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_OFFSET 0x0356 +#define regVPEC_QUEUE7_IB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_BASE_LO 0x0357 +#define regVPEC_QUEUE7_IB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_BASE_HI 0x0358 +#define regVPEC_QUEUE7_IB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_SIZE 0x0359 +#define regVPEC_QUEUE7_IB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_CNTL 0x035a +#define regVPEC_QUEUE7_CMDIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_RPTR 0x035b +#define regVPEC_QUEUE7_CMDIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_OFFSET 0x035c +#define regVPEC_QUEUE7_CMDIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_BASE_LO 0x035d +#define regVPEC_QUEUE7_CMDIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_BASE_HI 0x035e +#define regVPEC_QUEUE7_CMDIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_CMDIB_SIZE 0x035f +#define regVPEC_QUEUE7_CMDIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE7_3DLUTIB_CNTL 0x0360 +#define regVPEC_QUEUE7_3DLUTIB_CNTL_BASE_IDX 0 +#define regVPEC_QUEUE7_3DLUTIB_RPTR 0x0361 +#define regVPEC_QUEUE7_3DLUTIB_RPTR_BASE_IDX 0 +#define regVPEC_QUEUE7_3DLUTIB_OFFSET 0x0362 +#define regVPEC_QUEUE7_3DLUTIB_OFFSET_BASE_IDX 0 +#define regVPEC_QUEUE7_3DLUTIB_BASE_LO 0x0363 +#define regVPEC_QUEUE7_3DLUTIB_BASE_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_3DLUTIB_BASE_HI 0x0364 +#define regVPEC_QUEUE7_3DLUTIB_BASE_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_3DLUTIB_SIZE 0x0365 +#define regVPEC_QUEUE7_3DLUTIB_SIZE_BASE_IDX 0 +#define regVPEC_QUEUE7_CSA_ADDR_LO 0x0366 +#define regVPEC_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 +#define regVPEC_QUEUE7_CSA_ADDR_HI 0x0367 +#define regVPEC_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 +#define regVPEC_QUEUE7_CONTEXT_STATUS 0x0368 +#define regVPEC_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 +#define regVPEC_QUEUE7_DOORBELL_LOG 0x0369 +#define regVPEC_QUEUE7_DOORBELL_LOG_BASE_IDX 0 +#define regVPEC_QUEUE7_IB_SUB_REMAIN 0x036a +#define regVPEC_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 +#define regVPEC_QUEUE7_PREEMPT 0x036b +#define regVPEC_QUEUE7_PREEMPT_BASE_IDX 0 +#define regVPEC_QUEUE7_LOG0BUFFER_CFG 0x036c +#define regVPEC_QUEUE7_LOG0BUFFER_CFG_BASE_IDX 0 +#define regVPEC_QUEUE7_LOG1BUFFER_CFG 0x036d +#define regVPEC_QUEUE7_LOG1BUFFER_CFG_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_sh_mask.h new file mode 100644 index 000000000000..7e0e56d14e67 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vpe/vpe_2_0_0_sh_mask.h @@ -0,0 +1,3162 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _vpe_2_0_0_SH_MASK_HEADER +#define _vpe_2_0_0_SH_MASK_HEADER + + +// addressBlock: vpe_vpec_vpecdec +//VPEC_DEC_START +#define VPEC_DEC_START__START__SHIFT 0x0 +#define VPEC_DEC_START__START_MASK 0xFFFFFFFFL +//VPEC_UCODE_ADDR +#define VPEC_UCODE_ADDR__VALUE__SHIFT 0x0 +#define VPEC_UCODE_ADDR__THID__SHIFT 0xf +#define VPEC_UCODE_ADDR__VALUE_MASK 0x00001FFFL +#define VPEC_UCODE_ADDR__THID_MASK 0x00008000L +//VPEC_UCODE_DATA +#define VPEC_UCODE_DATA__VALUE__SHIFT 0x0 +#define VPEC_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL +//VPEC_F32_CNTL +#define VPEC_F32_CNTL__HALT__SHIFT 0x0 +#define VPEC_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8 +#define VPEC_F32_CNTL__TH0_RESET__SHIFT 0x9 +#define VPEC_F32_CNTL__TH0_ENABLE__SHIFT 0xa +#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT 0xc +#define VPEC_F32_CNTL__TH1_RESET__SHIFT 0xd +#define VPEC_F32_CNTL__TH1_ENABLE__SHIFT 0xe +#define VPEC_F32_CNTL__TH0_PRIORITY__SHIFT 0x10 +#define VPEC_F32_CNTL__TH1_PRIORITY__SHIFT 0x18 +#define VPEC_F32_CNTL__HALT_MASK 0x00000001L +#define VPEC_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL +#define VPEC_F32_CNTL__TH0_CHECKSUM_CLR_MASK 0x00000100L +#define VPEC_F32_CNTL__TH0_RESET_MASK 0x00000200L +#define VPEC_F32_CNTL__TH0_ENABLE_MASK 0x00000400L +#define VPEC_F32_CNTL__TH1_CHECKSUM_CLR_MASK 0x00001000L +#define VPEC_F32_CNTL__TH1_RESET_MASK 0x00002000L +#define VPEC_F32_CNTL__TH1_ENABLE_MASK 0x00004000L +#define VPEC_F32_CNTL__TH0_PRIORITY_MASK 0x00FF0000L +#define VPEC_F32_CNTL__TH1_PRIORITY_MASK 0xFF000000L +//VPEC_MMHUB_CNTL +#define VPEC_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 +#define VPEC_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL +//VPEC_MMHUB_TRUSTLVL +#define VPEC_MMHUB_TRUSTLVL__SECLVL0__SHIFT 0x0 +#define VPEC_MMHUB_TRUSTLVL__SECLVL1__SHIFT 0x4 +#define VPEC_MMHUB_TRUSTLVL__SECLVL2__SHIFT 0x8 +#define VPEC_MMHUB_TRUSTLVL__SECLVL3__SHIFT 0xc +#define VPEC_MMHUB_TRUSTLVL__SECLVL4__SHIFT 0x10 +#define VPEC_MMHUB_TRUSTLVL__SECLVL5__SHIFT 0x14 +#define VPEC_MMHUB_TRUSTLVL__SECLVL6__SHIFT 0x18 +#define VPEC_MMHUB_TRUSTLVL__SECLVL7__SHIFT 0x1c +#define VPEC_MMHUB_TRUSTLVL__SECLVL0_MASK 0x0000000FL +#define VPEC_MMHUB_TRUSTLVL__SECLVL1_MASK 0x000000F0L +#define VPEC_MMHUB_TRUSTLVL__SECLVL2_MASK 0x00000F00L +#define VPEC_MMHUB_TRUSTLVL__SECLVL3_MASK 0x0000F000L +#define VPEC_MMHUB_TRUSTLVL__SECLVL4_MASK 0x000F0000L +#define VPEC_MMHUB_TRUSTLVL__SECLVL5_MASK 0x00F00000L +#define VPEC_MMHUB_TRUSTLVL__SECLVL6_MASK 0x0F000000L +#define VPEC_MMHUB_TRUSTLVL__SECLVL7_MASK 0xF0000000L +//VPEC_VPEP_CTRL +#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN__SHIFT 0x0 +#define VPEC_VPEP_CTRL__VPEP_SW_RESETB__SHIFT 0x1 +#define VPEC_VPEP_CTRL__RESERVED__SHIFT 0x2 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P0__SHIFT 0x16 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P1__SHIFT 0x17 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P2__SHIFT 0x18 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P0__SHIFT 0x19 +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P1__SHIFT 0x1a +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P2__SHIFT 0x1b +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_3DLUT__SHIFT 0x1c +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEC_VPEP_REG_FGCLKEN__SHIFT 0x1d +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK__SHIFT 0x1e +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK__SHIFT 0x1f +#define VPEC_VPEP_CTRL__VPEP_SOCCLK_EN_MASK 0x00000001L +#define VPEC_VPEP_CTRL__VPEP_SW_RESETB_MASK 0x00000002L +#define VPEC_VPEP_CTRL__RESERVED_MASK 0x003FFFFCL +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P0_MASK 0x00400000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P1_MASK 0x00800000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S0P2_MASK 0x01000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P0_MASK 0x02000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P1_MASK 0x04000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_S1P2_MASK 0x08000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_FGCLKEN_3DLUT_MASK 0x10000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEC_VPEP_REG_FGCLKEN_MASK 0x20000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPEP_SOCCLK_MASK 0x40000000L +#define VPEC_VPEP_CTRL__SOFT_OVERRIDE_VPECLK_MASK 0x80000000L +//VPEC_CLK_CTRL +#define VPEC_CLK_CTRL__VPECLK_EN__SHIFT 0x1 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK__SHIFT 0x8 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK__SHIFT 0x9 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE2_CLK__SHIFT 0xa +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE3_CLK__SHIFT 0xb +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE4_CLK__SHIFT 0xc +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE5_CLK__SHIFT 0xd +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK__SHIFT 0x10 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE1_CLK__SHIFT 0x11 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE2_CLK__SHIFT 0x12 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE3_CLK__SHIFT 0x13 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE4_CLK__SHIFT 0x14 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE5_CLK__SHIFT 0x15 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE6_CLK__SHIFT 0x16 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE7_CLK__SHIFT 0x17 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE8_CLK__SHIFT 0x18 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE9_CLK__SHIFT 0x19 +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK__SHIFT 0x1b +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK__SHIFT 0x1c +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK__SHIFT 0x1d +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK__SHIFT 0x1e +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK__SHIFT 0x1f +#define VPEC_CLK_CTRL__VPECLK_EN_MASK 0x00000002L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE0_CLK_MASK 0x00000100L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE1_CLK_MASK 0x00000200L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE2_CLK_MASK 0x00000400L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE3_CLK_MASK 0x00000800L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE4_CLK_MASK 0x00001000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_IP_PIPE5_CLK_MASK 0x00002000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE0_CLK_MASK 0x00010000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE1_CLK_MASK 0x00020000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE2_CLK_MASK 0x00040000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE3_CLK_MASK 0x00080000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE4_CLK_MASK 0x00100000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE5_CLK_MASK 0x00200000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE6_CLK_MASK 0x00400000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE7_CLK_MASK 0x00800000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE8_CLK_MASK 0x01000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_OP_PIPE9_CLK_MASK 0x02000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_PERF_CLK_MASK 0x08000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_CE_CLK_MASK 0x10000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_F32_CLK_MASK 0x20000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_DYN_CLK_MASK 0x40000000L +#define VPEC_CLK_CTRL__SOFT_OVERRIDE_REG_CLK_MASK 0x80000000L +//VPEC_COLLABORATE_CNTL +#define VPEC_COLLABORATE_CNTL__COLLABORATE_MODE_EN__SHIFT 0x0 +#define VPEC_COLLABORATE_CNTL__COLLABORATE_MODE_EN_MASK 0x00000001L +//VPEC_COLLABORATE_CFG +#define VPEC_COLLABORATE_CFG__MASTER_ID__SHIFT 0x0 +#define VPEC_COLLABORATE_CFG__MASTER_EN__SHIFT 0x3 +#define VPEC_COLLABORATE_CFG__SLAVE0_ID__SHIFT 0x4 +#define VPEC_COLLABORATE_CFG__SLAVE0_EN__SHIFT 0x7 +#define VPEC_COLLABORATE_CFG__MASTER_ID_MASK 0x00000007L +#define VPEC_COLLABORATE_CFG__MASTER_EN_MASK 0x00000008L +#define VPEC_COLLABORATE_CFG__SLAVE0_ID_MASK 0x00000070L +#define VPEC_COLLABORATE_CFG__SLAVE0_EN_MASK 0x00000080L +//VPEC_POWER_CNTL +#define VPEC_POWER_CNTL__LS_ENABLE__SHIFT 0x0 +#define VPEC_POWER_CNTL__UCODE_SRAM_DS_EN__SHIFT 0x1 +#define VPEC_POWER_CNTL__FISO__SHIFT 0x2 +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_UP_RECOVER_DELAY__SHIFT 0x8 +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_WAKEUP_TIME__SHIFT 0xf +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_CLK_FORCE__SHIFT 0x12 +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_DELAY__SHIFT 0x14 +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE__SHIFT 0x17 +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE_DELAY__SHIFT 0x18 +#define VPEC_POWER_CNTL__LS_ENABLE_MASK 0x00000001L +#define VPEC_POWER_CNTL__UCODE_SRAM_DS_EN_MASK 0x00000002L +#define VPEC_POWER_CNTL__FISO_MASK 0x00000004L +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_UP_RECOVER_DELAY_MASK 0x00007F00L +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_WAKEUP_TIME_MASK 0x00038000L +#define VPEC_POWER_CNTL__UCODE_SRAM_POWER_STATUS_CHANGE_CLK_FORCE_MASK 0x00040000L +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_DELAY_MASK 0x00700000L +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE_MASK 0x00800000L +#define VPEC_POWER_CNTL__SRAM_POWER_LS_CHANGE_CLK_FORCE_DELAY_MASK 0x03000000L +//VPEC_ZPR_CNTL +#define VPEC_ZPR_CNTL__CLK_UNGATE_DELAY__SHIFT 0x0 +#define VPEC_ZPR_CNTL__RESERVED__SHIFT 0x8 +#define VPEC_ZPR_CNTL__CLK_UNGATE_DELAY_MASK 0x000000FFL +#define VPEC_ZPR_CNTL__RESERVED_MASK 0xFFFFFF00L +//VPEC_CNTL +#define VPEC_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define VPEC_CNTL__RESERVED_2_2__SHIFT 0x2 +#define VPEC_CNTL__DATA_SWAP__SHIFT 0x3 +#define VPEC_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x5 +#define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x6 +#define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 +#define VPEC_CNTL__UMSCH_INT_ENABLE__SHIFT 0xa +#define VPEC_CNTL__RESERVED_13_11__SHIFT 0xb +#define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE__SHIFT 0xe +#define VPEC_CNTL__NACK_PRT_INT_ENABLE__SHIFT 0xf +#define VPEC_CNTL__RESERVED_16_16__SHIFT 0x10 +#define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define VPEC_CNTL__RESERVED_19_19__SHIFT 0x13 +#define VPEC_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define VPEC_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define VPEC_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define VPEC_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f +#define VPEC_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define VPEC_CNTL__RESERVED_2_2_MASK 0x00000004L +#define VPEC_CNTL__DATA_SWAP_MASK 0x00000018L +#define VPEC_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000020L +#define VPEC_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000040L +#define VPEC_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L +#define VPEC_CNTL__UMSCH_INT_ENABLE_MASK 0x00000400L +#define VPEC_CNTL__RESERVED_13_11_MASK 0x00003800L +#define VPEC_CNTL__NACK_GEN_ERR_INT_ENABLE_MASK 0x00004000L +#define VPEC_CNTL__NACK_PRT_INT_ENABLE_MASK 0x00008000L +#define VPEC_CNTL__RESERVED_16_16_MASK 0x00010000L +#define VPEC_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define VPEC_CNTL__RESERVED_19_19_MASK 0x00080000L +#define VPEC_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define VPEC_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define VPEC_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +#define VPEC_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L +//VPEC_CNTL_DCC +#define VPEC_CNTL_DCC__WDCC_COMP_MODE__SHIFT 0x0 +#define VPEC_CNTL_DCC__RESERVED_3_2__SHIFT 0x2 +#define VPEC_CNTL_DCC__WDCC_MICRO_TILE_MODE__SHIFT 0x4 +#define VPEC_CNTL_DCC__RESERVED_7_6__SHIFT 0x6 +#define VPEC_CNTL_DCC__WDCC_DATA_FORMAT__SHIFT 0x8 +#define VPEC_CNTL_DCC__RESERVED_15_13__SHIFT 0xd +#define VPEC_CNTL_DCC__WDCC_NUM_FORMAT_EN__SHIFT 0x10 +#define VPEC_CNTL_DCC__RESERVED_19_17__SHIFT 0x11 +#define VPEC_CNTL_DCC__WDCC_NUM_TYPE__SHIFT 0x14 +#define VPEC_CNTL_DCC__RESERVED_23_23__SHIFT 0x17 +#define VPEC_CNTL_DCC__WDCC_MAX_UNCOMP_SIZE__SHIFT 0x18 +#define VPEC_CNTL_DCC__WDCC_MAX_COMP_SIZE__SHIFT 0x19 +#define VPEC_CNTL_DCC__RESERVED_30_27__SHIFT 0x1b +#define VPEC_CNTL_DCC__RDCC_COMP_MODE__SHIFT 0x1f +#define VPEC_CNTL_DCC__WDCC_COMP_MODE_MASK 0x00000003L +#define VPEC_CNTL_DCC__RESERVED_3_2_MASK 0x0000000CL +#define VPEC_CNTL_DCC__WDCC_MICRO_TILE_MODE_MASK 0x00000030L +#define VPEC_CNTL_DCC__RESERVED_7_6_MASK 0x000000C0L +#define VPEC_CNTL_DCC__WDCC_DATA_FORMAT_MASK 0x00001F00L +#define VPEC_CNTL_DCC__RESERVED_15_13_MASK 0x0000E000L +#define VPEC_CNTL_DCC__WDCC_NUM_FORMAT_EN_MASK 0x00010000L +#define VPEC_CNTL_DCC__RESERVED_19_17_MASK 0x000E0000L +#define VPEC_CNTL_DCC__WDCC_NUM_TYPE_MASK 0x00700000L +#define VPEC_CNTL_DCC__RESERVED_23_23_MASK 0x00800000L +#define VPEC_CNTL_DCC__WDCC_MAX_UNCOMP_SIZE_MASK 0x01000000L +#define VPEC_CNTL_DCC__WDCC_MAX_COMP_SIZE_MASK 0x06000000L +#define VPEC_CNTL_DCC__RESERVED_30_27_MASK 0x78000000L +#define VPEC_CNTL_DCC__RDCC_COMP_MODE_MASK 0x80000000L +//VPEC_CE_OP_MULTI_64B_BURST +#define VPEC_CE_OP_MULTI_64B_BURST__EN__SHIFT 0x0 +#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_3_1__SHIFT 0x1 +#define VPEC_CE_OP_MULTI_64B_BURST__LAZY_TIMER_DLY__SHIFT 0x4 +#define VPEC_CE_OP_MULTI_64B_BURST__NUM_64B_BURST_ALLOWED__SHIFT 0xa +#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_31_12__SHIFT 0xc +#define VPEC_CE_OP_MULTI_64B_BURST__EN_MASK 0x00000001L +#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_3_1_MASK 0x0000000EL +#define VPEC_CE_OP_MULTI_64B_BURST__LAZY_TIMER_DLY_MASK 0x000003F0L +#define VPEC_CE_OP_MULTI_64B_BURST__NUM_64B_BURST_ALLOWED_MASK 0x00000C00L +#define VPEC_CE_OP_MULTI_64B_BURST__RESERVED_31_12_MASK 0xFFFFF000L +//VPEC_CNTL1 +#define VPEC_CNTL1__RESERVED_3_1__SHIFT 0x1 +#define VPEC_CNTL1__SRBM_POLL_RETRYING__SHIFT 0x5 +#define VPEC_CNTL1__RESERVED_23_10__SHIFT 0xa +#define VPEC_CNTL1__CG_STATUS_OUTPUT__SHIFT 0x18 +#define VPEC_CNTL1__SW_FREEZE_ENABLE__SHIFT 0x19 +#define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE__SHIFT 0x1a +#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_RETURN_ERROR_ENABLE__SHIFT 0x1b +#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_REPORT_ERROR_ENABLE__SHIFT 0x1c +#define VPEC_CNTL1__RESERVED__SHIFT 0x1d +#define VPEC_CNTL1__RESERVED_3_1_MASK 0x0000000EL +#define VPEC_CNTL1__SRBM_POLL_RETRYING_MASK 0x00000020L +#define VPEC_CNTL1__RESERVED_23_10_MASK 0x00FFFC00L +#define VPEC_CNTL1__CG_STATUS_OUTPUT_MASK 0x01000000L +#define VPEC_CNTL1__SW_FREEZE_ENABLE_MASK 0x02000000L +#define VPEC_CNTL1__VPEP_CONFIG_INVALID_CHECK_ENABLE_MASK 0x04000000L +#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_RETURN_ERROR_ENABLE_MASK 0x08000000L +#define VPEC_CNTL1__RSMU_ACCESS_OFF_VPEP_REPORT_ERROR_ENABLE_MASK 0x10000000L +#define VPEC_CNTL1__RESERVED_MASK 0xE0000000L +//VPEC_CNTL2 +#define VPEC_CNTL2__F32_CMD_PROC_DELAY__SHIFT 0x0 +#define VPEC_CNTL2__F32_SEND_POSTCODE_EN__SHIFT 0x4 +#define VPEC_CNTL2__UCODE_BUF_DS_EN__SHIFT 0x6 +#define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT 0x7 +#define VPEC_CNTL2__LUTIB_FIFO_WATERMARK__SHIFT 0x8 +#define VPEC_CNTL2__CMDIB_FIFO_WATERMARK__SHIFT 0xa +#define VPEC_CNTL2__RESERVED_14_12__SHIFT 0xc +#define VPEC_CNTL2__IMPROVE_CE_IP_ARBITER__SHIFT 0xf +#define VPEC_CNTL2__RB_FIFO_WATERMARK__SHIFT 0x10 +#define VPEC_CNTL2__IB_FIFO_WATERMARK__SHIFT 0x12 +#define VPEC_CNTL2__RESERVED_22_20__SHIFT 0x14 +#define VPEC_CNTL2__CH_RD_WATERMARK__SHIFT 0x17 +#define VPEC_CNTL2__CH_WR_WATERMARK__SHIFT 0x19 +#define VPEC_CNTL2__CH_WR_WATERMARK_LSB__SHIFT 0x1e +#define VPEC_CNTL2__F32_CMD_PROC_DELAY_MASK 0x0000000FL +#define VPEC_CNTL2__F32_SEND_POSTCODE_EN_MASK 0x00000010L +#define VPEC_CNTL2__UCODE_BUF_DS_EN_MASK 0x00000040L +#define VPEC_CNTL2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK 0x00000080L +#define VPEC_CNTL2__LUTIB_FIFO_WATERMARK_MASK 0x00000300L +#define VPEC_CNTL2__CMDIB_FIFO_WATERMARK_MASK 0x00000C00L +#define VPEC_CNTL2__RESERVED_14_12_MASK 0x00007000L +#define VPEC_CNTL2__IMPROVE_CE_IP_ARBITER_MASK 0x00008000L +#define VPEC_CNTL2__RB_FIFO_WATERMARK_MASK 0x00030000L +#define VPEC_CNTL2__IB_FIFO_WATERMARK_MASK 0x000C0000L +#define VPEC_CNTL2__RESERVED_22_20_MASK 0x00700000L +#define VPEC_CNTL2__CH_RD_WATERMARK_MASK 0x01800000L +#define VPEC_CNTL2__CH_WR_WATERMARK_MASK 0x3E000000L +#define VPEC_CNTL2__CH_WR_WATERMARK_LSB_MASK 0x40000000L +//VPEC_GB_ADDR_CONFIG +#define VPEC_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define VPEC_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 +#define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a +#define VPEC_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define VPEC_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define VPEC_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define VPEC_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L +#define VPEC_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +#define VPEC_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L +//VPEC_GB_ADDR_CONFIG_READ +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define VPEC_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define VPEC_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define VPEC_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L +#define VPEC_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L +#define VPEC_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L +//VPEC_GB_ADDR_CONFIG_META +#define VPEC_GB_ADDR_CONFIG_META__NUM_PIPES__SHIFT 0x0 +#define VPEC_GB_ADDR_CONFIG_META__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define VPEC_GB_ADDR_CONFIG_META__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define VPEC_GB_ADDR_CONFIG_META__NUM_PKRS__SHIFT 0x8 +#define VPEC_GB_ADDR_CONFIG_META__NUM_SHADER_ENGINES__SHIFT 0x13 +#define VPEC_GB_ADDR_CONFIG_META__NUM_RB_PER_SE__SHIFT 0x1a +#define VPEC_GB_ADDR_CONFIG_META__NUM_PIPES_MASK 0x00000007L +#define VPEC_GB_ADDR_CONFIG_META__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define VPEC_GB_ADDR_CONFIG_META__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define VPEC_GB_ADDR_CONFIG_META__NUM_PKRS_MASK 0x00000700L +#define VPEC_GB_ADDR_CONFIG_META__NUM_SHADER_ENGINES_MASK 0x00180000L +#define VPEC_GB_ADDR_CONFIG_META__NUM_RB_PER_SE_MASK 0x0C000000L +//VPEC_PROCESS_QUANTUM0 +#define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 +#define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 +#define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 +#define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 +#define VPEC_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL +#define VPEC_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L +#define VPEC_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L +#define VPEC_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L +//VPEC_PROCESS_QUANTUM1 +#define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 +#define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 +#define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 +#define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 +#define VPEC_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL +#define VPEC_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L +#define VPEC_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L +#define VPEC_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L +//VPEC_CONTEXT_SWITCH_THRESHOLD +#define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD__SHIFT 0x0 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD__SHIFT 0x2 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD__SHIFT 0x4 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD__SHIFT 0x6 +#define VPEC_CONTEXT_SWITCH_THRESHOLD__REALTIME_THRESHOLD_MASK 0x00000003L +#define VPEC_CONTEXT_SWITCH_THRESHOLD__FOCUS_THRESHOLD_MASK 0x0000000CL +#define VPEC_CONTEXT_SWITCH_THRESHOLD__NORMAL_THRESHOLD_MASK 0x00000030L +#define VPEC_CONTEXT_SWITCH_THRESHOLD__IDLE_THRESHOLD_MASK 0x000000C0L +//VPEC_GLOBAL_QUANTUM +#define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 +#define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 +#define VPEC_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL +#define VPEC_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L +//VPEC_WATCHDOG_CNTL +#define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 +#define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 +#define VPEC_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL +#define VPEC_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L +//VPEC_ATOMIC_CNTL +#define VPEC_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define VPEC_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define VPEC_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//VPEC_UCODE_VERSION +#define VPEC_UCODE_VERSION__T0_UCODE_VERSION__SHIFT 0x0 +#define VPEC_UCODE_VERSION__T1_UCODE_VERSION__SHIFT 0x10 +#define VPEC_UCODE_VERSION__T0_UCODE_VERSION_MASK 0x0000FFFFL +#define VPEC_UCODE_VERSION__T1_UCODE_VERSION_MASK 0xFFFF0000L +//VPEC_MEMREQ_BURST_CNTL +#define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST__SHIFT 0x0 +#define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST__SHIFT 0x2 +#define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST__SHIFT 0x4 +#define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST__SHIFT 0x6 +#define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE__SHIFT 0x8 +#define VPEC_MEMREQ_BURST_CNTL__DATA_RD_BURST_MASK 0x00000003L +#define VPEC_MEMREQ_BURST_CNTL__DATA_WR_BURST_MASK 0x0000000CL +#define VPEC_MEMREQ_BURST_CNTL__RB_RD_BURST_MASK 0x00000030L +#define VPEC_MEMREQ_BURST_CNTL__IB_RD_BURST_MASK 0x000000C0L +#define VPEC_MEMREQ_BURST_CNTL__WR_BURST_WAIT_CYCLE_MASK 0x00000700L +//VPEC_TIMESTAMP_CNTL +#define VPEC_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 +#define VPEC_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L +//VPEC_GLOBAL_TIMESTAMP_LO +#define VPEC_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 +#define VPEC_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL +//VPEC_GLOBAL_TIMESTAMP_HI +#define VPEC_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 +#define VPEC_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL +//VPEC_FREEZE +#define VPEC_FREEZE__PREEMPT__SHIFT 0x0 +#define VPEC_FREEZE__FREEZE__SHIFT 0x4 +#define VPEC_FREEZE__FROZEN__SHIFT 0x5 +#define VPEC_FREEZE__F32_FREEZE__SHIFT 0x6 +#define VPEC_FREEZE__PREEMPT_MASK 0x00000001L +#define VPEC_FREEZE__FREEZE_MASK 0x00000010L +#define VPEC_FREEZE__FROZEN_MASK 0x00000020L +#define VPEC_FREEZE__F32_FREEZE_MASK 0x00000040L +//VPEC_CE_CTRL +#define VPEC_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define VPEC_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define VPEC_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define VPEC_CE_CTRL__RESERVED__SHIFT 0x8 +#define VPEC_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define VPEC_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define VPEC_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define VPEC_CE_CTRL__RESERVED_MASK 0xFFFFFF00L +//VPEC_RELAX_ORDERING_LUT +#define VPEC_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 +#define VPEC_RELAX_ORDERING_LUT__VPE__SHIFT 0x1 +#define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2__SHIFT 0x2 +#define VPEC_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 +#define VPEC_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 +#define VPEC_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 +#define VPEC_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 +#define VPEC_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 +#define VPEC_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 +#define VPEC_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa +#define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11__SHIFT 0xb +#define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12__SHIFT 0xc +#define VPEC_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd +#define VPEC_RELAX_ORDERING_LUT__NATIVE_FENCE__SHIFT 0xe +#define VPEC_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xf +#define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b +#define VPEC_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c +#define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29__SHIFT 0x1d +#define VPEC_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e +#define VPEC_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f +#define VPEC_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L +#define VPEC_RELAX_ORDERING_LUT__VPE_MASK 0x00000002L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_2_2_MASK 0x00000004L +#define VPEC_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L +#define VPEC_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L +#define VPEC_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L +#define VPEC_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L +#define VPEC_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L +#define VPEC_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L +#define VPEC_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_11_11_MASK 0x00000800L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_12_12_MASK 0x00001000L +#define VPEC_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L +#define VPEC_RELAX_ORDERING_LUT__NATIVE_FENCE_MASK 0x00004000L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FF8000L +#define VPEC_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L +#define VPEC_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L +#define VPEC_RELAX_ORDERING_LUT__RESERVED_29_29_MASK 0x20000000L +#define VPEC_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L +#define VPEC_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L +//VPEC_CREDIT_CNTL +#define VPEC_CREDIT_CNTL__DRM_CREDIT__SHIFT 0x0 +#define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 +#define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd +#define VPEC_CREDIT_CNTL__DRM_CREDIT_MASK 0x0000007FL +#define VPEC_CREDIT_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L +#define VPEC_CREDIT_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L +//VPEC_SCRATCH_RAM_DATA +#define VPEC_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define VPEC_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//VPEC_SCRATCH_RAM_ADDR +#define VPEC_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define VPEC_SCRATCH_RAM_ADDR__ADDR_MASK 0x000000FFL +//VPEC_QUEUE_RESET_REQ +#define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 +#define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 +#define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 +#define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 +#define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 +#define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 +#define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 +#define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 +#define VPEC_QUEUE_RESET_REQ__RESERVED__SHIFT 0x8 +#define VPEC_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L +#define VPEC_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L +#define VPEC_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L +#define VPEC_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L +#define VPEC_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L +#define VPEC_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L +#define VPEC_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L +#define VPEC_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L +#define VPEC_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFF00L +//VPEC_MAILBOX0 +#define VPEC_MAILBOX0__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX0__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX1 +#define VPEC_MAILBOX1__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX1__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX2 +#define VPEC_MAILBOX2__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX2__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX3 +#define VPEC_MAILBOX3__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX3__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX4 +#define VPEC_MAILBOX4__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX4__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX5 +#define VPEC_MAILBOX5__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX5__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX6 +#define VPEC_MAILBOX6__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX6__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX7 +#define VPEC_MAILBOX7__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX7__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX8 +#define VPEC_MAILBOX8__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX8__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX9 +#define VPEC_MAILBOX9__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX9__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX10 +#define VPEC_MAILBOX10__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX10__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX11 +#define VPEC_MAILBOX11__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX11__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX12 +#define VPEC_MAILBOX12__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX12__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX13 +#define VPEC_MAILBOX13__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX13__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX14 +#define VPEC_MAILBOX14__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX14__VALUE_MASK 0xFFFFFFFFL +//VPEC_MAILBOX15 +#define VPEC_MAILBOX15__VALUE__SHIFT 0x0 +#define VPEC_MAILBOX15__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY0 +#define VPEC_PUB_DUMMY0__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY0__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY1 +#define VPEC_PUB_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY2 +#define VPEC_PUB_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY3 +#define VPEC_PUB_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY4 +#define VPEC_PUB_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY5 +#define VPEC_PUB_DUMMY5__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY5__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY6 +#define VPEC_PUB_DUMMY6__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY6__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY7 +#define VPEC_PUB_DUMMY7__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY7__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY8 +#define VPEC_PUB_DUMMY8__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY8__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY9 +#define VPEC_PUB_DUMMY9__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY9__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY10 +#define VPEC_PUB_DUMMY10__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY10__VALUE_MASK 0xFFFFFFFFL +//VPEC_PUB_DUMMY11 +#define VPEC_PUB_DUMMY11__VALUE__SHIFT 0x0 +#define VPEC_PUB_DUMMY11__VALUE_MASK 0xFFFFFFFFL +//VPEC_UCODE1_CHECKSUM +#define VPEC_UCODE1_CHECKSUM__DATA__SHIFT 0x0 +#define VPEC_UCODE1_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//VPEC_VERSION +#define VPEC_VERSION__MINVER__SHIFT 0x0 +#define VPEC_VERSION__MAJVER__SHIFT 0x8 +#define VPEC_VERSION__REV__SHIFT 0x10 +#define VPEC_VERSION__MINVER_MASK 0x0000007FL +#define VPEC_VERSION__MAJVER_MASK 0x00007F00L +#define VPEC_VERSION__REV_MASK 0x003F0000L +//VPEC_UCODE_CHECKSUM +#define VPEC_UCODE_CHECKSUM__DATA__SHIFT 0x0 +#define VPEC_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL +//VPEC_RB_RPTR_FETCH +#define VPEC_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define VPEC_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//VPEC_RB_RPTR_FETCH_HI +#define VPEC_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define VPEC_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_IB_OFFSET_FETCH +#define VPEC_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define VPEC_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//VPEC_CMDIB_OFFSET_FETCH +#define VPEC_CMDIB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define VPEC_CMDIB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//VPEC_3DLUTIB_OFFSET_FETCH +#define VPEC_3DLUTIB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define VPEC_3DLUTIB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//VPEC_ATOMIC_PREOP_LO +#define VPEC_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define VPEC_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//VPEC_ATOMIC_PREOP_HI +#define VPEC_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define VPEC_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//VPEC_CE_BUSY +#define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY__SHIFT 0x0 +#define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY__SHIFT 0x1 +#define VPEC_CE_BUSY__CE_IP_PIPE2_BUSY__SHIFT 0x2 +#define VPEC_CE_BUSY__CE_IP_PIPE3_BUSY__SHIFT 0x3 +#define VPEC_CE_BUSY__CE_IP_PIPE4_BUSY__SHIFT 0x4 +#define VPEC_CE_BUSY__CE_IP_PIPE5_BUSY__SHIFT 0x5 +#define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY__SHIFT 0x10 +#define VPEC_CE_BUSY__CE_OP_PIPE1_BUSY__SHIFT 0x11 +#define VPEC_CE_BUSY__CE_OP_PIPE2_BUSY__SHIFT 0x12 +#define VPEC_CE_BUSY__CE_OP_PIPE3_BUSY__SHIFT 0x13 +#define VPEC_CE_BUSY__CE_OP_PIPE4_BUSY__SHIFT 0x14 +#define VPEC_CE_BUSY__CE_OP_PIPE5_BUSY__SHIFT 0x15 +#define VPEC_CE_BUSY__CE_OP_PIPE6_BUSY__SHIFT 0x16 +#define VPEC_CE_BUSY__CE_OP_PIPE7_BUSY__SHIFT 0x17 +#define VPEC_CE_BUSY__CE_OP_PIPE8_BUSY__SHIFT 0x18 +#define VPEC_CE_BUSY__CE_OP_PIPE9_BUSY__SHIFT 0x19 +#define VPEC_CE_BUSY__CE_IP_PIPE0_BUSY_MASK 0x00000001L +#define VPEC_CE_BUSY__CE_IP_PIPE1_BUSY_MASK 0x00000002L +#define VPEC_CE_BUSY__CE_IP_PIPE2_BUSY_MASK 0x00000004L +#define VPEC_CE_BUSY__CE_IP_PIPE3_BUSY_MASK 0x00000008L +#define VPEC_CE_BUSY__CE_IP_PIPE4_BUSY_MASK 0x00000010L +#define VPEC_CE_BUSY__CE_IP_PIPE5_BUSY_MASK 0x00000020L +#define VPEC_CE_BUSY__CE_OP_PIPE0_BUSY_MASK 0x00010000L +#define VPEC_CE_BUSY__CE_OP_PIPE1_BUSY_MASK 0x00020000L +#define VPEC_CE_BUSY__CE_OP_PIPE2_BUSY_MASK 0x00040000L +#define VPEC_CE_BUSY__CE_OP_PIPE3_BUSY_MASK 0x00080000L +#define VPEC_CE_BUSY__CE_OP_PIPE4_BUSY_MASK 0x00100000L +#define VPEC_CE_BUSY__CE_OP_PIPE5_BUSY_MASK 0x00200000L +#define VPEC_CE_BUSY__CE_OP_PIPE6_BUSY_MASK 0x00400000L +#define VPEC_CE_BUSY__CE_OP_PIPE7_BUSY_MASK 0x00800000L +#define VPEC_CE_BUSY__CE_OP_PIPE8_BUSY_MASK 0x01000000L +#define VPEC_CE_BUSY__CE_OP_PIPE9_BUSY_MASK 0x02000000L +//VPEC_F32_COUNTER +#define VPEC_F32_COUNTER__VALUE__SHIFT 0x0 +#define VPEC_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL +//VPEC_HOLE_ADDR_LO +#define VPEC_HOLE_ADDR_LO__VALUE__SHIFT 0x0 +#define VPEC_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL +//VPEC_HOLE_ADDR_HI +#define VPEC_HOLE_ADDR_HI__VALUE__SHIFT 0x0 +#define VPEC_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL +//VPEC_ERROR_LOG +#define VPEC_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define VPEC_ERROR_LOG__STATUS__SHIFT 0x10 +#define VPEC_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define VPEC_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//VPEC_INT_STATUS +#define VPEC_INT_STATUS__DATA__SHIFT 0x0 +#define VPEC_INT_STATUS__DATA_MASK 0xFFFFFFFFL +//VPEC_STATUS +#define VPEC_STATUS__IDLE__SHIFT 0x0 +#define VPEC_STATUS__REG_IDLE__SHIFT 0x1 +#define VPEC_STATUS__RB_EMPTY__SHIFT 0x2 +#define VPEC_STATUS__RB_FULL__SHIFT 0x3 +#define VPEC_STATUS__RB_CMD_IDLE__SHIFT 0x4 +#define VPEC_STATUS__RB_CMD_FULL__SHIFT 0x5 +#define VPEC_STATUS__IB_CMD_IDLE__SHIFT 0x6 +#define VPEC_STATUS__IB_CMD_FULL__SHIFT 0x7 +#define VPEC_STATUS__BLOCK_IDLE__SHIFT 0x8 +#define VPEC_STATUS__INSIDE_VPEP_CONFIG__SHIFT 0x9 +#define VPEC_STATUS__EX_IDLE__SHIFT 0xa +#define VPEC_STATUS__INSIDE_VPEP_3DLUT_CONFIG__SHIFT 0xb +#define VPEC_STATUS__PACKET_READY__SHIFT 0xc +#define VPEC_STATUS__MC_WR_IDLE__SHIFT 0xd +#define VPEC_STATUS__SRBM_IDLE__SHIFT 0xe +#define VPEC_STATUS__CONTEXT_EMPTY__SHIFT 0xf +#define VPEC_STATUS__INSIDE_IB__SHIFT 0x10 +#define VPEC_STATUS__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define VPEC_STATUS__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define VPEC_STATUS__MC_RD_IDLE__SHIFT 0x13 +#define VPEC_STATUS__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define VPEC_STATUS__MC_RD_RET_STALL__SHIFT 0x15 +#define VPEC_STATUS__LUTIB_CMD_IDLE__SHIFT 0x16 +#define VPEC_STATUS__LUTIB_CMD_FULL__SHIFT 0x17 +#define VPEC_STATUS__CMDIB_MC_RREQ_IDLE__SHIFT 0x18 +#define VPEC_STATUS__PREV_CMD_IDLE__SHIFT 0x19 +#define VPEC_STATUS__CMDIB_CMD_IDLE__SHIFT 0x1a +#define VPEC_STATUS__CMDIB_CMD_FULL__SHIFT 0x1b +#define VPEC_STATUS__RESERVED_29_28__SHIFT 0x1c +#define VPEC_STATUS__INT_IDLE__SHIFT 0x1e +#define VPEC_STATUS__INT_REQ_STALL__SHIFT 0x1f +#define VPEC_STATUS__IDLE_MASK 0x00000001L +#define VPEC_STATUS__REG_IDLE_MASK 0x00000002L +#define VPEC_STATUS__RB_EMPTY_MASK 0x00000004L +#define VPEC_STATUS__RB_FULL_MASK 0x00000008L +#define VPEC_STATUS__RB_CMD_IDLE_MASK 0x00000010L +#define VPEC_STATUS__RB_CMD_FULL_MASK 0x00000020L +#define VPEC_STATUS__IB_CMD_IDLE_MASK 0x00000040L +#define VPEC_STATUS__IB_CMD_FULL_MASK 0x00000080L +#define VPEC_STATUS__BLOCK_IDLE_MASK 0x00000100L +#define VPEC_STATUS__INSIDE_VPEP_CONFIG_MASK 0x00000200L +#define VPEC_STATUS__EX_IDLE_MASK 0x00000400L +#define VPEC_STATUS__INSIDE_VPEP_3DLUT_CONFIG_MASK 0x00000800L +#define VPEC_STATUS__PACKET_READY_MASK 0x00001000L +#define VPEC_STATUS__MC_WR_IDLE_MASK 0x00002000L +#define VPEC_STATUS__SRBM_IDLE_MASK 0x00004000L +#define VPEC_STATUS__CONTEXT_EMPTY_MASK 0x00008000L +#define VPEC_STATUS__INSIDE_IB_MASK 0x00010000L +#define VPEC_STATUS__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define VPEC_STATUS__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define VPEC_STATUS__MC_RD_IDLE_MASK 0x00080000L +#define VPEC_STATUS__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define VPEC_STATUS__MC_RD_RET_STALL_MASK 0x00200000L +#define VPEC_STATUS__LUTIB_CMD_IDLE_MASK 0x00400000L +#define VPEC_STATUS__LUTIB_CMD_FULL_MASK 0x00800000L +#define VPEC_STATUS__CMDIB_MC_RREQ_IDLE_MASK 0x01000000L +#define VPEC_STATUS__PREV_CMD_IDLE_MASK 0x02000000L +#define VPEC_STATUS__CMDIB_CMD_IDLE_MASK 0x04000000L +#define VPEC_STATUS__CMDIB_CMD_FULL_MASK 0x08000000L +#define VPEC_STATUS__RESERVED_29_28_MASK 0x30000000L +#define VPEC_STATUS__INT_IDLE_MASK 0x40000000L +#define VPEC_STATUS__INT_REQ_STALL_MASK 0x80000000L +//VPEC_STATUS1 +#define VPEC_STATUS1__EX_START__SHIFT 0x0 +#define VPEC_STATUS1__VPEC_IDLE__SHIFT 0x1 +#define VPEC_STATUS1__RESERVED_31_2__SHIFT 0x2 +#define VPEC_STATUS1__EX_START_MASK 0x00000001L +#define VPEC_STATUS1__VPEC_IDLE_MASK 0x00000002L +#define VPEC_STATUS1__RESERVED_31_2_MASK 0xFFFFFFFCL +//VPEC_STATUS2 +#define VPEC_STATUS2__ID__SHIFT 0x0 +#define VPEC_STATUS2__TH0F32_INSTR_PTR__SHIFT 0x2 +#define VPEC_STATUS2__CMD_OP__SHIFT 0x10 +#define VPEC_STATUS2__ID_MASK 0x00000003L +#define VPEC_STATUS2__TH0F32_INSTR_PTR_MASK 0x0000FFFCL +#define VPEC_STATUS2__CMD_OP_MASK 0xFFFF0000L +//VPEC_STATUS3 +#define VPEC_STATUS3__RESERVED_15_0__SHIFT 0x0 +#define VPEC_STATUS3__RESERVED_19_16__SHIFT 0x10 +#define VPEC_STATUS3__EXCEPTION_IDLE__SHIFT 0x14 +#define VPEC_STATUS3__RESERVED_21_21__SHIFT 0x15 +#define VPEC_STATUS3__RESERVED_22_22__SHIFT 0x16 +#define VPEC_STATUS3__RESERVED_23_23__SHIFT 0x17 +#define VPEC_STATUS3__RESERVED_24_24__SHIFT 0x18 +#define VPEC_STATUS3__RESERVED_25_25__SHIFT 0x19 +#define VPEC_STATUS3__INT_QUEUE_ID__SHIFT 0x1a +#define VPEC_STATUS3__RESERVED_31_30__SHIFT 0x1e +#define VPEC_STATUS3__RESERVED_15_0_MASK 0x0000FFFFL +#define VPEC_STATUS3__RESERVED_19_16_MASK 0x000F0000L +#define VPEC_STATUS3__EXCEPTION_IDLE_MASK 0x00100000L +#define VPEC_STATUS3__RESERVED_21_21_MASK 0x00200000L +#define VPEC_STATUS3__RESERVED_22_22_MASK 0x00400000L +#define VPEC_STATUS3__RESERVED_23_23_MASK 0x00800000L +#define VPEC_STATUS3__RESERVED_24_24_MASK 0x01000000L +#define VPEC_STATUS3__RESERVED_25_25_MASK 0x02000000L +#define VPEC_STATUS3__INT_QUEUE_ID_MASK 0x3C000000L +#define VPEC_STATUS3__RESERVED_31_30_MASK 0xC0000000L +//VPEC_STATUS4 +#define VPEC_STATUS4__IDLE__SHIFT 0x0 +#define VPEC_STATUS4__IH_OUTSTANDING__SHIFT 0x2 +#define VPEC_STATUS4__RESERVED_3_3__SHIFT 0x3 +#define VPEC_STATUS4__CH_RD_OUTSTANDING__SHIFT 0x4 +#define VPEC_STATUS4__CH_WR_OUTSTANDING__SHIFT 0x5 +#define VPEC_STATUS4__RESERVED_6_6__SHIFT 0x6 +#define VPEC_STATUS4__RESERVED_7_7__SHIFT 0x7 +#define VPEC_STATUS4__RESERVED_8_8__SHIFT 0x8 +#define VPEC_STATUS4__RESERVED_9_9__SHIFT 0x9 +#define VPEC_STATUS4__REG_POLLING__SHIFT 0xa +#define VPEC_STATUS4__MEM_POLLING__SHIFT 0xb +#define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING__SHIFT 0xc +#define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING__SHIFT 0xd +#define VPEC_STATUS4__RESERVED_15_14__SHIFT 0xe +#define VPEC_STATUS4__ACTIVE_QUEUE_ID__SHIFT 0x10 +#define VPEC_STATUS4__RESERVED_27_20__SHIFT 0x14 +#define VPEC_STATUS4__IDLE_MASK 0x00000001L +#define VPEC_STATUS4__IH_OUTSTANDING_MASK 0x00000004L +#define VPEC_STATUS4__RESERVED_3_3_MASK 0x00000008L +#define VPEC_STATUS4__CH_RD_OUTSTANDING_MASK 0x00000010L +#define VPEC_STATUS4__CH_WR_OUTSTANDING_MASK 0x00000020L +#define VPEC_STATUS4__RESERVED_6_6_MASK 0x00000040L +#define VPEC_STATUS4__RESERVED_7_7_MASK 0x00000080L +#define VPEC_STATUS4__RESERVED_8_8_MASK 0x00000100L +#define VPEC_STATUS4__RESERVED_9_9_MASK 0x00000200L +#define VPEC_STATUS4__REG_POLLING_MASK 0x00000400L +#define VPEC_STATUS4__MEM_POLLING_MASK 0x00000800L +#define VPEC_STATUS4__VPEP_REG_RD_OUTSTANDING_MASK 0x00001000L +#define VPEC_STATUS4__VPEP_REG_WR_OUTSTANDING_MASK 0x00002000L +#define VPEC_STATUS4__RESERVED_15_14_MASK 0x0000C000L +#define VPEC_STATUS4__ACTIVE_QUEUE_ID_MASK 0x000F0000L +#define VPEC_STATUS4__RESERVED_27_20_MASK 0x0FF00000L +//VPEC_STATUS5 +#define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 +#define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 +#define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 +#define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 +#define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 +#define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 +#define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 +#define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 +#define VPEC_STATUS5__RESERVED_27_16__SHIFT 0x10 +#define VPEC_STATUS5__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L +#define VPEC_STATUS5__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L +#define VPEC_STATUS5__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L +#define VPEC_STATUS5__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L +#define VPEC_STATUS5__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L +#define VPEC_STATUS5__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L +#define VPEC_STATUS5__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L +#define VPEC_STATUS5__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L +#define VPEC_STATUS5__RESERVED_27_16_MASK 0x000F0000L +//VPEC_STATUS6 +#define VPEC_STATUS6__ID__SHIFT 0x0 +#define VPEC_STATUS6__TH1F32_INSTR_PTR__SHIFT 0x2 +#define VPEC_STATUS6__TH1_EXCEPTION__SHIFT 0x10 +#define VPEC_STATUS6__ID_MASK 0x00000003L +#define VPEC_STATUS6__TH1F32_INSTR_PTR_MASK 0x0000FFFCL +#define VPEC_STATUS6__TH1_EXCEPTION_MASK 0xFFFF0000L +//VPEC_STATUS7 +#define VPEC_STATUS7__TH0_DBG_STATUS__SHIFT 0x0 +#define VPEC_STATUS7__TH0_DBG_STATUS_MASK 0xFFFFFFFFL +//VPEC_STATUS8 +#define VPEC_STATUS8__CE_IP0_WREQ_IDLE__SHIFT 0x0 +#define VPEC_STATUS8__CE_IP0_WR_IDLE__SHIFT 0x1 +#define VPEC_STATUS8__CE_IP0_SPLIT_RD_IDLE__SHIFT 0x2 +#define VPEC_STATUS8__CE_IP0_SPLIT_WR_IDLE__SHIFT 0x3 +#define VPEC_STATUS8__CE_IP0_RREQ_IDLE__SHIFT 0x4 +#define VPEC_STATUS8__CE_IP0_OUT_IDLE__SHIFT 0x5 +#define VPEC_STATUS8__CE_IP0_IN_IDLE__SHIFT 0x6 +#define VPEC_STATUS8__CE_IP0_DST_IDLE__SHIFT 0x7 +#define VPEC_STATUS8__CE_IP0_CMD_IDLE__SHIFT 0x8 +#define VPEC_STATUS8__CE_IP1_WREQ_IDLE__SHIFT 0x9 +#define VPEC_STATUS8__CE_IP1_WR_IDLE__SHIFT 0xa +#define VPEC_STATUS8__CE_IP1_SPLIT_RD_IDLE__SHIFT 0xb +#define VPEC_STATUS8__CE_IP1_SPLIT_WR_IDLE__SHIFT 0xc +#define VPEC_STATUS8__CE_IP1_RREQ_IDLE__SHIFT 0xd +#define VPEC_STATUS8__CE_IP1_OUT_IDLE__SHIFT 0xe +#define VPEC_STATUS8__CE_IP1_IN_IDLE__SHIFT 0xf +#define VPEC_STATUS8__CE_IP1_DST_IDLE__SHIFT 0x10 +#define VPEC_STATUS8__CE_IP1_CMD_IDLE__SHIFT 0x11 +#define VPEC_STATUS8__CE_IP0_AFIFO_FULL__SHIFT 0x12 +#define VPEC_STATUS8__CE_IP0_CMD_INFO_FULL__SHIFT 0x13 +#define VPEC_STATUS8__CE_IP0_CMD_INFO1_FULL__SHIFT 0x14 +#define VPEC_STATUS8__CE_IP1_AFIFO_FULL__SHIFT 0x15 +#define VPEC_STATUS8__CE_IP1_CMD_INFO_FULL__SHIFT 0x16 +#define VPEC_STATUS8__CE_IP1_CMD_INFO1_FULL__SHIFT 0x17 +#define VPEC_STATUS8__CE_IP0_WR_STALL__SHIFT 0x18 +#define VPEC_STATUS8__CE_IP1_WR_STALL__SHIFT 0x19 +#define VPEC_STATUS8__CE_IP0_RD_STALL__SHIFT 0x1a +#define VPEC_STATUS8__CE_IP1_RD_STALL__SHIFT 0x1b +#define VPEC_STATUS8__RESERVED_31_28__SHIFT 0x1c +#define VPEC_STATUS8__CE_IP0_WREQ_IDLE_MASK 0x00000001L +#define VPEC_STATUS8__CE_IP0_WR_IDLE_MASK 0x00000002L +#define VPEC_STATUS8__CE_IP0_SPLIT_RD_IDLE_MASK 0x00000004L +#define VPEC_STATUS8__CE_IP0_SPLIT_WR_IDLE_MASK 0x00000008L +#define VPEC_STATUS8__CE_IP0_RREQ_IDLE_MASK 0x00000010L +#define VPEC_STATUS8__CE_IP0_OUT_IDLE_MASK 0x00000020L +#define VPEC_STATUS8__CE_IP0_IN_IDLE_MASK 0x00000040L +#define VPEC_STATUS8__CE_IP0_DST_IDLE_MASK 0x00000080L +#define VPEC_STATUS8__CE_IP0_CMD_IDLE_MASK 0x00000100L +#define VPEC_STATUS8__CE_IP1_WREQ_IDLE_MASK 0x00000200L +#define VPEC_STATUS8__CE_IP1_WR_IDLE_MASK 0x00000400L +#define VPEC_STATUS8__CE_IP1_SPLIT_RD_IDLE_MASK 0x00000800L +#define VPEC_STATUS8__CE_IP1_SPLIT_WR_IDLE_MASK 0x00001000L +#define VPEC_STATUS8__CE_IP1_RREQ_IDLE_MASK 0x00002000L +#define VPEC_STATUS8__CE_IP1_OUT_IDLE_MASK 0x00004000L +#define VPEC_STATUS8__CE_IP1_IN_IDLE_MASK 0x00008000L +#define VPEC_STATUS8__CE_IP1_DST_IDLE_MASK 0x00010000L +#define VPEC_STATUS8__CE_IP1_CMD_IDLE_MASK 0x00020000L +#define VPEC_STATUS8__CE_IP0_AFIFO_FULL_MASK 0x00040000L +#define VPEC_STATUS8__CE_IP0_CMD_INFO_FULL_MASK 0x00080000L +#define VPEC_STATUS8__CE_IP0_CMD_INFO1_FULL_MASK 0x00100000L +#define VPEC_STATUS8__CE_IP1_AFIFO_FULL_MASK 0x00200000L +#define VPEC_STATUS8__CE_IP1_CMD_INFO_FULL_MASK 0x00400000L +#define VPEC_STATUS8__CE_IP1_CMD_INFO1_FULL_MASK 0x00800000L +#define VPEC_STATUS8__CE_IP0_WR_STALL_MASK 0x01000000L +#define VPEC_STATUS8__CE_IP1_WR_STALL_MASK 0x02000000L +#define VPEC_STATUS8__CE_IP0_RD_STALL_MASK 0x04000000L +#define VPEC_STATUS8__CE_IP1_RD_STALL_MASK 0x08000000L +#define VPEC_STATUS8__RESERVED_31_28_MASK 0xF0000000L +//VPEC_STATUS9 +#define VPEC_STATUS9__CE_IP2_WREQ_IDLE__SHIFT 0x0 +#define VPEC_STATUS9__CE_IP2_WR_IDLE__SHIFT 0x1 +#define VPEC_STATUS9__CE_IP2_SPLIT_RD_IDLE__SHIFT 0x2 +#define VPEC_STATUS9__CE_IP2_SPLIT_WR_IDLE__SHIFT 0x3 +#define VPEC_STATUS9__CE_IP2_RREQ_IDLE__SHIFT 0x4 +#define VPEC_STATUS9__CE_IP2_OUT_IDLE__SHIFT 0x5 +#define VPEC_STATUS9__CE_IP2_IN_IDLE__SHIFT 0x6 +#define VPEC_STATUS9__CE_IP2_DST_IDLE__SHIFT 0x7 +#define VPEC_STATUS9__CE_IP2_CMD_IDLE__SHIFT 0x8 +#define VPEC_STATUS9__CE_IP3_WREQ_IDLE__SHIFT 0x9 +#define VPEC_STATUS9__CE_IP3_WR_IDLE__SHIFT 0xa +#define VPEC_STATUS9__CE_IP3_SPLIT_RD_IDLE__SHIFT 0xb +#define VPEC_STATUS9__CE_IP3_SPLIT_WR_IDLE__SHIFT 0xc +#define VPEC_STATUS9__CE_IP3_RREQ_IDLE__SHIFT 0xd +#define VPEC_STATUS9__CE_IP3_OUT_IDLE__SHIFT 0xe +#define VPEC_STATUS9__CE_IP3_IN_IDLE__SHIFT 0xf +#define VPEC_STATUS9__CE_IP3_DST_IDLE__SHIFT 0x10 +#define VPEC_STATUS9__CE_IP3_CMD_IDLE__SHIFT 0x11 +#define VPEC_STATUS9__CE_IP2_AFIFO_FULL__SHIFT 0x12 +#define VPEC_STATUS9__CE_IP2_CMD_INFO_FULL__SHIFT 0x13 +#define VPEC_STATUS9__CE_IP2_CMD_INFO1_FULL__SHIFT 0x14 +#define VPEC_STATUS9__CE_IP3_AFIFO_FULL__SHIFT 0x15 +#define VPEC_STATUS9__CE_IP3_CMD_INFO_FULL__SHIFT 0x16 +#define VPEC_STATUS9__CE_IP3_CMD_INFO1_FULL__SHIFT 0x17 +#define VPEC_STATUS9__CE_IP2_WR_STALL__SHIFT 0x18 +#define VPEC_STATUS9__CE_IP3_WR_STALL__SHIFT 0x19 +#define VPEC_STATUS9__CE_IP2_RD_STALL__SHIFT 0x1a +#define VPEC_STATUS9__CE_IP3_RD_STALL__SHIFT 0x1b +#define VPEC_STATUS9__RESERVED_31_28__SHIFT 0x1c +#define VPEC_STATUS9__CE_IP2_WREQ_IDLE_MASK 0x00000001L +#define VPEC_STATUS9__CE_IP2_WR_IDLE_MASK 0x00000002L +#define VPEC_STATUS9__CE_IP2_SPLIT_RD_IDLE_MASK 0x00000004L +#define VPEC_STATUS9__CE_IP2_SPLIT_WR_IDLE_MASK 0x00000008L +#define VPEC_STATUS9__CE_IP2_RREQ_IDLE_MASK 0x00000010L +#define VPEC_STATUS9__CE_IP2_OUT_IDLE_MASK 0x00000020L +#define VPEC_STATUS9__CE_IP2_IN_IDLE_MASK 0x00000040L +#define VPEC_STATUS9__CE_IP2_DST_IDLE_MASK 0x00000080L +#define VPEC_STATUS9__CE_IP2_CMD_IDLE_MASK 0x00000100L +#define VPEC_STATUS9__CE_IP3_WREQ_IDLE_MASK 0x00000200L +#define VPEC_STATUS9__CE_IP3_WR_IDLE_MASK 0x00000400L +#define VPEC_STATUS9__CE_IP3_SPLIT_RD_IDLE_MASK 0x00000800L +#define VPEC_STATUS9__CE_IP3_SPLIT_WR_IDLE_MASK 0x00001000L +#define VPEC_STATUS9__CE_IP3_RREQ_IDLE_MASK 0x00002000L +#define VPEC_STATUS9__CE_IP3_OUT_IDLE_MASK 0x00004000L +#define VPEC_STATUS9__CE_IP3_IN_IDLE_MASK 0x00008000L +#define VPEC_STATUS9__CE_IP3_DST_IDLE_MASK 0x00010000L +#define VPEC_STATUS9__CE_IP3_CMD_IDLE_MASK 0x00020000L +#define VPEC_STATUS9__CE_IP2_AFIFO_FULL_MASK 0x00040000L +#define VPEC_STATUS9__CE_IP2_CMD_INFO_FULL_MASK 0x00080000L +#define VPEC_STATUS9__CE_IP2_CMD_INFO1_FULL_MASK 0x00100000L +#define VPEC_STATUS9__CE_IP3_AFIFO_FULL_MASK 0x00200000L +#define VPEC_STATUS9__CE_IP3_CMD_INFO_FULL_MASK 0x00400000L +#define VPEC_STATUS9__CE_IP3_CMD_INFO1_FULL_MASK 0x00800000L +#define VPEC_STATUS9__CE_IP2_WR_STALL_MASK 0x01000000L +#define VPEC_STATUS9__CE_IP3_WR_STALL_MASK 0x02000000L +#define VPEC_STATUS9__CE_IP2_RD_STALL_MASK 0x04000000L +#define VPEC_STATUS9__CE_IP3_RD_STALL_MASK 0x08000000L +#define VPEC_STATUS9__RESERVED_31_28_MASK 0xF0000000L +//VPEC_STATUS10 +#define VPEC_STATUS10__CE_OP0_WR_IDLE__SHIFT 0x0 +#define VPEC_STATUS10__CE_OP0_CMD_IDLE__SHIFT 0x1 +#define VPEC_STATUS10__CE_OP1_WR_IDLE__SHIFT 0x2 +#define VPEC_STATUS10__CE_OP1_CMD_IDLE__SHIFT 0x3 +#define VPEC_STATUS10__CE_OP2_WR_IDLE__SHIFT 0x4 +#define VPEC_STATUS10__CE_OP2_CMD_IDLE__SHIFT 0x5 +#define VPEC_STATUS10__CE_OP3_WR_IDLE__SHIFT 0x6 +#define VPEC_STATUS10__CE_OP3_CMD_IDLE__SHIFT 0x7 +#define VPEC_STATUS10__CE_OP4_WR_IDLE__SHIFT 0x8 +#define VPEC_STATUS10__CE_OP4_CMD_IDLE__SHIFT 0x9 +#define VPEC_STATUS10__CE_OP5_WR_IDLE__SHIFT 0xa +#define VPEC_STATUS10__CE_OP5_CMD_IDLE__SHIFT 0xb +#define VPEC_STATUS10__CE_OP6_WR_IDLE__SHIFT 0xc +#define VPEC_STATUS10__CE_OP6_CMD_IDLE__SHIFT 0xd +#define VPEC_STATUS10__CE_OP7_WR_IDLE__SHIFT 0xe +#define VPEC_STATUS10__CE_OP7_CMD_IDLE__SHIFT 0xf +#define VPEC_STATUS10__CE_OP8_WR_IDLE__SHIFT 0x10 +#define VPEC_STATUS10__CE_OP8_CMD_IDLE__SHIFT 0x11 +#define VPEC_STATUS10__CE_OP9_WR_IDLE__SHIFT 0x12 +#define VPEC_STATUS10__CE_OP9_CMD_IDLE__SHIFT 0x13 +#define VPEC_STATUS10__RESERVED_31_28__SHIFT 0x1c +#define VPEC_STATUS10__CE_OP0_WR_IDLE_MASK 0x00000001L +#define VPEC_STATUS10__CE_OP0_CMD_IDLE_MASK 0x00000002L +#define VPEC_STATUS10__CE_OP1_WR_IDLE_MASK 0x00000004L +#define VPEC_STATUS10__CE_OP1_CMD_IDLE_MASK 0x00000008L +#define VPEC_STATUS10__CE_OP2_WR_IDLE_MASK 0x00000010L +#define VPEC_STATUS10__CE_OP2_CMD_IDLE_MASK 0x00000020L +#define VPEC_STATUS10__CE_OP3_WR_IDLE_MASK 0x00000040L +#define VPEC_STATUS10__CE_OP3_CMD_IDLE_MASK 0x00000080L +#define VPEC_STATUS10__CE_OP4_WR_IDLE_MASK 0x00000100L +#define VPEC_STATUS10__CE_OP4_CMD_IDLE_MASK 0x00000200L +#define VPEC_STATUS10__CE_OP5_WR_IDLE_MASK 0x00000400L +#define VPEC_STATUS10__CE_OP5_CMD_IDLE_MASK 0x00000800L +#define VPEC_STATUS10__CE_OP6_WR_IDLE_MASK 0x00001000L +#define VPEC_STATUS10__CE_OP6_CMD_IDLE_MASK 0x00002000L +#define VPEC_STATUS10__CE_OP7_WR_IDLE_MASK 0x00004000L +#define VPEC_STATUS10__CE_OP7_CMD_IDLE_MASK 0x00008000L +#define VPEC_STATUS10__CE_OP8_WR_IDLE_MASK 0x00010000L +#define VPEC_STATUS10__CE_OP8_CMD_IDLE_MASK 0x00020000L +#define VPEC_STATUS10__CE_OP9_WR_IDLE_MASK 0x00040000L +#define VPEC_STATUS10__CE_OP9_CMD_IDLE_MASK 0x00080000L +#define VPEC_STATUS10__RESERVED_31_28_MASK 0xF0000000L +//VPEC_STATUS_DCC +#define VPEC_STATUS_DCC__CE_IP0_MRQ_IDLE__SHIFT 0x0 +#define VPEC_STATUS_DCC__CE_IP0_DCCP_IDLE__SHIFT 0x1 +#define VPEC_STATUS_DCC__CE_IP0_DCC_RET_IDLE__SHIFT 0x2 +#define VPEC_STATUS_DCC__CE_IP1_MRQ_IDLE__SHIFT 0x3 +#define VPEC_STATUS_DCC__CE_IP1_DCCP_IDLE__SHIFT 0x4 +#define VPEC_STATUS_DCC__CE_IP1_DCC_RET_IDLE__SHIFT 0x5 +#define VPEC_STATUS_DCC__CE_IP2_MRQ_IDLE__SHIFT 0x6 +#define VPEC_STATUS_DCC__CE_IP2_DCCP_IDLE__SHIFT 0x7 +#define VPEC_STATUS_DCC__CE_IP2_DCC_RET_IDLE__SHIFT 0x8 +#define VPEC_STATUS_DCC__CE_IP3_MRQ_IDLE__SHIFT 0x9 +#define VPEC_STATUS_DCC__CE_IP3_DCCP_IDLE__SHIFT 0xa +#define VPEC_STATUS_DCC__CE_IP3_DCC_RET_IDLE__SHIFT 0xb +#define VPEC_STATUS_DCC__CE_IP4_MRQ_IDLE__SHIFT 0xc +#define VPEC_STATUS_DCC__CE_IP4_DCCP_IDLE__SHIFT 0xd +#define VPEC_STATUS_DCC__CE_IP4_DCC_RET_IDLE__SHIFT 0xe +#define VPEC_STATUS_DCC__CE_IP5_MRQ_IDLE__SHIFT 0xf +#define VPEC_STATUS_DCC__CE_IP5_DCCP_IDLE__SHIFT 0x10 +#define VPEC_STATUS_DCC__CE_IP5_DCC_RET_IDLE__SHIFT 0x11 +#define VPEC_STATUS_DCC__RESERVED_31_18__SHIFT 0x12 +#define VPEC_STATUS_DCC__CE_IP0_MRQ_IDLE_MASK 0x00000001L +#define VPEC_STATUS_DCC__CE_IP0_DCCP_IDLE_MASK 0x00000002L +#define VPEC_STATUS_DCC__CE_IP0_DCC_RET_IDLE_MASK 0x00000004L +#define VPEC_STATUS_DCC__CE_IP1_MRQ_IDLE_MASK 0x00000008L +#define VPEC_STATUS_DCC__CE_IP1_DCCP_IDLE_MASK 0x00000010L +#define VPEC_STATUS_DCC__CE_IP1_DCC_RET_IDLE_MASK 0x00000020L +#define VPEC_STATUS_DCC__CE_IP2_MRQ_IDLE_MASK 0x00000040L +#define VPEC_STATUS_DCC__CE_IP2_DCCP_IDLE_MASK 0x00000080L +#define VPEC_STATUS_DCC__CE_IP2_DCC_RET_IDLE_MASK 0x00000100L +#define VPEC_STATUS_DCC__CE_IP3_MRQ_IDLE_MASK 0x00000200L +#define VPEC_STATUS_DCC__CE_IP3_DCCP_IDLE_MASK 0x00000400L +#define VPEC_STATUS_DCC__CE_IP3_DCC_RET_IDLE_MASK 0x00000800L +#define VPEC_STATUS_DCC__CE_IP4_MRQ_IDLE_MASK 0x00001000L +#define VPEC_STATUS_DCC__CE_IP4_DCCP_IDLE_MASK 0x00002000L +#define VPEC_STATUS_DCC__CE_IP4_DCC_RET_IDLE_MASK 0x00004000L +#define VPEC_STATUS_DCC__CE_IP5_MRQ_IDLE_MASK 0x00008000L +#define VPEC_STATUS_DCC__CE_IP5_DCCP_IDLE_MASK 0x00010000L +#define VPEC_STATUS_DCC__CE_IP5_DCC_RET_IDLE_MASK 0x00020000L +#define VPEC_STATUS_DCC__RESERVED_31_18_MASK 0xFFFC0000L +//VPEC_STATUS11 +#define VPEC_STATUS11__CE_IP4_WREQ_IDLE__SHIFT 0x0 +#define VPEC_STATUS11__CE_IP4_WR_IDLE__SHIFT 0x1 +#define VPEC_STATUS11__CE_IP4_SPLIT_RD_IDLE__SHIFT 0x2 +#define VPEC_STATUS11__CE_IP4_SPLIT_WR_IDLE__SHIFT 0x3 +#define VPEC_STATUS11__CE_IP4_RREQ_IDLE__SHIFT 0x4 +#define VPEC_STATUS11__CE_IP4_OUT_IDLE__SHIFT 0x5 +#define VPEC_STATUS11__CE_IP4_IN_IDLE__SHIFT 0x6 +#define VPEC_STATUS11__CE_IP4_DST_IDLE__SHIFT 0x7 +#define VPEC_STATUS11__CE_IP4_CMD_IDLE__SHIFT 0x8 +#define VPEC_STATUS11__CE_IP5_WREQ_IDLE__SHIFT 0x9 +#define VPEC_STATUS11__CE_IP5_WR_IDLE__SHIFT 0xa +#define VPEC_STATUS11__CE_IP5_SPLIT_RD_IDLE__SHIFT 0xb +#define VPEC_STATUS11__CE_IP5_SPLIT_WR_IDLE__SHIFT 0xc +#define VPEC_STATUS11__CE_IP5_RREQ_IDLE__SHIFT 0xd +#define VPEC_STATUS11__CE_IP5_OUT_IDLE__SHIFT 0xe +#define VPEC_STATUS11__CE_IP5_IN_IDLE__SHIFT 0xf +#define VPEC_STATUS11__CE_IP5_DST_IDLE__SHIFT 0x10 +#define VPEC_STATUS11__CE_IP5_CMD_IDLE__SHIFT 0x11 +#define VPEC_STATUS11__CE_IP4_AFIFO_FULL__SHIFT 0x12 +#define VPEC_STATUS11__CE_IP4_CMD_INFO_FULL__SHIFT 0x13 +#define VPEC_STATUS11__CE_IP4_CMD_INFO1_FULL__SHIFT 0x14 +#define VPEC_STATUS11__CE_IP5_AFIFO_FULL__SHIFT 0x15 +#define VPEC_STATUS11__CE_IP5_CMD_INFO_FULL__SHIFT 0x16 +#define VPEC_STATUS11__CE_IP5_CMD_INFO1_FULL__SHIFT 0x17 +#define VPEC_STATUS11__CE_IP4_WR_STALL__SHIFT 0x18 +#define VPEC_STATUS11__CE_IP5_WR_STALL__SHIFT 0x19 +#define VPEC_STATUS11__CE_IP4_RD_STALL__SHIFT 0x1a +#define VPEC_STATUS11__CE_IP5_RD_STALL__SHIFT 0x1b +#define VPEC_STATUS11__RESERVED_31_28__SHIFT 0x1c +#define VPEC_STATUS11__CE_IP4_WREQ_IDLE_MASK 0x00000001L +#define VPEC_STATUS11__CE_IP4_WR_IDLE_MASK 0x00000002L +#define VPEC_STATUS11__CE_IP4_SPLIT_RD_IDLE_MASK 0x00000004L +#define VPEC_STATUS11__CE_IP4_SPLIT_WR_IDLE_MASK 0x00000008L +#define VPEC_STATUS11__CE_IP4_RREQ_IDLE_MASK 0x00000010L +#define VPEC_STATUS11__CE_IP4_OUT_IDLE_MASK 0x00000020L +#define VPEC_STATUS11__CE_IP4_IN_IDLE_MASK 0x00000040L +#define VPEC_STATUS11__CE_IP4_DST_IDLE_MASK 0x00000080L +#define VPEC_STATUS11__CE_IP4_CMD_IDLE_MASK 0x00000100L +#define VPEC_STATUS11__CE_IP5_WREQ_IDLE_MASK 0x00000200L +#define VPEC_STATUS11__CE_IP5_WR_IDLE_MASK 0x00000400L +#define VPEC_STATUS11__CE_IP5_SPLIT_RD_IDLE_MASK 0x00000800L +#define VPEC_STATUS11__CE_IP5_SPLIT_WR_IDLE_MASK 0x00001000L +#define VPEC_STATUS11__CE_IP5_RREQ_IDLE_MASK 0x00002000L +#define VPEC_STATUS11__CE_IP5_OUT_IDLE_MASK 0x00004000L +#define VPEC_STATUS11__CE_IP5_IN_IDLE_MASK 0x00008000L +#define VPEC_STATUS11__CE_IP5_DST_IDLE_MASK 0x00010000L +#define VPEC_STATUS11__CE_IP5_CMD_IDLE_MASK 0x00020000L +#define VPEC_STATUS11__CE_IP4_AFIFO_FULL_MASK 0x00040000L +#define VPEC_STATUS11__CE_IP4_CMD_INFO_FULL_MASK 0x00080000L +#define VPEC_STATUS11__CE_IP4_CMD_INFO1_FULL_MASK 0x00100000L +#define VPEC_STATUS11__CE_IP5_AFIFO_FULL_MASK 0x00200000L +#define VPEC_STATUS11__CE_IP5_CMD_INFO_FULL_MASK 0x00400000L +#define VPEC_STATUS11__CE_IP5_CMD_INFO1_FULL_MASK 0x00800000L +#define VPEC_STATUS11__CE_IP4_WR_STALL_MASK 0x01000000L +#define VPEC_STATUS11__CE_IP5_WR_STALL_MASK 0x02000000L +#define VPEC_STATUS11__CE_IP4_RD_STALL_MASK 0x04000000L +#define VPEC_STATUS11__CE_IP5_RD_STALL_MASK 0x08000000L +#define VPEC_STATUS11__RESERVED_31_28_MASK 0xF0000000L +//VPEC_INST +#define VPEC_INST__ID__SHIFT 0x0 +#define VPEC_INST__RESERVED__SHIFT 0x3 +#define VPEC_INST__ID_MASK 0x00000007L +#define VPEC_INST__RESERVED_MASK 0xFFFFFFF8L +//VPEC_QUEUE_STATUS0 +#define VPEC_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 +#define VPEC_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 +#define VPEC_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 +#define VPEC_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc +#define VPEC_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 +#define VPEC_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 +#define VPEC_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 +#define VPEC_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c +#define VPEC_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL +#define VPEC_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L +#define VPEC_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L +#define VPEC_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L +#define VPEC_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L +#define VPEC_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L +#define VPEC_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L +#define VPEC_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L +//VPEC_QUEUE_HANG_STATUS +#define VPEC_QUEUE_HANG_STATUS__F30T0_HANG__SHIFT 0x0 +#define VPEC_QUEUE_HANG_STATUS__CE_HANG__SHIFT 0x1 +#define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH__SHIFT 0x2 +#define VPEC_QUEUE_HANG_STATUS__INVALID_PKT_FIELD__SHIFT 0x3 +#define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR__SHIFT 0x4 +#define VPEC_QUEUE_HANG_STATUS__F32_ACCESS_OFF_VPDPP1__SHIFT 0x5 +#define VPEC_QUEUE_HANG_STATUS__RSMU_ACCESS_OFF_VPDPP1__SHIFT 0x6 +#define VPEC_QUEUE_HANG_STATUS__EOH_MISMATCH__SHIFT 0x7 +#define VPEC_QUEUE_HANG_STATUS__F30T0_HANG_MASK 0x00000001L +#define VPEC_QUEUE_HANG_STATUS__CE_HANG_MASK 0x00000002L +#define VPEC_QUEUE_HANG_STATUS__EOF_MISMATCH_MASK 0x00000004L +#define VPEC_QUEUE_HANG_STATUS__INVALID_PKT_FIELD_MASK 0x00000008L +#define VPEC_QUEUE_HANG_STATUS__INVALID_VPEP_CONFIG_ADDR_MASK 0x00000010L +#define VPEC_QUEUE_HANG_STATUS__F32_ACCESS_OFF_VPDPP1_MASK 0x00000020L +#define VPEC_QUEUE_HANG_STATUS__RSMU_ACCESS_OFF_VPDPP1_MASK 0x00000040L +#define VPEC_QUEUE_HANG_STATUS__EOH_MISMATCH_MASK 0x00000080L +//VPEC_DPM_IDLE_TIME +#define VPEC_DPM_IDLE_TIME__VALUE__SHIFT 0x0 +#define VPEC_DPM_IDLE_TIME__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_BUSY_TIME +#define VPEC_DPM_BUSY_TIME__VALUE__SHIFT 0x0 +#define VPEC_DPM_BUSY_TIME__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_IDLE_START_LO +#define VPEC_DPM_IDLE_START_LO__VALUE__SHIFT 0x0 +#define VPEC_DPM_IDLE_START_LO__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_IDLE_START_HI +#define VPEC_DPM_IDLE_START_HI__VALUE__SHIFT 0x0 +#define VPEC_DPM_IDLE_START_HI__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_BUSY_START_LO +#define VPEC_DPM_BUSY_START_LO__VALUE__SHIFT 0x0 +#define VPEC_DPM_BUSY_START_LO__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_BUSY_START_HI +#define VPEC_DPM_BUSY_START_HI__VALUE__SHIFT 0x0 +#define VPEC_DPM_BUSY_START_HI__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_LAST_REQ_TIMESTAMP +#define VPEC_DPM_LAST_REQ_TIMESTAMP__VALUE__SHIFT 0x0 +#define VPEC_DPM_LAST_REQ_TIMESTAMP__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_NEW_JOB_DUMMY3 +#define VPEC_DPM_NEW_JOB_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_DPM_NEW_JOB_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_STATE +#define VPEC_DPM_STATE__VALUE__SHIFT 0x0 +#define VPEC_DPM_STATE__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM0_FREQ +#define VPEC_DPM0_FREQ__VALUE__SHIFT 0x0 +#define VPEC_DPM0_FREQ__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM1_FREQ +#define VPEC_DPM1_FREQ__VALUE__SHIFT 0x0 +#define VPEC_DPM1_FREQ__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM2_FREQ +#define VPEC_DPM2_FREQ__VALUE__SHIFT 0x0 +#define VPEC_DPM2_FREQ__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM3_FREQ +#define VPEC_DPM3_FREQ__VALUE__SHIFT 0x0 +#define VPEC_DPM3_FREQ__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_THRESHOLD_SKIP +#define VPEC_DPM_THRESHOLD_SKIP__VALUE__SHIFT 0x0 +#define VPEC_DPM_THRESHOLD_SKIP__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_THRESHOLD_BUSY_OVERFLOW +#define VPEC_DPM_THRESHOLD_BUSY_OVERFLOW__VALUE__SHIFT 0x0 +#define VPEC_DPM_THRESHOLD_BUSY_OVERFLOW__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_CALC_BUSY_IN_POSTPROCESS +#define VPEC_DPM_CALC_BUSY_IN_POSTPROCESS__VALUE__SHIFT 0x0 +#define VPEC_DPM_CALC_BUSY_IN_POSTPROCESS__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_IN_CHECKIDLE_LOOP +#define VPEC_DPM_IN_CHECKIDLE_LOOP__VALUE__SHIFT 0x0 +#define VPEC_DPM_IN_CHECKIDLE_LOOP__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_THRESHOLD_IDLE_OVERFLOW +#define VPEC_DPM_THRESHOLD_IDLE_OVERFLOW__VALUE__SHIFT 0x0 +#define VPEC_DPM_THRESHOLD_IDLE_OVERFLOW__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_BUSY_CLAMP_COUNT +#define VPEC_DPM_BUSY_CLAMP_COUNT__VALUE__SHIFT 0x0 +#define VPEC_DPM_BUSY_CLAMP_COUNT__VALUE_MASK 0xFFFFFFFFL +//VPEC_DPM_IDLE_CLAMP_COUNT +#define VPEC_DPM_IDLE_CLAMP_COUNT__VALUE__SHIFT 0x0 +#define VPEC_DPM_IDLE_CLAMP_COUNT__VALUE_MASK 0xFFFFFFFFL +//VPEC_PG_CNTL +#define VPEC_PG_CNTL__PG_EN__SHIFT 0x0 +#define VPEC_PG_CNTL__PG_HYSTERESIS__SHIFT 0x1 +#define VPEC_PG_CNTL__PG1_EN__SHIFT 0x8 +#define VPEC_PG_CNTL__PG1_HYSTERESIS__SHIFT 0x9 +#define VPEC_PG_CNTL__ZSTATES_ENABLE__SHIFT 0x10 +#define VPEC_PG_CNTL__ZSTATES_HYSTERESIS__SHIFT 0x11 +#define VPEC_PG_CNTL__FENCE_HYSTERESIS__SHIFT 0x18 +#define VPEC_PG_CNTL__CHECK_RSMU_UPON_POWER_UP__SHIFT 0x1c +#define VPEC_PG_CNTL__PG_EN_MASK 0x00000001L +#define VPEC_PG_CNTL__PG_HYSTERESIS_MASK 0x0000003EL +#define VPEC_PG_CNTL__PG1_EN_MASK 0x00000100L +#define VPEC_PG_CNTL__PG1_HYSTERESIS_MASK 0x00003E00L +#define VPEC_PG_CNTL__ZSTATES_ENABLE_MASK 0x00010000L +#define VPEC_PG_CNTL__ZSTATES_HYSTERESIS_MASK 0x003E0000L +#define VPEC_PG_CNTL__FENCE_HYSTERESIS_MASK 0x0F000000L +#define VPEC_PG_CNTL__CHECK_RSMU_UPON_POWER_UP_MASK 0x10000000L +//VPEC_PG_STATUS +#define VPEC_PG_STATUS__PG_STATUS__SHIFT 0x0 +#define VPEC_PG_STATUS__PG1_STATUS__SHIFT 0x2 +#define VPEC_PG_STATUS__PG_STATUS_MASK 0x00000003L +#define VPEC_PG_STATUS__PG1_STATUS_MASK 0x0000000CL +//VPEC_CLOCK_GATING_STATUS +#define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT 0x0 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS__SHIFT 0x2 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS__SHIFT 0x3 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE2_CLK_GATE_STATUS__SHIFT 0x4 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE3_CLK_GATE_STATUS__SHIFT 0x5 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS__SHIFT 0x6 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE1_CLK_GATE_STATUS__SHIFT 0x7 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE2_CLK_GATE_STATUS__SHIFT 0x8 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE3_CLK_GATE_STATUS__SHIFT 0x9 +#define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT 0xa +#define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT 0xb +#define VPEC_CLOCK_GATING_STATUS__USRAM_CLK_GATE_STATUS__SHIFT 0xc +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE4_CLK_GATE_STATUS__SHIFT 0xd +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE5_CLK_GATE_STATUS__SHIFT 0xe +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE6_CLK_GATE_STATUS__SHIFT 0xf +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE7_CLK_GATE_STATUS__SHIFT 0x10 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE4_CLK_GATE_STATUS__SHIFT 0x11 +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE5_CLK_GATE_STATUS__SHIFT 0x12 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE8_CLK_GATE_STATUS__SHIFT 0x13 +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE9_CLK_GATE_STATUS__SHIFT 0x14 +#define VPEC_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK 0x00000001L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE0_CLK_GATE_STATUS_MASK 0x00000004L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE1_CLK_GATE_STATUS_MASK 0x00000008L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE2_CLK_GATE_STATUS_MASK 0x00000010L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE3_CLK_GATE_STATUS_MASK 0x00000020L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE0_CLK_GATE_STATUS_MASK 0x00000040L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE1_CLK_GATE_STATUS_MASK 0x00000080L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE2_CLK_GATE_STATUS_MASK 0x00000100L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE3_CLK_GATE_STATUS_MASK 0x00000200L +#define VPEC_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK 0x00000400L +#define VPEC_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK 0x00000800L +#define VPEC_CLOCK_GATING_STATUS__USRAM_CLK_GATE_STATUS_MASK 0x00001000L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE4_CLK_GATE_STATUS_MASK 0x00002000L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE5_CLK_GATE_STATUS_MASK 0x00004000L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE6_CLK_GATE_STATUS_MASK 0x00008000L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE7_CLK_GATE_STATUS_MASK 0x00010000L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE4_CLK_GATE_STATUS_MASK 0x00020000L +#define VPEC_CLOCK_GATING_STATUS__IP_PIPE5_CLK_GATE_STATUS_MASK 0x00040000L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE8_CLK_GATE_STATUS_MASK 0x00080000L +#define VPEC_CLOCK_GATING_STATUS__OP_PIPE9_CLK_GATE_STATUS_MASK 0x00100000L +//VPEC_QUEUE0_RB_CNTL +#define VPEC_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE0_SCHEDULE_CNTL +#define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE0_RB_BASE +#define VPEC_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_BASE_HI +#define VPEC_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE0_RB_RPTR +#define VPEC_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_RPTR_HI +#define VPEC_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_WPTR +#define VPEC_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_WPTR_HI +#define VPEC_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_RPTR_ADDR_HI +#define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_RPTR_ADDR_LO +#define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE0_RB_AQL_CNTL +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE0_MINOR_PTR_UPDATE +#define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE0_CD_INFO +#define VPEC_QUEUE0_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE0_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_RB_PREEMPT +#define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE0_SKIP_CNTL +#define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE0_DOORBELL +#define VPEC_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE0_DOORBELL_OFFSET +#define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE0_DUMMY0 +#define VPEC_QUEUE0_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_DUMMY1 +#define VPEC_QUEUE0_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_DUMMY2 +#define VPEC_QUEUE0_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_DUMMY3 +#define VPEC_QUEUE0_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_DUMMY4 +#define VPEC_QUEUE0_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE0_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_IB_CNTL +#define VPEC_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE0_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE0_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE0_IB_RPTR +#define VPEC_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_IB_OFFSET +#define VPEC_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_IB_BASE_LO +#define VPEC_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE0_IB_BASE_HI +#define VPEC_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_IB_SIZE +#define VPEC_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE0_CMDIB_CNTL +#define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE0_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE0_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE0_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE0_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE0_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE0_CMDIB_RPTR +#define VPEC_QUEUE0_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_CMDIB_OFFSET +#define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_CMDIB_BASE_LO +#define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE0_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE0_CMDIB_BASE_HI +#define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_CMDIB_SIZE +#define VPEC_QUEUE0_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE0_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE0_3DLUTIB_CNTL +#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE0_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE0_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE0_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE0_3DLUTIB_RPTR +#define VPEC_QUEUE0_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_3DLUTIB_OFFSET +#define VPEC_QUEUE0_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE0_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE0_3DLUTIB_BASE_LO +#define VPEC_QUEUE0_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE0_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE0_3DLUTIB_BASE_HI +#define VPEC_QUEUE0_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_3DLUTIB_SIZE +#define VPEC_QUEUE0_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE0_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE0_CSA_ADDR_LO +#define VPEC_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_CSA_ADDR_HI +#define VPEC_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE0_CONTEXT_STATUS +#define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE0_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE0_DOORBELL_LOG +#define VPEC_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE0_IB_SUB_REMAIN +#define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE0_PREEMPT +#define VPEC_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE0_LOG0BUFFER_CFG +#define VPEC_QUEUE0_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE0_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE0_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE0_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE0_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE0_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE0_LOG1BUFFER_CFG +#define VPEC_QUEUE0_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE0_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE0_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE0_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE0_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE0_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE0_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE0_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE0_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE0_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE1_RB_CNTL +#define VPEC_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE1_SCHEDULE_CNTL +#define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE1_RB_BASE +#define VPEC_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_BASE_HI +#define VPEC_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE1_RB_RPTR +#define VPEC_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_RPTR_HI +#define VPEC_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_WPTR +#define VPEC_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_WPTR_HI +#define VPEC_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_RPTR_ADDR_HI +#define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_RPTR_ADDR_LO +#define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE1_RB_AQL_CNTL +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE1_MINOR_PTR_UPDATE +#define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE1_CD_INFO +#define VPEC_QUEUE1_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE1_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_RB_PREEMPT +#define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE1_SKIP_CNTL +#define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE1_DOORBELL +#define VPEC_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE1_DOORBELL_OFFSET +#define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE1_DUMMY0 +#define VPEC_QUEUE1_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_DUMMY1 +#define VPEC_QUEUE1_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_DUMMY2 +#define VPEC_QUEUE1_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_DUMMY3 +#define VPEC_QUEUE1_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_DUMMY4 +#define VPEC_QUEUE1_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE1_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_IB_CNTL +#define VPEC_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE1_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE1_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE1_IB_RPTR +#define VPEC_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_IB_OFFSET +#define VPEC_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_IB_BASE_LO +#define VPEC_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE1_IB_BASE_HI +#define VPEC_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_IB_SIZE +#define VPEC_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE1_CMDIB_CNTL +#define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE1_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE1_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE1_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE1_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE1_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE1_CMDIB_RPTR +#define VPEC_QUEUE1_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_CMDIB_OFFSET +#define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_CMDIB_BASE_LO +#define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE1_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE1_CMDIB_BASE_HI +#define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_CMDIB_SIZE +#define VPEC_QUEUE1_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE1_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE1_3DLUTIB_CNTL +#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE1_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE1_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE1_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE1_3DLUTIB_RPTR +#define VPEC_QUEUE1_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_3DLUTIB_OFFSET +#define VPEC_QUEUE1_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE1_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE1_3DLUTIB_BASE_LO +#define VPEC_QUEUE1_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE1_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE1_3DLUTIB_BASE_HI +#define VPEC_QUEUE1_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_3DLUTIB_SIZE +#define VPEC_QUEUE1_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE1_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE1_CSA_ADDR_LO +#define VPEC_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_CSA_ADDR_HI +#define VPEC_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE1_CONTEXT_STATUS +#define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE1_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE1_DOORBELL_LOG +#define VPEC_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE1_IB_SUB_REMAIN +#define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE1_PREEMPT +#define VPEC_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE1_LOG0BUFFER_CFG +#define VPEC_QUEUE1_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE1_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE1_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE1_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE1_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE1_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE1_LOG1BUFFER_CFG +#define VPEC_QUEUE1_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE1_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE1_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE1_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE1_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE1_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE1_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE1_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE1_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE1_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE2_RB_CNTL +#define VPEC_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE2_SCHEDULE_CNTL +#define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE2_RB_BASE +#define VPEC_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_BASE_HI +#define VPEC_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE2_RB_RPTR +#define VPEC_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_RPTR_HI +#define VPEC_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_WPTR +#define VPEC_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_WPTR_HI +#define VPEC_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_RPTR_ADDR_HI +#define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_RPTR_ADDR_LO +#define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE2_RB_AQL_CNTL +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE2_MINOR_PTR_UPDATE +#define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE2_CD_INFO +#define VPEC_QUEUE2_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE2_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_RB_PREEMPT +#define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE2_SKIP_CNTL +#define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE2_DOORBELL +#define VPEC_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE2_DOORBELL_OFFSET +#define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE2_DUMMY0 +#define VPEC_QUEUE2_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_DUMMY1 +#define VPEC_QUEUE2_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_DUMMY2 +#define VPEC_QUEUE2_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_DUMMY3 +#define VPEC_QUEUE2_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_DUMMY4 +#define VPEC_QUEUE2_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE2_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_IB_CNTL +#define VPEC_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE2_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE2_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE2_IB_RPTR +#define VPEC_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_IB_OFFSET +#define VPEC_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_IB_BASE_LO +#define VPEC_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE2_IB_BASE_HI +#define VPEC_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_IB_SIZE +#define VPEC_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE2_CMDIB_CNTL +#define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE2_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE2_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE2_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE2_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE2_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE2_CMDIB_RPTR +#define VPEC_QUEUE2_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_CMDIB_OFFSET +#define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_CMDIB_BASE_LO +#define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE2_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE2_CMDIB_BASE_HI +#define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_CMDIB_SIZE +#define VPEC_QUEUE2_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE2_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE2_3DLUTIB_CNTL +#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE2_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE2_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE2_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE2_3DLUTIB_RPTR +#define VPEC_QUEUE2_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_3DLUTIB_OFFSET +#define VPEC_QUEUE2_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE2_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE2_3DLUTIB_BASE_LO +#define VPEC_QUEUE2_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE2_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE2_3DLUTIB_BASE_HI +#define VPEC_QUEUE2_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_3DLUTIB_SIZE +#define VPEC_QUEUE2_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE2_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE2_CSA_ADDR_LO +#define VPEC_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_CSA_ADDR_HI +#define VPEC_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE2_CONTEXT_STATUS +#define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE2_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE2_DOORBELL_LOG +#define VPEC_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE2_IB_SUB_REMAIN +#define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE2_PREEMPT +#define VPEC_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE2_LOG0BUFFER_CFG +#define VPEC_QUEUE2_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE2_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE2_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE2_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE2_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE2_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE2_LOG1BUFFER_CFG +#define VPEC_QUEUE2_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE2_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE2_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE2_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE2_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE2_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE2_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE2_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE2_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE2_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE3_RB_CNTL +#define VPEC_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE3_SCHEDULE_CNTL +#define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE3_RB_BASE +#define VPEC_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_BASE_HI +#define VPEC_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE3_RB_RPTR +#define VPEC_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_RPTR_HI +#define VPEC_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_WPTR +#define VPEC_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_WPTR_HI +#define VPEC_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_RPTR_ADDR_HI +#define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_RPTR_ADDR_LO +#define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE3_RB_AQL_CNTL +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE3_MINOR_PTR_UPDATE +#define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE3_CD_INFO +#define VPEC_QUEUE3_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE3_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_RB_PREEMPT +#define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE3_SKIP_CNTL +#define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE3_DOORBELL +#define VPEC_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE3_DOORBELL_OFFSET +#define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE3_DUMMY0 +#define VPEC_QUEUE3_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_DUMMY1 +#define VPEC_QUEUE3_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_DUMMY2 +#define VPEC_QUEUE3_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_DUMMY3 +#define VPEC_QUEUE3_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_DUMMY4 +#define VPEC_QUEUE3_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE3_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_IB_CNTL +#define VPEC_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE3_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE3_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE3_IB_RPTR +#define VPEC_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_IB_OFFSET +#define VPEC_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_IB_BASE_LO +#define VPEC_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE3_IB_BASE_HI +#define VPEC_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_IB_SIZE +#define VPEC_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE3_CMDIB_CNTL +#define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE3_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE3_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE3_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE3_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE3_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE3_CMDIB_RPTR +#define VPEC_QUEUE3_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_CMDIB_OFFSET +#define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_CMDIB_BASE_LO +#define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE3_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE3_CMDIB_BASE_HI +#define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_CMDIB_SIZE +#define VPEC_QUEUE3_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE3_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE3_3DLUTIB_CNTL +#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE3_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE3_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE3_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE3_3DLUTIB_RPTR +#define VPEC_QUEUE3_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_3DLUTIB_OFFSET +#define VPEC_QUEUE3_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE3_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE3_3DLUTIB_BASE_LO +#define VPEC_QUEUE3_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE3_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE3_3DLUTIB_BASE_HI +#define VPEC_QUEUE3_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_3DLUTIB_SIZE +#define VPEC_QUEUE3_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE3_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE3_CSA_ADDR_LO +#define VPEC_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_CSA_ADDR_HI +#define VPEC_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE3_CONTEXT_STATUS +#define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE3_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE3_DOORBELL_LOG +#define VPEC_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE3_IB_SUB_REMAIN +#define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE3_PREEMPT +#define VPEC_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE3_LOG0BUFFER_CFG +#define VPEC_QUEUE3_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE3_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE3_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE3_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE3_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE3_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE3_LOG1BUFFER_CFG +#define VPEC_QUEUE3_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE3_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE3_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE3_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE3_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE3_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE3_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE3_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE3_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE3_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE4_RB_CNTL +#define VPEC_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE4_SCHEDULE_CNTL +#define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE4_RB_BASE +#define VPEC_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_BASE_HI +#define VPEC_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE4_RB_RPTR +#define VPEC_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_RPTR_HI +#define VPEC_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_WPTR +#define VPEC_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_WPTR_HI +#define VPEC_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_RPTR_ADDR_HI +#define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_RPTR_ADDR_LO +#define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE4_RB_AQL_CNTL +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE4_MINOR_PTR_UPDATE +#define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE4_CD_INFO +#define VPEC_QUEUE4_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE4_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_RB_PREEMPT +#define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE4_SKIP_CNTL +#define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE4_DOORBELL +#define VPEC_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE4_DOORBELL_OFFSET +#define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE4_DUMMY0 +#define VPEC_QUEUE4_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_DUMMY1 +#define VPEC_QUEUE4_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_DUMMY2 +#define VPEC_QUEUE4_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_DUMMY3 +#define VPEC_QUEUE4_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_DUMMY4 +#define VPEC_QUEUE4_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE4_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_IB_CNTL +#define VPEC_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE4_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE4_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE4_IB_RPTR +#define VPEC_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_IB_OFFSET +#define VPEC_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_IB_BASE_LO +#define VPEC_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE4_IB_BASE_HI +#define VPEC_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_IB_SIZE +#define VPEC_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE4_CMDIB_CNTL +#define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE4_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE4_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE4_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE4_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE4_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE4_CMDIB_RPTR +#define VPEC_QUEUE4_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_CMDIB_OFFSET +#define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_CMDIB_BASE_LO +#define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE4_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE4_CMDIB_BASE_HI +#define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_CMDIB_SIZE +#define VPEC_QUEUE4_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE4_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE4_3DLUTIB_CNTL +#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE4_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE4_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE4_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE4_3DLUTIB_RPTR +#define VPEC_QUEUE4_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_3DLUTIB_OFFSET +#define VPEC_QUEUE4_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE4_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE4_3DLUTIB_BASE_LO +#define VPEC_QUEUE4_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE4_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE4_3DLUTIB_BASE_HI +#define VPEC_QUEUE4_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_3DLUTIB_SIZE +#define VPEC_QUEUE4_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE4_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE4_CSA_ADDR_LO +#define VPEC_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_CSA_ADDR_HI +#define VPEC_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE4_CONTEXT_STATUS +#define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE4_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE4_DOORBELL_LOG +#define VPEC_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE4_IB_SUB_REMAIN +#define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE4_PREEMPT +#define VPEC_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE4_LOG0BUFFER_CFG +#define VPEC_QUEUE4_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE4_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE4_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE4_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE4_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE4_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE4_LOG1BUFFER_CFG +#define VPEC_QUEUE4_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE4_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE4_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE4_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE4_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE4_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE4_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE4_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE4_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE4_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE5_RB_CNTL +#define VPEC_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE5_SCHEDULE_CNTL +#define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE5_RB_BASE +#define VPEC_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_BASE_HI +#define VPEC_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE5_RB_RPTR +#define VPEC_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_RPTR_HI +#define VPEC_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_WPTR +#define VPEC_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_WPTR_HI +#define VPEC_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_RPTR_ADDR_HI +#define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_RPTR_ADDR_LO +#define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE5_RB_AQL_CNTL +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE5_MINOR_PTR_UPDATE +#define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE5_CD_INFO +#define VPEC_QUEUE5_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE5_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_RB_PREEMPT +#define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE5_SKIP_CNTL +#define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE5_DOORBELL +#define VPEC_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE5_DOORBELL_OFFSET +#define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE5_DUMMY0 +#define VPEC_QUEUE5_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_DUMMY1 +#define VPEC_QUEUE5_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_DUMMY2 +#define VPEC_QUEUE5_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_DUMMY3 +#define VPEC_QUEUE5_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_DUMMY4 +#define VPEC_QUEUE5_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE5_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_IB_CNTL +#define VPEC_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE5_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE5_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE5_IB_RPTR +#define VPEC_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_IB_OFFSET +#define VPEC_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_IB_BASE_LO +#define VPEC_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE5_IB_BASE_HI +#define VPEC_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_IB_SIZE +#define VPEC_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE5_CMDIB_CNTL +#define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE5_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE5_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE5_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE5_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE5_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE5_CMDIB_RPTR +#define VPEC_QUEUE5_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_CMDIB_OFFSET +#define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_CMDIB_BASE_LO +#define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE5_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE5_CMDIB_BASE_HI +#define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_CMDIB_SIZE +#define VPEC_QUEUE5_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE5_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE5_3DLUTIB_CNTL +#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE5_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE5_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE5_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE5_3DLUTIB_RPTR +#define VPEC_QUEUE5_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_3DLUTIB_OFFSET +#define VPEC_QUEUE5_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE5_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE5_3DLUTIB_BASE_LO +#define VPEC_QUEUE5_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE5_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE5_3DLUTIB_BASE_HI +#define VPEC_QUEUE5_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_3DLUTIB_SIZE +#define VPEC_QUEUE5_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE5_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE5_CSA_ADDR_LO +#define VPEC_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_CSA_ADDR_HI +#define VPEC_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE5_CONTEXT_STATUS +#define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE5_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE5_DOORBELL_LOG +#define VPEC_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE5_IB_SUB_REMAIN +#define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE5_PREEMPT +#define VPEC_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE5_LOG0BUFFER_CFG +#define VPEC_QUEUE5_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE5_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE5_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE5_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE5_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE5_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE5_LOG1BUFFER_CFG +#define VPEC_QUEUE5_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE5_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE5_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE5_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE5_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE5_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE5_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE5_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE5_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE5_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE6_RB_CNTL +#define VPEC_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE6_SCHEDULE_CNTL +#define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE6_RB_BASE +#define VPEC_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_BASE_HI +#define VPEC_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE6_RB_RPTR +#define VPEC_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_RPTR_HI +#define VPEC_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_WPTR +#define VPEC_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_WPTR_HI +#define VPEC_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_RPTR_ADDR_HI +#define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_RPTR_ADDR_LO +#define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE6_RB_AQL_CNTL +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE6_MINOR_PTR_UPDATE +#define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE6_CD_INFO +#define VPEC_QUEUE6_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE6_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_RB_PREEMPT +#define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE6_SKIP_CNTL +#define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE6_DOORBELL +#define VPEC_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE6_DOORBELL_OFFSET +#define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE6_DUMMY0 +#define VPEC_QUEUE6_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_DUMMY1 +#define VPEC_QUEUE6_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_DUMMY2 +#define VPEC_QUEUE6_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_DUMMY3 +#define VPEC_QUEUE6_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_DUMMY4 +#define VPEC_QUEUE6_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE6_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_IB_CNTL +#define VPEC_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE6_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE6_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE6_IB_RPTR +#define VPEC_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_IB_OFFSET +#define VPEC_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_IB_BASE_LO +#define VPEC_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE6_IB_BASE_HI +#define VPEC_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_IB_SIZE +#define VPEC_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE6_CMDIB_CNTL +#define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE6_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE6_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE6_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE6_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE6_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE6_CMDIB_RPTR +#define VPEC_QUEUE6_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_CMDIB_OFFSET +#define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_CMDIB_BASE_LO +#define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE6_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE6_CMDIB_BASE_HI +#define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_CMDIB_SIZE +#define VPEC_QUEUE6_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE6_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE6_3DLUTIB_CNTL +#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE6_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE6_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE6_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE6_3DLUTIB_RPTR +#define VPEC_QUEUE6_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_3DLUTIB_OFFSET +#define VPEC_QUEUE6_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE6_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE6_3DLUTIB_BASE_LO +#define VPEC_QUEUE6_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE6_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE6_3DLUTIB_BASE_HI +#define VPEC_QUEUE6_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_3DLUTIB_SIZE +#define VPEC_QUEUE6_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE6_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE6_CSA_ADDR_LO +#define VPEC_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_CSA_ADDR_HI +#define VPEC_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE6_CONTEXT_STATUS +#define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE6_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE6_DOORBELL_LOG +#define VPEC_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE6_IB_SUB_REMAIN +#define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE6_PREEMPT +#define VPEC_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE6_LOG0BUFFER_CFG +#define VPEC_QUEUE6_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE6_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE6_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE6_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE6_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE6_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE6_LOG1BUFFER_CFG +#define VPEC_QUEUE6_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE6_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE6_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE6_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE6_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE6_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE6_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE6_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE6_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE6_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE7_RB_CNTL +#define VPEC_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define VPEC_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define VPEC_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define VPEC_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define VPEC_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define VPEC_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define VPEC_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define VPEC_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define VPEC_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define VPEC_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//VPEC_QUEUE7_SCHEDULE_CNTL +#define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define VPEC_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define VPEC_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define VPEC_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define VPEC_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//VPEC_QUEUE7_RB_BASE +#define VPEC_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_BASE_HI +#define VPEC_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//VPEC_QUEUE7_RB_RPTR +#define VPEC_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_RPTR_HI +#define VPEC_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_WPTR +#define VPEC_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_WPTR_HI +#define VPEC_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define VPEC_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_RPTR_ADDR_HI +#define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_RPTR_ADDR_LO +#define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define VPEC_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//VPEC_QUEUE7_RB_AQL_CNTL +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define VPEC_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define VPEC_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define VPEC_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//VPEC_QUEUE7_MINOR_PTR_UPDATE +#define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//VPEC_QUEUE7_CD_INFO +#define VPEC_QUEUE7_CD_INFO__CD_INFO__SHIFT 0x0 +#define VPEC_QUEUE7_CD_INFO__CD_INFO_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_RB_PREEMPT +#define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 +#define VPEC_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L +//VPEC_QUEUE7_SKIP_CNTL +#define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 +#define VPEC_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL +//VPEC_QUEUE7_DOORBELL +#define VPEC_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c +#define VPEC_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e +#define VPEC_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L +#define VPEC_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L +//VPEC_QUEUE7_DOORBELL_OFFSET +#define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//VPEC_QUEUE7_DUMMY0 +#define VPEC_QUEUE7_DUMMY0__DUMMY__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY0__DUMMY_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_DUMMY1 +#define VPEC_QUEUE7_DUMMY1__VALUE__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY1__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_DUMMY2 +#define VPEC_QUEUE7_DUMMY2__VALUE__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY2__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_DUMMY3 +#define VPEC_QUEUE7_DUMMY3__VALUE__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY3__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_DUMMY4 +#define VPEC_QUEUE7_DUMMY4__VALUE__SHIFT 0x0 +#define VPEC_QUEUE7_DUMMY4__VALUE_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_IB_CNTL +#define VPEC_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE7_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE7_IB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE7_IB_RPTR +#define VPEC_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_IB_OFFSET +#define VPEC_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_IB_BASE_LO +#define VPEC_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE7_IB_BASE_HI +#define VPEC_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_IB_SIZE +#define VPEC_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE7_CMDIB_CNTL +#define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE7_CMDIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE7_CMDIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_CMDIB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define VPEC_QUEUE7_CMDIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE7_CMDIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE7_CMDIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE7_CMDIB_RPTR +#define VPEC_QUEUE7_CMDIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_CMDIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_CMDIB_OFFSET +#define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_CMDIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_CMDIB_BASE_LO +#define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE7_CMDIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE7_CMDIB_BASE_HI +#define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_CMDIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_CMDIB_SIZE +#define VPEC_QUEUE7_CMDIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE7_CMDIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE7_3DLUTIB_CNTL +#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_3DLUTIB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define VPEC_QUEUE7_3DLUTIB_CNTL__CMD_VMID__SHIFT 0x10 +#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_PRIV__SHIFT 0x1f +#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_3DLUTIB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define VPEC_QUEUE7_3DLUTIB_CNTL__CMD_VMID_MASK 0x000F0000L +#define VPEC_QUEUE7_3DLUTIB_CNTL__IB_PRIV_MASK 0x80000000L +//VPEC_QUEUE7_3DLUTIB_RPTR +#define VPEC_QUEUE7_3DLUTIB_RPTR__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_3DLUTIB_RPTR__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_3DLUTIB_OFFSET +#define VPEC_QUEUE7_3DLUTIB_OFFSET__OFFSET__SHIFT 0x2 +#define VPEC_QUEUE7_3DLUTIB_OFFSET__OFFSET_MASK 0x003FFFFCL +//VPEC_QUEUE7_3DLUTIB_BASE_LO +#define VPEC_QUEUE7_3DLUTIB_BASE_LO__ADDR__SHIFT 0x5 +#define VPEC_QUEUE7_3DLUTIB_BASE_LO__ADDR_MASK 0xFFFFFFE0L +//VPEC_QUEUE7_3DLUTIB_BASE_HI +#define VPEC_QUEUE7_3DLUTIB_BASE_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_3DLUTIB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_3DLUTIB_SIZE +#define VPEC_QUEUE7_3DLUTIB_SIZE__SIZE__SHIFT 0x0 +#define VPEC_QUEUE7_3DLUTIB_SIZE__SIZE_MASK 0x000FFFFFL +//VPEC_QUEUE7_CSA_ADDR_LO +#define VPEC_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_CSA_ADDR_HI +#define VPEC_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define VPEC_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//VPEC_QUEUE7_CONTEXT_STATUS +#define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define VPEC_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_3DLUTIB__SHIFT 0x8 +#define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define VPEC_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define VPEC_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define VPEC_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define VPEC_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define VPEC_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define VPEC_QUEUE7_CONTEXT_STATUS__USE_3DLUTIB_MASK 0x00000100L +#define VPEC_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define VPEC_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define VPEC_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//VPEC_QUEUE7_DOORBELL_LOG +#define VPEC_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define VPEC_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define VPEC_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define VPEC_QUEUE7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//VPEC_QUEUE7_IB_SUB_REMAIN +#define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define VPEC_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//VPEC_QUEUE7_PREEMPT +#define VPEC_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define VPEC_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//VPEC_QUEUE7_LOG0BUFFER_CFG +#define VPEC_QUEUE7_LOG0BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_LOG0BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE7_LOG0BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE7_LOG0BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE7_LOG0BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_LOG0BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE7_LOG0BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE7_LOG0BUFFER_CFG__RESERVED_MASK 0xFFF00000L +//VPEC_QUEUE7_LOG1BUFFER_CFG +#define VPEC_QUEUE7_LOG1BUFFER_CFG__ENABLE__SHIFT 0x0 +#define VPEC_QUEUE7_LOG1BUFFER_CFG__PARTIAL_ENTRY__SHIFT 0x1 +#define VPEC_QUEUE7_LOG1BUFFER_CFG__FIRST_FREE_ENTRY__SHIFT 0x4 +#define VPEC_QUEUE7_LOG1BUFFER_CFG__LAST_FREE_ENTRY__SHIFT 0xc +#define VPEC_QUEUE7_LOG1BUFFER_CFG__RESERVED__SHIFT 0x14 +#define VPEC_QUEUE7_LOG1BUFFER_CFG__ENABLE_MASK 0x00000001L +#define VPEC_QUEUE7_LOG1BUFFER_CFG__PARTIAL_ENTRY_MASK 0x00000002L +#define VPEC_QUEUE7_LOG1BUFFER_CFG__FIRST_FREE_ENTRY_MASK 0x00000FF0L +#define VPEC_QUEUE7_LOG1BUFFER_CFG__LAST_FREE_ENTRY_MASK 0x000FF000L +#define VPEC_QUEUE7_LOG1BUFFER_CFG__RESERVED_MASK 0xFFF00000L + +#endif From ab18f6d9f65ae105f3931e196d952083d947554f Mon Sep 17 00:00:00 2001 From: Caden Chien Date: Tue, 21 Apr 2026 18:02:34 +0800 Subject: [PATCH 69/71] drm/amdgpu/vpe: add vpe v2.0.0 support This patch adds support for vpe v2.0.0 with new structs and ip functions Acked-by: Roy Chan Signed-off-by: Caden Chien Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 25 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h | 1 + drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c | 350 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/vpe_v2_0.h | 29 ++ 6 files changed, 410 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c create mode 100644 drivers/gpu/drm/amd/amdgpu/vpe_v2_0.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 154a60e22c70..ee3574797bc2 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -234,7 +234,8 @@ amdgpu-y += \ # add VPE block amdgpu-y += \ amdgpu_vpe.o \ - vpe_v6_1.o + vpe_v6_1.o \ + vpe_v2_0.o # add UMSCH block amdgpu-y += \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index a6040ad15384..623f7a399d65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -2738,6 +2738,9 @@ static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(6, 1, 3): amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); break; + case IP_VERSION(2, 0, 0): + amdgpu_device_ip_block_add(adev, &vpe_v2_0_ip_block); + break; default: break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index fd881388d612..0a34a27d1106 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -29,6 +29,7 @@ #include "amdgpu_smu.h" #include "soc15_common.h" #include "vpe_v6_1.h" +#include "vpe_v2_0.h" #define AMDGPU_CSA_VPE_SIZE 64 /* VPE CSA resides in the 4th page of CSA */ @@ -310,6 +311,9 @@ static int vpe_early_init(struct amdgpu_ip_block *ip_block) vpe_v6_1_set_funcs(vpe); vpe->collaborate_mode = true; break; + case IP_VERSION(2, 0, 0): + vpe_v2_0_set_funcs(vpe); + break; default: return -EINVAL; } @@ -1009,6 +1013,19 @@ const struct amd_ip_funcs vpe_ip_funcs = { .set_powergating_state = vpe_set_powergating_state, }; +const struct amd_ip_funcs vpe2_ip_funcs = { + .name = "vpe_v2_0", + .early_init = vpe_early_init, + .sw_init = vpe_sw_init, + .sw_fini = vpe_sw_fini, + .hw_init = vpe_hw_init, + .hw_fini = vpe_hw_fini, + .suspend = vpe_suspend, + .resume = vpe_resume, + .set_clockgating_state = vpe_set_clockgating_state, + .set_powergating_state = vpe_set_powergating_state, +}; + const struct amdgpu_ip_block_version vpe_v6_1_ip_block = { .type = AMD_IP_BLOCK_TYPE_VPE, .major = 6, @@ -1016,3 +1033,11 @@ const struct amdgpu_ip_block_version vpe_v6_1_ip_block = { .rev = 0, .funcs = &vpe_ip_funcs, }; + +const struct amdgpu_ip_block_version vpe_v2_0_ip_block = { + .type = AMD_IP_BLOCK_TYPE_VPE, + .major = 2, + .minor = 0, + .rev = 0, + .funcs = &vpe2_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h index 695da740a97e..5c9a9f59a02b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h @@ -107,5 +107,6 @@ int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev); ((vpe)->funcs->load_microcode ? (vpe)->funcs->load_microcode((vpe)) : 0) extern const struct amdgpu_ip_block_version vpe_v6_1_ip_block; +extern const struct amdgpu_ip_block_version vpe_v2_0_ip_block; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c new file mode 100644 index 000000000000..0d91e01fbf3a --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.c @@ -0,0 +1,350 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "amdgpu.h" +#include "amdgpu_ucode.h" +#include "amdgpu_vpe.h" +#include "vpe_v2_0.h" +#include "soc15_common.h" +#include "ivsrcid/vpe/irqsrcs_vpe_6_1.h" +#include "vpe/vpe_2_0_0_offset.h" +#include "vpe/vpe_2_0_0_sh_mask.h" + +MODULE_FIRMWARE("amdgpu/vpe_2_0_0.bin"); + +#define VPE_THREAD1_UCODE_OFFSET 0x8000 + +static uint32_t vpe_v2_0_get_reg_offset(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset) +{ + uint32_t base; + + base = vpe->ring.adev->reg_offset[VPE_HWIP][inst][0]; + + return base + offset; +} + +static int vpe_v2_0_irq_init(struct amdgpu_vpe *vpe) +{ + struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe); + int ret; + + ret = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VPE, + VPE_6_1_SRCID__VPE_TRAP, + &adev->vpe.trap_irq); + if (ret) + return ret; + + return 0; +} + +static int vpe_v2_0_load_microcode(struct amdgpu_vpe *vpe) +{ + struct amdgpu_device *adev = vpe->ring.adev; + const struct vpe_firmware_header_v1_0 *vpe_hdr; + const __le32 *data; + uint32_t ucode_offset[2], ucode_size[2], size_dw, ret; + uint32_t f32_offset, f32_cntl, reg_data; + + ret = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL)); + ret = REG_SET_FIELD(ret, VPEC_CNTL, UMSCH_INT_ENABLE, 0); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), ret); + + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL2)); + reg_data = REG_SET_FIELD(reg_data, VPEC_CNTL2, IB_FIFO_WATERMARK, 1); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL2), reg_data); + + if (amdgpu_vpe_configure_dpm(vpe)) + dev_warn(adev->dev, "VPE DPM not enabled.\n"); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + + f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL); + f32_cntl = RREG32(f32_offset); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0); + + adev->vpe.cmdbuf_cpu_addr[0] = f32_offset; + adev->vpe.cmdbuf_cpu_addr[1] = f32_cntl; + + return amdgpu_vpe_psp_update_sram(adev); + } + + /* Halt and Check F32 cleaness */ + f32_offset = vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL); + f32_cntl = RREG32(f32_offset); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 1); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 1); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_CHECKSUM_CLR, 1); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH0_CHECKSUM_CLR, 1); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl); + + f32_cntl = RREG32(f32_offset); + if (!REG_GET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT)) { + dev_err(adev->dev, "VPEC is not halted"); + return -EBUSY; + } + + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_CHECKSUM_CLR, 0); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH0_CHECKSUM_CLR, 0); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl); + + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE_CHECKSUM)); + if (reg_data) { + dev_err(adev->dev, "VPE FW checksum 0 not clean"); + return -EBUSY; + } + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_UCODE1_CHECKSUM)); + if (reg_data) { + dev_err(adev->dev, "VPE FW checksum 1 not clean"); + return -EBUSY; + } + + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_STATUS2)); + if (REG_GET_FIELD(reg_data, VPEC_STATUS2, TH0F32_INSTR_PTR)) { + dev_err(adev->dev, "VPE FW initial status not clean"); + return -EBUSY; + } + + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_STATUS6)); + if (REG_GET_FIELD(reg_data, VPEC_STATUS6, TH1F32_INSTR_PTR)) { + dev_err(adev->dev, "VPE FW initial status not clean"); + return -EBUSY; + } + /* end of F32 cleaness check */ + + vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data; + + /* Thread 0(command thread) ucode offset/size */ + ucode_offset[0] = le32_to_cpu(vpe_hdr->header.ucode_array_offset_bytes); + ucode_size[0] = le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes); + /* Thread 1(control thread) ucode offset/size */ + ucode_offset[1] = le32_to_cpu(vpe_hdr->ctl_ucode_offset); + ucode_size[1] = le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes); + + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL)); + reg_data = REG_SET_FIELD(reg_data, VPEC_PG_CNTL, PG_EN, 0); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL), reg_data); + + for (int j = 0; j < vpe->num_instances; j++) { + for (int i = 0; i < 2; i++) { + if (i > 0) + WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), VPE_THREAD1_UCODE_OFFSET); + else + WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_ADDR), 0); + + data = (const __le32 *)(adev->vpe.fw->data + ucode_offset[i]); + size_dw = ucode_size[i] / sizeof(__le32); + + while (size_dw--) { + if (amdgpu_emu_mode && size_dw % 500 == 0) + msleep(1); + WREG32(vpe_get_reg_offset(vpe, j, regVPEC_UCODE_DATA), le32_to_cpup(data++)); + } + } + } + + reg_data = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL)); + reg_data = REG_SET_FIELD(reg_data, VPEC_PG_CNTL, PG_EN, 1); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_PG_CNTL), reg_data); + + /* Unhalt F32 */ + f32_cntl = RREG32(f32_offset); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, HALT, 0); + f32_cntl = REG_SET_FIELD(f32_cntl, VPEC_F32_CNTL, TH1_RESET, 0); + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_F32_CNTL), f32_cntl); + + return 0; +} + +static int vpe_v2_0_ring_start(struct amdgpu_vpe *vpe) +{ + struct amdgpu_ring *ring = &vpe->ring; + struct amdgpu_device *adev = ring->adev; + uint32_t doorbell, doorbell_offset; + uint32_t rb_bufsz, rb_cntl; + uint32_t ib_cntl, i; + int ret; + + for (i = 0; i < vpe->num_instances; i++) { + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); + rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_PRIV, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_VMID, 0); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl); + + /* Initialize the ring buffer's read and write pointers */ + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR), 0); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_HI), 0); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), 0); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), 0); + + /* set the wb address whether it's enabled or not */ + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_LO), + lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_RPTR_ADDR_HI), + upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); + + rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE), ring->gpu_addr >> 8); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); + + ring->wptr = 0; + + /* before programing wptr to a less value, need set minor_ptr_update first */ + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 1); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); + /* set minor_ptr_update to 0 after wptr programed */ + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_MINOR_PTR_UPDATE), 0); + + doorbell_offset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET)); + doorbell_offset = REG_SET_FIELD(doorbell_offset, VPEC_QUEUE0_DOORBELL_OFFSET, OFFSET, ring->doorbell_index + i*4); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL_OFFSET), doorbell_offset); + + doorbell = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL)); + doorbell = REG_SET_FIELD(doorbell, VPEC_QUEUE0_DOORBELL, ENABLE, ring->use_doorbell ? 1 : 0); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_DOORBELL), doorbell); + + adev->nbio.funcs->vpe_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index + i*4, 4); + + rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_ENABLE, 1); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl); + + ib_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, VPEC_QUEUE0_IB_CNTL, IB_ENABLE, 1); + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_IB_CNTL), ib_cntl); + } + + ret = amdgpu_ring_test_helper(ring); + if (ret) + return ret; + + return 0; +} + +static int vpe_v2_0_ring_stop(struct amdgpu_vpe *vpe) +{ + struct amdgpu_device *adev = vpe->ring.adev; + uint32_t queue_reset, i; + int ret; + + for (i = 0; i < vpe->num_instances; i++) { + queue_reset = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ)); + + queue_reset = REG_SET_FIELD(queue_reset, VPEC_QUEUE_RESET_REQ, QUEUE0_RESET, 1); + + WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE_RESET_REQ), queue_reset); + /* timeout length is adev->timeout_usec */ + ret = SOC15_WAIT_ON_RREG(VPE, i, regVPEC_QUEUE_RESET_REQ, 0, + VPEC_QUEUE_RESET_REQ__QUEUE0_RESET_MASK); + + if (ret) + dev_err(adev->dev, "VPE queue reset failed\n"); + } + + vpe->ring.sched.ready = false; + + return ret; +} + +static int vpe_v2_0_set_trap_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + struct amdgpu_vpe *vpe = &adev->vpe; + uint32_t vpe_cntl; + + vpe_cntl = RREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL)); + vpe_cntl = REG_SET_FIELD(vpe_cntl, VPEC_CNTL, TRAP_ENABLE, + state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); + + WREG32(vpe_get_reg_offset(vpe, 0, regVPEC_CNTL), vpe_cntl); + + return 0; +} + +static int vpe_v2_0_process_trap_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + + DRM_DEBUG("IH: VPE trap\n"); + + switch (entry->client_id) { + case SOC21_IH_CLIENTID_VPE: + amdgpu_fence_process(&adev->vpe.ring); + break; + default: + break; + } + + return 0; +} + +static int vpe_v2_0_set_regs(struct amdgpu_vpe *vpe) +{ + vpe->regs.queue0_rb_rptr_lo = regVPEC_QUEUE0_RB_RPTR; + vpe->regs.queue0_rb_rptr_hi = regVPEC_QUEUE0_RB_RPTR_HI; + vpe->regs.queue0_rb_wptr_lo = regVPEC_QUEUE0_RB_WPTR; + vpe->regs.queue0_rb_wptr_hi = regVPEC_QUEUE0_RB_WPTR_HI; + vpe->regs.queue0_preempt = regVPEC_QUEUE0_PREEMPT; + vpe->regs.dpm_enable = regVPEC_PUB_DUMMY2; + + vpe->regs.dpm_pratio = regVPEC_QUEUE6_DUMMY4; + vpe->regs.dpm_request_interval = regVPEC_QUEUE5_DUMMY3; + vpe->regs.dpm_decision_threshold = regVPEC_QUEUE5_DUMMY4; + vpe->regs.dpm_busy_clamp_threshold = regVPEC_QUEUE7_DUMMY2; + vpe->regs.dpm_idle_clamp_threshold = regVPEC_QUEUE7_DUMMY3; + vpe->regs.dpm_request_lv = regVPEC_QUEUE7_DUMMY1; + vpe->regs.context_indicator = regVPEC_QUEUE6_DUMMY3; + + return 0; +} + +static struct vpe_funcs vpe_v2_0_funcs = { + .get_reg_offset = vpe_v2_0_get_reg_offset, + .set_regs = vpe_v2_0_set_regs, + .irq_init = vpe_v2_0_irq_init, + .init_microcode = amdgpu_vpe_init_microcode, + .load_microcode = vpe_v2_0_load_microcode, + .ring_init = amdgpu_vpe_ring_init, + .ring_start = vpe_v2_0_ring_start, + .ring_stop = vpe_v2_0_ring_stop, + .ring_fini = amdgpu_vpe_ring_fini, +}; + +static const struct amdgpu_irq_src_funcs vpe_v2_0_trap_irq_funcs = { + .set = vpe_v2_0_set_trap_irq_state, + .process = vpe_v2_0_process_trap_irq, +}; + +void vpe_v2_0_set_funcs(struct amdgpu_vpe *vpe) +{ + vpe->funcs = &vpe_v2_0_funcs; + vpe->trap_irq.funcs = &vpe_v2_0_trap_irq_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.h new file mode 100644 index 000000000000..e9f2077bfdc2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vpe_v2_0.h @@ -0,0 +1,29 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __VPE_V2_0_H__ +#define __VPE_V2_0_H__ + +#include "amdgpu_vpe.h" + +void vpe_v2_0_set_funcs(struct amdgpu_vpe *vpe); + +#endif From b03d53598b0d2048e8fa7303b8d0784768ec4fa6 Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Fri, 3 Apr 2026 15:58:31 +0800 Subject: [PATCH 70/71] drm/amdgpu/gfx_v12_0: set gfx.rs64_enable from PFP header on GFX12 gfx_v12_0_init_microcode() always loads RS64 CP ucode but never set adev->gfx.rs64_enable, so it stayed false and code that branches on it (e.g. MEC pipe reset) used the legacy CP_MEC_CNTL path incorrectly. Match GFX11: derive RS64 mode from the PFP firmware header (v2.0) via amdgpu_ucode_hdr_version(). Log at debug when RS64 is enabled. Reviewed-by: Alex Deucher Signed-off-by: Jesse Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index b866a944f878..f47928dcd848 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -602,6 +602,13 @@ static int gfx_v12_0_init_microcode(struct amdgpu_device *adev) "amdgpu/%s_pfp.bin", ucode_prefix); if (err) goto out; + + adev->gfx.rs64_enable = amdgpu_ucode_hdr_version( + (union amdgpu_firmware_header *) + adev->gfx.pfp_fw->data, 2, 0); + if (adev->gfx.rs64_enable) + dev_dbg(adev->dev, "CP RS64 enable\n"); + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP); amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK); From d00df389371346d6ac5739d8692405d9d8b11041 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Fri, 8 May 2026 10:31:22 +0800 Subject: [PATCH 71/71] drm/amd/pm: update dpm clock pm attributes for aldebaran (gc 9.4.2) v1: Separate DPM clock attribute constraints for Arcturus (9.4.1) and Aldebaran (9.4.2) ASICs. - For Aldebaran: * mclk/socclk: Disable write, only voltage control supported * fclk/pcie: Mark as unsupported - Remove 9.4.2 from global pcie check and handle it in ASIC specific case - Update comments to reflect correct hardware names v2: fix some coding logic issue (by asad) Signed-off-by: Yang Wang Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 024bfdb7c157..bb11f8bb7bd4 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -2034,15 +2034,13 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2)) *states = ATTR_STATE_UNSUPPORTED; } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) { - if (gc_ver == IP_VERSION(9, 4, 2) || - amdgpu_is_multi_aid(adev)) + if (amdgpu_is_multi_aid(adev)) *states = ATTR_STATE_UNSUPPORTED; } switch (gc_ver) { case IP_VERSION(9, 4, 1): - case IP_VERSION(9, 4, 2): - /* the Mi series card does not support standalone mclk/socclk/fclk level setting */ + /* Arcturus does not support standalone mclk/socclk/fclk level setting */ if (DEVICE_ATTR_IS(pp_dpm_mclk) || DEVICE_ATTR_IS(pp_dpm_socclk) || DEVICE_ATTR_IS(pp_dpm_fclk)) { @@ -2050,6 +2048,19 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd dev_attr->store = NULL; } break; + case IP_VERSION(9, 4, 2): + if (DEVICE_ATTR_IS(pp_dpm_mclk) || + DEVICE_ATTR_IS(pp_dpm_socclk)) { + /* Aldebaran mclk/socclk DPM only supports voltage control, + * not allow to set dpm level directly */ + dev_attr->attr.mode &= ~S_IWUGO; + dev_attr->store = NULL; + } else if (DEVICE_ATTR_IS(pp_dpm_fclk) || + DEVICE_ATTR_IS(pp_dpm_pcie)) { + /* Aldebaran does not support fclk/pcie dpm */ + *states = ATTR_STATE_UNSUPPORTED; + } + break; default: break; }