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dt-bindings: PCI: qcom: Document Hawi and Maili PCIe Controllers
Add a dedicated schema for the PCIe controllers found on the Hawi and Maili platforms. Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com> [mani: added MAINTAINERS entry and squashed the Maili patch] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260625-hawi-pcie-v4-1-1a578603cd86@oss.qualcomm.com
This commit is contained in:
Matthew Leung
Manivannan Sadhasivam
parent
dc59e4fea9
commit
55aeda95ee
201
Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
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201
Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Hawi PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <mani@kernel.org>
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description:
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Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based on
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the Synopsys DesignWare PCIe IP.
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properties:
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compatible:
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oneOf:
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- const: qcom,hawi-pcie
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- items:
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- enum:
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- qcom,maili-pcie
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- const: qcom,hawi-pcie
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reg:
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items:
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- description: Qualcomm specific registers
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- description: DesignWare PCIe registers
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- description: External local bus interface registers
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- description: ATU address space
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- description: PCIe configuration space
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- description: MHI registers
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reg-names:
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items:
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- const: parf
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- const: dbi
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- const: elbi
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- const: atu
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- const: config
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- const: mhi
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clocks:
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items:
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- description: PCIe Auxiliary clock
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- description: PCIe Configuration clock
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- description: PCIe Master AXI clock
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- description: PCIe Slave AXI clock
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- description: PCIe Slave Q2A AXI clock
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- description: PCIe Aggre NoC AXI clock
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- description: PCIe Config NoC AXI clock
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clock-names:
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items:
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- const: aux
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- const: cfg
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- const: bus_master
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- const: bus_slave
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- const: slave_q2a
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- const: noc_aggr
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- const: cnoc_sf_axi
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interrupts:
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minItems: 9
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maxItems: 9
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interrupt-names:
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items:
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- const: msi0
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- const: msi1
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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- const: global
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resets:
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items:
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- description: PCIe core reset
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- description: PCIe link down reset
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reset-names:
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items:
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- const: pci
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- const: link_down
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required:
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- power-domains
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- resets
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- reset-names
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allOf:
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- $ref: qcom,pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@1c00000 {
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compatible = "qcom,hawi-pcie";
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reg = <0 0x01c00000 0 0x3000>,
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<0 0x40000000 0 0xf1d>,
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<0 0x40000f20 0 0xa8>,
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<0 0x40001000 0 0x1000>,
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<0 0x40100000 0 0x100000>,
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<0 0x01c03000 0 0x1000>;
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reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
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ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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linux,pci-domain = <0>;
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num-lanes = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&gcc_pcie_0_aux_clk>,
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<&gcc_pcie_0_cfg_ahb_clk>,
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<&gcc_pcie_0_mstr_axi_clk>,
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<&gcc_pcie_0_slv_axi_clk>,
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<&gcc_pcie_0_slv_q2a_axi_clk>,
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<&gcc_aggre_noc_pcie_axi_clk>,
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<&gcc_cnoc_pcie_sf_axi_clk>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a",
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"noc_aggr",
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"cnoc_sf_axi";
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dma-coherent;
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interrupts = <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7", "global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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interconnects = <&pcie_anoc_master_pcie_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY
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&cnoc_main_slave_pcie_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
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interconnect-names = "pcie-mem", "cpu-pcie";
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iommu-map = <0x0 &apps_smmu 0x1000 0x1>,
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<0x100 &apps_smmu 0x1001 0x1>;
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pinctrl-0 = <&pcie0_default_state>;
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pinctrl-names = "default";
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power-domains = <&gcc_pcie_0_phy_gdsc>;
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resets = <&gcc_pcie_0_bcr>,
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<&gcc_pcie_0_link_down_bcr>;
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reset-names = "pci", "link_down";
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msi-map = <0x0 &gic_its 0x1000 0x1>,
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<0x100 &gic_its 0x1001 0x1>;
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msi-map-mask = <0xff00>;
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pcie@0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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phys = <&pcie0_phy>;
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wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
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};
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};
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};
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@ -21011,6 +21011,7 @@ M: Manivannan Sadhasivam <mani@kernel.org>
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L: linux-pci@vger.kernel.org
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L: linux-arm-msm@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/qcom,*.yaml
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F: drivers/pci/controller/dwc/pcie-qcom-common.c
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F: drivers/pci/controller/dwc/pcie-qcom.c
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