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drm/xe: Fix build_pt_update_batch_sram for non-4K PAGE_SIZE
The build_pt_update_batch_sram function in the Xe migrate layer assumes PAGE_SIZE == XE_PAGE_SIZE (4K), which is not a valid assumption on non-x86 platforms. This patch updates build_pt_update_batch_sram to correctly handle PAGE_SIZE > 4K by programming multiple 4K GPU pages per CPU page. v5: - Mask off non-address bits during compare Signed-off-by: Matthew Brost <matthew.brost@intel.com> Tested-by: Simon Richter <Simon.Richter@hogyros.de> Reviewed-by: Stuart Summers <stuart.summers@intel.com> Link: https://lore.kernel.org/r/20251013034555.4121168-2-matthew.brost@intel.com
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@ -1781,13 +1781,15 @@ static void build_pt_update_batch_sram(struct xe_migrate *m,
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u32 size)
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{
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u16 pat_index = tile_to_xe(m->tile)->pat.idx[XE_CACHE_WB];
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u64 gpu_page_size = 0x1ull << xe_pt_shift(0);
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u32 ptes;
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int i = 0;
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ptes = DIV_ROUND_UP(size, XE_PAGE_SIZE);
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ptes = DIV_ROUND_UP(size, gpu_page_size);
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while (ptes) {
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u32 chunk = min(MAX_PTE_PER_SDI, ptes);
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chunk = ALIGN_DOWN(chunk, PAGE_SIZE / XE_PAGE_SIZE);
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bb->cs[bb->len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk);
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bb->cs[bb->len++] = pt_offset;
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bb->cs[bb->len++] = 0;
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@ -1796,18 +1798,30 @@ static void build_pt_update_batch_sram(struct xe_migrate *m,
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ptes -= chunk;
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while (chunk--) {
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u64 addr = sram_addr[i].addr & PAGE_MASK;
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u64 addr = sram_addr[i].addr & ~(gpu_page_size - 1);
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u64 pte, orig_addr = addr;
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xe_tile_assert(m->tile, sram_addr[i].proto ==
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DRM_INTERCONNECT_SYSTEM);
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xe_tile_assert(m->tile, addr);
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addr = m->q->vm->pt_ops->pte_encode_addr(m->tile->xe,
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addr, pat_index,
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0, false, 0);
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bb->cs[bb->len++] = lower_32_bits(addr);
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bb->cs[bb->len++] = upper_32_bits(addr);
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i++;
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again:
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pte = m->q->vm->pt_ops->pte_encode_addr(m->tile->xe,
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addr, pat_index,
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0, false, 0);
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bb->cs[bb->len++] = lower_32_bits(pte);
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bb->cs[bb->len++] = upper_32_bits(pte);
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if (gpu_page_size < PAGE_SIZE) {
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addr += XE_PAGE_SIZE;
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if (orig_addr + PAGE_SIZE != addr) {
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chunk--;
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goto again;
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}
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i++;
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} else {
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i += gpu_page_size / PAGE_SIZE;
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}
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}
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}
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}
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