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Couple of display fixes (NV12 for bigjoiner and Watermark clear

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on plane disable) along with couple of GT selftests fixes.
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Merge tag 'drm-intel-fixes-2026-07-17' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes

Couple of display fixes (NV12 for bigjoiner and Watermark clear
on plane disable) along with couple of GT selftests fixes.

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/alp3ks0K1ZsxUC05@intel.com
This commit is contained in:
Dave Airlie 2026-07-18 07:17:46 +10:00
commit 5554e0599c
4 changed files with 19 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
drivers/gpu/drm/i915/display/skl_universal_plane.c
View File

@ -2126,19 +2126,6 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
return 0;
}
/* Divide a U16.16 fixed-point value by 2, staying in fixed-point domain */
static inline u32 fp_16_16_div2(u32 fp)
{
return fp >> 1;
}
/* Convert a U16.16 fixed-point value to integer, rounding up */
static inline int fp_16_16_to_int_ceil(u32 fp)
{
return DIV_ROUND_UP(fp, 1 << 16);
}
static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
{
struct intel_display *display = to_intel_display(plane_state);
@ -2154,14 +2141,20 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
/*
* LNL+ UV surface start/size =
* ceiling(half of Y plane start/size). Use ceiling division
* unconditionally; it is a no-op for even values.
* UV (chroma) start/size = ceiling(half of the *integer* Y plane
* start/size), i.e. the value the luma surface programs (src >> 16),
* not the raw U16.16. A bigjoiner seam mapped through the scaler can
* give a fractional luma src; ceiling that directly would round the
* chroma one column too far and read past the chroma surface.
*/
int x = fp_16_16_to_int_ceil(fp_16_16_div2(plane_state->uapi.src.x1));
int y = fp_16_16_to_int_ceil(fp_16_16_div2(plane_state->uapi.src.y1));
int w = fp_16_16_to_int_ceil(fp_16_16_div2(drm_rect_width(&plane_state->uapi.src)));
int h = fp_16_16_to_int_ceil(fp_16_16_div2(drm_rect_height(&plane_state->uapi.src)));
int luma_x = plane_state->uapi.src.x1 >> 16;
int luma_y = plane_state->uapi.src.y1 >> 16;
int luma_w = drm_rect_width(&plane_state->uapi.src) >> 16;
int luma_h = drm_rect_height(&plane_state->uapi.src) >> 16;
int x = DIV_ROUND_UP(luma_x, 2);
int y = DIV_ROUND_UP(luma_y, 2);
int w = DIV_ROUND_UP(luma_x + luma_w, 2) - x;
int h = DIV_ROUND_UP(luma_y + luma_h, 2) - y;
u32 offset;
/* FIXME not quite sure how/if these apply to the chroma plane */

2
drivers/gpu/drm/i915/display/skl_watermark.c
View File

@ -3856,7 +3856,7 @@ void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc,
return;
skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0);
skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0);
skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb_y[plane->id], 0, 0);
crtc_state->wm.skl.plane_min_ddb[plane->id] = 0;
crtc_state->wm.skl.plane_interim_ddb[plane->id] = 0;

2
drivers/gpu/drm/i915/gt/intel_engine_user.c
View File

@ -259,7 +259,7 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
p = &prev->rb_right;
}
if (IS_ENABLED(CONFIG_DRM_I915_SELFTESTS) &&
if (IS_ENABLED(CONFIG_DRM_I915_SELFTEST) &&
IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
struct intel_engine_cs *engine;
unsigned int isolation;

8
drivers/gpu/drm/i915/gt/selftest_gt_pm.c
View File

@ -16,9 +16,9 @@ static int cmp_u64(const void *A, const void *B)
{
const u64 *a = A, *b = B;
if (a < b)
if (*a < *b)
return -1;
else if (a > b)
else if (*a > *b)
return 1;
else
return 0;
@ -28,9 +28,9 @@ static int cmp_u32(const void *A, const void *B)
{
const u32 *a = A, *b = B;
if (a < b)
if (*a < *b)
return -1;
else if (a > b)
else if (*a > *b)
return 1;
else
return 0;