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ARM: use BIT() and GENMASK() for fault status register fields

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Modernise the fault status field definitions by using BIT() and
GENMASK().

Reviewed-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Russell King (Oracle) 2025-12-05 15:34:42 +00:00
parent 9c46fcaf2e
commit 5548e8a466
1 changed files with 6 additions and 6 deletions
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12
arch/arm/mm/fault.h
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@ -5,12 +5,12 @@
/*
* Fault status register encodings. We steal bit 31 for our own purposes.
*/
#define FSR_LNX_PF (1 << 31)
#define FSR_CM (1 << 13)
#define FSR_WRITE (1 << 11)
#define FSR_FS4 (1 << 10)
#define FSR_FS3_0 (15)
#define FSR_FS5_0 (0x3f)
#define FSR_LNX_PF BIT(31)
#define FSR_CM BIT(13)
#define FSR_WRITE BIT(11)
#define FSR_FS4 BIT(10)
#define FSR_FS3_0 GENMASK(3, 0)
#define FSR_FS5_0 GENMASK(5, 0)
#ifdef CONFIG_ARM_LPAE
#define FSR_FS_AEA 17