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drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeued

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[Why]
As MES KIQ is dequeued, tell RLC that KIQ is inactive

[How]
Clear the RLC_CP_SCHEDULERS Active bit which RLC checks KIQ status
In addition, driver can halt MES under SRIOV when unloading driver

v2:
Use scheduler0 mask to clear KIQ portion of RLC_CP_SCHEDULERS

Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
Reviewed-by: Horace Chen <horace.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yifan Zha 2023-03-29 17:18:47 +08:00 committed by Alex Deucher
parent a2a0bdf198
commit 554836cc24
1 changed files with 12 additions and 2 deletions
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14
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
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@ -1138,6 +1138,16 @@ static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
}
static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)
{
uint32_t tmp;
/* tell RLC which is KIQ dequeue */
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK;
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
}
static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
{
int r = 0;
@ -1182,10 +1192,10 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
if (amdgpu_sriov_vf(adev)) {
mes_v11_0_kiq_dequeue(&adev->gfx.kiq.ring);
mes_v11_0_kiq_clear(adev);
}
if (!amdgpu_sriov_vf(adev))
mes_v11_0_enable(adev, false);
mes_v11_0_enable(adev, false);
return 0;
}