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Bluetooth: btintel_pcie: add MDBGC multi-buffer DBGC allocation
Newer Intel BT PCIe variants (Nova Lake SCP2 and PTL FMP2) require three independent DRAM debug (DBGC) buffer pools instead of the single pool used by existing controllers. Factor the per-pool buffer allocation into a common helper and add a multi-DBGC (MDBGC) setup path that allocates three pools using the fragment context format. MDBGC is used when the device reports an MDBGC-capable variant; otherwise the existing single-pool DBGC path is retained. Assisted-by: Copilot:claude-opus-4.7 sparse Signed-off-by: Chandrashekar Devegowda <chandrashekar.devegowda@intel.com> Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
This commit is contained in:
Chandrashekar Devegowda
Luiz Augusto von Dentz
parent
937363063a
commit
5530f514d9
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@ -134,6 +134,20 @@ struct btintel_pcie_dbgc_ctxt {
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struct btintel_pcie_dbgc_ctxt_buf bufs[BTINTEL_PCIE_DBGC_BUFFER_COUNT];
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};
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struct btintel_pcie_mdbgc_ctxt {
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u32 magic_num;
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u32 ver;
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u32 buf1_index;
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u32 buf1_count;
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struct btintel_pcie_dbgc_ctxt_buf buf1[BTINTEL_PCIE_DBGC_BUFFER_COUNT];
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u32 buf2_index;
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u32 buf2_count;
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struct btintel_pcie_dbgc_ctxt_buf buf2[BTINTEL_PCIE_DBGC_BUFFER_COUNT];
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u32 buf3_index;
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u32 buf3_count;
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struct btintel_pcie_dbgc_ctxt_buf buf3[BTINTEL_PCIE_DBGC_BUFFER_COUNT];
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};
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struct btintel_pcie_trigger_evt {
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u8 type;
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u8 len;
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@ -184,57 +198,159 @@ static inline bool btintel_pcie_dbg_to_wifi(struct btintel_pcie_data *data)
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return data->dbg_path_cache != BTINTEL_PCIE_DRAM;
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}
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/* This function initializes the memory for DBGC buffers and formats the
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* DBGC fragment which consists header info and DBGC buffer's LSB, MSB and
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* size as the payload
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*/
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/* Helper function to allocate and setup a debug buffer group */
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static int btintel_pcie_alloc_dbgc_buf(struct btintel_pcie_data *data,
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struct data_buf **buf,
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dma_addr_t *p_addr,
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void **v_addr,
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struct btintel_pcie_dbgc_ctxt_buf *frag,
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u32 buf_index,
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u32 buf_count)
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{
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struct data_buf *b;
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int i;
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*buf = devm_kcalloc(&data->pdev->dev, buf_count,
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sizeof(**buf), GFP_KERNEL);
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if (!*buf) {
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BT_ERR("Failed to allocate dbgc buf: %u",
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buf_index + 1);
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return -ENOMEM;
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}
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*v_addr = dmam_alloc_coherent(&data->pdev->dev,
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buf_count *
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BTINTEL_PCIE_DBGC_BUFFER_SIZE,
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p_addr,
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GFP_KERNEL | __GFP_NOWARN);
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if (!*v_addr) {
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BT_ERR("Failed to allocate dbgc buf: %u DMA",
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buf_index + 1);
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return -ENOMEM;
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}
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for (i = 0; i < buf_count; i++) {
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b = &(*buf)[i];
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b->data_p_addr = *p_addr +
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i * BTINTEL_PCIE_DBGC_BUFFER_SIZE;
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b->data = *v_addr +
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i * BTINTEL_PCIE_DBGC_BUFFER_SIZE;
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frag[i].buf_addr_lsb =
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lower_32_bits(b->data_p_addr);
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frag[i].buf_addr_msb =
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upper_32_bits(b->data_p_addr);
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frag[i].buf_size = BTINTEL_PCIE_DBGC_BUFFER_SIZE;
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}
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return 0;
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}
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/* This function initializes the memory for MDBGC buffers */
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static int btintel_pcie_setup_mdbgc(struct btintel_pcie_data *data)
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{
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struct btintel_pcie_mdbgc_ctxt db_frag;
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u32 frag_size = sizeof(db_frag);
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void *frag_v_addr;
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int err;
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data->mdbgc.count = BTINTEL_PCIE_DBGC_BUFFER_COUNT;
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frag_v_addr = dmam_alloc_coherent(&data->pdev->dev, frag_size,
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&data->mdbgc.frag_p_addr,
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GFP_KERNEL | __GFP_NOWARN);
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if (!frag_v_addr)
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return -ENOMEM;
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data->mdbgc.frag_v_addr = frag_v_addr;
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data->mdbgc.frag_size = frag_size;
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memset(&db_frag, 0, sizeof(db_frag));
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db_frag.magic_num = BTINTEL_PCIE_MAGIC_NUM;
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db_frag.ver = BTINTEL_PCIE_MDBGC_FRAG_VERSION;
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/* Allocate DBGC buffer 1 */
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db_frag.buf1_index = BTINTEL_PCIE_MDBGC_ALLOCATIONID_1;
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db_frag.buf1_count = data->mdbgc.count;
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err = btintel_pcie_alloc_dbgc_buf(data,
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&data->mdbgc.buf1,
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&data->mdbgc.buf1_p_addr,
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&data->mdbgc.buf1_v_addr,
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db_frag.buf1, 0,
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data->mdbgc.count);
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if (err)
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return err;
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/* Allocate DBGC buffer 2 */
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db_frag.buf2_index = BTINTEL_PCIE_MDBGC_ALLOCATIONID_2;
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db_frag.buf2_count = data->mdbgc.count;
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err = btintel_pcie_alloc_dbgc_buf(data,
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&data->mdbgc.buf2,
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&data->mdbgc.buf2_p_addr,
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&data->mdbgc.buf2_v_addr,
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db_frag.buf2, 1,
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data->mdbgc.count);
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if (err)
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return err;
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/* Allocate DBGC buffer 3 */
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db_frag.buf3_index = BTINTEL_PCIE_MDBGC_ALLOCATIONID_3;
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db_frag.buf3_count = data->mdbgc.count;
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err = btintel_pcie_alloc_dbgc_buf(data,
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&data->mdbgc.buf3,
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&data->mdbgc.buf3_p_addr,
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&data->mdbgc.buf3_v_addr,
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db_frag.buf3, 2,
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data->mdbgc.count);
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if (err)
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return err;
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memcpy(data->mdbgc.frag_v_addr, &db_frag, sizeof(db_frag));
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return 0;
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}
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/* This function initializes the memory for DBGC buffers */
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static int btintel_pcie_setup_dbgc(struct btintel_pcie_data *data)
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{
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struct btintel_pcie_dbgc_ctxt db_frag;
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struct data_buf *buf;
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int i;
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int err;
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data->dbgc.count = BTINTEL_PCIE_DBGC_BUFFER_COUNT;
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data->dbgc.bufs = devm_kcalloc(&data->pdev->dev, data->dbgc.count,
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sizeof(*buf), GFP_KERNEL);
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if (!data->dbgc.bufs)
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return -ENOMEM;
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data->dbgc.buf_v_addr = dmam_alloc_coherent(&data->pdev->dev,
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data->dbgc.count *
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BTINTEL_PCIE_DBGC_BUFFER_SIZE,
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&data->dbgc.buf_p_addr,
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GFP_KERNEL | __GFP_NOWARN);
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if (!data->dbgc.buf_v_addr)
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return -ENOMEM;
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data->dbgc.frag_v_addr = dmam_alloc_coherent(&data->pdev->dev,
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sizeof(struct btintel_pcie_dbgc_ctxt),
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&data->dbgc.frag_p_addr,
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GFP_KERNEL | __GFP_NOWARN);
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sizeof(struct btintel_pcie_dbgc_ctxt),
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&data->dbgc.frag_p_addr,
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GFP_KERNEL | __GFP_NOWARN);
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if (!data->dbgc.frag_v_addr)
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return -ENOMEM;
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data->dbgc.frag_size = sizeof(struct btintel_pcie_dbgc_ctxt);
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memset(&db_frag, 0, sizeof(db_frag));
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db_frag.magic_num = BTINTEL_PCIE_MAGIC_NUM;
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db_frag.ver = BTINTEL_PCIE_DBGC_FRAG_VERSION;
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db_frag.total_size = BTINTEL_PCIE_DBGC_FRAG_PAYLOAD_SIZE;
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db_frag.num_buf = BTINTEL_PCIE_DBGC_FRAG_BUFFER_COUNT;
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for (i = 0; i < data->dbgc.count; i++) {
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buf = &data->dbgc.bufs[i];
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buf->data_p_addr = data->dbgc.buf_p_addr + i * BTINTEL_PCIE_DBGC_BUFFER_SIZE;
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buf->data = data->dbgc.buf_v_addr + i * BTINTEL_PCIE_DBGC_BUFFER_SIZE;
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db_frag.bufs[i].buf_addr_lsb = lower_32_bits(buf->data_p_addr);
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db_frag.bufs[i].buf_addr_msb = upper_32_bits(buf->data_p_addr);
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db_frag.bufs[i].buf_size = BTINTEL_PCIE_DBGC_BUFFER_SIZE;
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}
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err = btintel_pcie_alloc_dbgc_buf(data,
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&data->dbgc.bufs,
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&data->dbgc.buf_p_addr,
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&data->dbgc.buf_v_addr,
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db_frag.bufs, 0,
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data->dbgc.count);
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if (err)
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return err;
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memcpy(data->dbgc.frag_v_addr, &db_frag, sizeof(db_frag));
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return 0;
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}
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static bool btintel_pcie_is_mdbgc_supported(struct btintel_pcie_data *data)
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{
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return data->pdev->device == BTINTEL_PCIE_DEVICE_ID_NVL_S_SCP2 ||
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data->pdev->device == BTINTEL_PCIE_DEVICE_ID_NVL_Hx_SCP2 ||
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data->pdev->device == BTINTEL_PCIE_DEVICE_ID_PTL_FMP2;
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}
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static inline void ipc_print_ia_ring(struct hci_dev *hdev, struct ia *ia,
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u16 queue_num)
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{
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@ -1877,6 +1993,12 @@ static void btintel_pcie_coredump_worker(struct work_struct *work)
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goto out;
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}
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if (btintel_pcie_is_mdbgc_supported(data)) {
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bt_dev_info(data->hdev,
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"Skipping coredump: MDBGC dump format not supported yet");
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goto out;
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}
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btintel_pcie_dump_traces(data->hdev);
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out:
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/* Release guard last so a new trigger can run only after this
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@ -2282,10 +2404,14 @@ static void btintel_pcie_init_ci(struct btintel_pcie_data *data,
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*/
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ci->dbgc_addr = 0;
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ci->dbgc_size = 0;
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} else if (btintel_pcie_is_mdbgc_supported(data)) {
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ci->dbgc_addr = data->mdbgc.frag_p_addr;
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ci->dbgc_size = data->mdbgc.frag_size;
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} else {
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ci->dbgc_addr = data->dbgc.frag_p_addr;
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ci->dbgc_size = data->dbgc.frag_size;
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}
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ci->dbg_preset = 0x00;
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}
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@ -2518,6 +2644,8 @@ static int btintel_pcie_alloc(struct btintel_pcie_data *data)
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* buffer allocation entirely.
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*/
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err = 0;
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} else if (btintel_pcie_is_mdbgc_supported(data)) {
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err = btintel_pcie_setup_mdbgc(data);
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} else {
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err = btintel_pcie_setup_dbgc(data);
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}
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@ -106,8 +106,19 @@
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* Bits[2:3] DBGI O/P : 01 = WiFi DBGC
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*/
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#define BTINTEL_PCIE_DRAM 0x01
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#define BTINTEL_PCIE_FW_MON_MODE_DRAM 0x02
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#define BTINTEL_PCIE_WIFI_DBGC 0x06
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#define BTINTEL_PCIE_MDBGC_FRAG_VERSION 2
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#define BTINTEL_PCIE_MDBGC_ALLOCATIONID_1 0
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#define BTINTEL_PCIE_MDBGC_ALLOCATIONID_2 1
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#define BTINTEL_PCIE_MDBGC_ALLOCATIONID_3 2
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#define BTINTEL_PCIE_DEVICE_ID_NVL_S_SCP2 0x6E74
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#define BTINTEL_PCIE_DEVICE_ID_NVL_Hx_SCP2 0xD346
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#define BTINTEL_PCIE_DEVICE_ID_PTL_FMP2 0xE476
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/* Causes for the FH register interrupts */
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enum msix_fh_int_causes {
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BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0 = BIT(0), /* cause 0 */
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@ -459,6 +470,24 @@ struct btintel_pcie_dbgc {
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struct data_buf *bufs;
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};
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struct btintel_pcie_mdbgc {
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u32 count;
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void *frag_v_addr;
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dma_addr_t frag_p_addr;
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u32 frag_size;
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dma_addr_t buf1_p_addr;
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void *buf1_v_addr;
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dma_addr_t buf2_p_addr;
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void *buf2_v_addr;
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dma_addr_t buf3_p_addr;
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void *buf3_v_addr;
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struct data_buf *buf1;
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struct data_buf *buf2;
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struct data_buf *buf3;
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};
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struct btintel_pcie_dump_mem_info {
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u32 exception_dump_addr;
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u32 exception_dump_len;
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@ -599,6 +628,7 @@ struct btintel_pcie_data {
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u32 alive_intr_ctxt;
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enum btintel_pcie_reset_type reset_type;
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struct btintel_pcie_dbgc dbgc;
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struct btintel_pcie_mdbgc mdbgc;
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struct btintel_pcie_dump_header dmp_hdr;
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u8 pm_sx_event;
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u32 debug_evt_addr;
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