mirror of
https://github.com/torvalds/linux.git
synced 2026-06-02 19:43:40 +02:00
arm64: dts: qcom: sm8550: use ICC tag for all interconnect phandles
Use the proper QCOM_ICC_TAG_ define instead of passing 0 in all interconnect paths phandle third argument. Use QCOM_ICC_TAG_ALWAYS which is the fallback mask if 0 is used as third phandle argument. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250115-topic-sm8x50-upstream-dt-icc-update-v1-1-eaa8b10e2af7@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Neil Armstrong
Bjorn Andersson
parent
984748d30c
commit
54df5e5277
|
|
@ -331,7 +331,8 @@ firmware {
|
|||
scm: scm {
|
||||
compatible = "qcom,scm-sm8550", "qcom,scm";
|
||||
qcom,dload-mode = <&tcsr 0x19000>;
|
||||
interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -850,9 +851,12 @@ i2c8: i2c@880000 {
|
|||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
|
||||
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
|
||||
|
|
@ -868,9 +872,12 @@ spi8: spi@880000 {
|
|||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
|
||||
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
|
||||
|
|
@ -890,9 +897,12 @@ i2c9: i2c@884000 {
|
|||
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
|
||||
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
|
||||
|
|
@ -908,9 +918,12 @@ spi9: spi@884000 {
|
|||
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
|
||||
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
|
||||
|
|
@ -930,9 +943,12 @@ i2c10: i2c@888000 {
|
|||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
|
||||
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
|
||||
|
|
@ -948,9 +964,12 @@ spi10: spi@888000 {
|
|||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
|
||||
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
|
||||
|
|
@ -970,9 +989,12 @@ i2c11: i2c@88c000 {
|
|||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
|
||||
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
|
||||
|
|
@ -988,9 +1010,12 @@ spi11: spi@88c000 {
|
|||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
|
||||
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
|
||||
|
|
@ -1010,9 +1035,12 @@ i2c12: i2c@890000 {
|
|||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
|
||||
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
|
||||
|
|
@ -1028,9 +1056,12 @@ spi12: spi@890000 {
|
|||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
|
||||
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
|
||||
|
|
@ -1050,9 +1081,12 @@ i2c13: i2c@894000 {
|
|||
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
|
||||
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
|
||||
|
|
@ -1068,9 +1102,12 @@ spi13: spi@894000 {
|
|||
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
|
||||
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
|
||||
|
|
@ -1088,8 +1125,10 @@ uart14: serial@898000 {
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
|
||||
interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1104,9 +1143,12 @@ i2c15: i2c@89c000 {
|
|||
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
|
||||
<&gpi_dma2 1 7 QCOM_GPI_I2C>;
|
||||
|
|
@ -1122,9 +1164,12 @@ spi15: spi@89c000 {
|
|||
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
|
||||
<&gpi_dma2 1 7 QCOM_GPI_SPI>;
|
||||
|
|
@ -1156,8 +1201,10 @@ i2c_hub_0: i2c@980000 {
|
|||
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1173,8 +1220,10 @@ i2c_hub_1: i2c@984000 {
|
|||
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1190,8 +1239,10 @@ i2c_hub_2: i2c@988000 {
|
|||
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1207,8 +1258,10 @@ i2c_hub_3: i2c@98c000 {
|
|||
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1224,8 +1277,10 @@ i2c_hub_4: i2c@990000 {
|
|||
interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1241,8 +1296,10 @@ i2c_hub_5: i2c@994000 {
|
|||
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1258,8 +1315,10 @@ i2c_hub_6: i2c@998000 {
|
|||
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1275,8 +1334,10 @@ i2c_hub_7: i2c@99c000 {
|
|||
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1292,8 +1353,10 @@ i2c_hub_8: i2c@9a0000 {
|
|||
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1309,8 +1372,10 @@ i2c_hub_9: i2c@9a4000 {
|
|||
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1347,7 +1412,8 @@ qupv3_id_0: geniqup@ac0000 {
|
|||
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0xa3 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core";
|
||||
dma-coherent;
|
||||
#address-cells = <2>;
|
||||
|
|
@ -1364,9 +1430,12 @@ i2c0: i2c@a80000 {
|
|||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
|
||||
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
|
||||
|
|
@ -1382,9 +1451,12 @@ spi0: spi@a80000 {
|
|||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
|
||||
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
|
||||
|
|
@ -1404,9 +1476,12 @@ i2c1: i2c@a84000 {
|
|||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
|
||||
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
|
||||
|
|
@ -1422,9 +1497,12 @@ spi1: spi@a84000 {
|
|||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
|
||||
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
|
||||
|
|
@ -1444,9 +1522,12 @@ i2c2: i2c@a88000 {
|
|||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
|
||||
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
|
||||
|
|
@ -1462,9 +1543,12 @@ spi2: spi@a88000 {
|
|||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
|
||||
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
|
||||
|
|
@ -1484,9 +1568,12 @@ i2c3: i2c@a8c000 {
|
|||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
|
||||
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
|
||||
|
|
@ -1502,9 +1589,12 @@ spi3: spi@a8c000 {
|
|||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
|
||||
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
|
||||
|
|
@ -1524,9 +1614,12 @@ i2c4: i2c@a90000 {
|
|||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
|
||||
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
|
||||
|
|
@ -1542,9 +1635,12 @@ spi4: spi@a90000 {
|
|||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
|
||||
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
|
||||
|
|
@ -1562,9 +1658,12 @@ i2c5: i2c@a94000 {
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c5_data_clk>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
|
||||
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
|
||||
|
|
@ -1582,9 +1681,12 @@ spi5: spi@a94000 {
|
|||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
|
||||
<&gpi_dma1 1 5 QCOM_GPI_SPI>;
|
||||
|
|
@ -1602,9 +1704,12 @@ i2c6: i2c@a98000 {
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_i2c6_data_clk>;
|
||||
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
|
||||
<&gpi_dma1 1 6 QCOM_GPI_I2C>;
|
||||
|
|
@ -1622,9 +1727,12 @@ spi6: spi@a98000 {
|
|||
interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
|
||||
<&gpi_dma1 1 6 QCOM_GPI_SPI>;
|
||||
|
|
@ -1643,8 +1751,10 @@ uart7: serial@a9c000 {
|
|||
pinctrl-0 = <&qup_uart7_default>;
|
||||
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -1768,8 +1878,10 @@ pcie0: pcie@1c00000 {
|
|||
"ddrss_sf_tbu",
|
||||
"noc_aggr";
|
||||
|
||||
interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
|
||||
interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
msi-map = <0x0 &gic_its 0x1400 0x1>,
|
||||
|
|
@ -1891,8 +2003,10 @@ pcie1: pcie@1c08000 {
|
|||
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
|
||||
interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "pcie-mem", "cpu-pcie";
|
||||
|
||||
msi-map = <0x0 &gic_its 0x1480 0x1>,
|
||||
|
|
@ -1969,7 +2083,8 @@ crypto: crypto@1dfa000 {
|
|||
dma-names = "rx", "tx";
|
||||
iommus = <&apps_smmu 0x480 0x0>,
|
||||
<&apps_smmu 0x481 0x0>;
|
||||
interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "memory";
|
||||
};
|
||||
|
||||
|
|
@ -2013,8 +2128,10 @@ ufs_mem_hc: ufshc@1d84000 {
|
|||
dma-coherent;
|
||||
|
||||
operating-points-v2 = <&ufs_opp_table>;
|
||||
interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
|
||||
interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
|
||||
|
||||
interconnect-names = "ufs-ddr", "cpu-ufs";
|
||||
clock-names = "core_clk",
|
||||
|
|
@ -2314,8 +2431,10 @@ ipa: ipa@3f40000 {
|
|||
clocks = <&rpmhcc RPMH_IPA_CLK>;
|
||||
clock-names = "core";
|
||||
|
||||
interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
|
||||
interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_IPA_CFG QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "memory",
|
||||
"config";
|
||||
|
||||
|
|
@ -2349,7 +2468,8 @@ remoteproc_mpss: remoteproc@4080000 {
|
|||
<&rpmhpd RPMHPD_MSS>;
|
||||
power-domain-names = "cx", "mss";
|
||||
|
||||
interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
|
||||
memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
|
||||
|
||||
|
|
@ -2390,7 +2510,8 @@ remoteproc_adsp: remoteproc@6800000 {
|
|||
<&rpmhpd RPMHPD_LMX>;
|
||||
power-domain-names = "lcx", "lmx";
|
||||
|
||||
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
|
||||
memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
|
||||
|
||||
|
|
@ -2848,8 +2969,10 @@ sdhc_2: mmc@8804000 {
|
|||
power-domains = <&rpmhpd RPMHPD_CX>;
|
||||
operating-points-v2 = <&sdhc2_opp_table>;
|
||||
|
||||
interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
|
||||
interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "sdhc-ddr", "cpu-sdhc";
|
||||
bus-width = <4>;
|
||||
dma-coherent;
|
||||
|
|
@ -3020,7 +3143,8 @@ mdss: display-subsystem@ae00000 {
|
|||
|
||||
power-domains = <&dispcc MDSS_GDSC>;
|
||||
|
||||
interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "mdp0-mem";
|
||||
|
||||
iommus = <&apps_smmu 0x1c00 0x2>;
|
||||
|
|
@ -3493,8 +3617,10 @@ usb_1: usb@a6f8800 {
|
|||
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
|
||||
interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
|
||||
interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
status = "disabled";
|
||||
|
|
@ -4617,7 +4743,8 @@ pmu@24091000 {
|
|||
compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
|
||||
reg = <0 0x24091000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
|
||||
interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
|
||||
|
||||
operating-points-v2 = <&llcc_bwmon_opp_table>;
|
||||
|
||||
|
|
@ -4666,7 +4793,8 @@ pmu@240b6400 {
|
|||
compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
|
||||
reg = <0 0x240b6400 0 0x600>;
|
||||
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
|
||||
|
||||
operating-points-v2 = <&cpu_bwmon_opp_table>;
|
||||
|
||||
|
|
@ -4750,7 +4878,8 @@ remoteproc_cdsp: remoteproc@32300000 {
|
|||
<&rpmhpd RPMHPD_NSP>;
|
||||
power-domain-names = "cx", "mxc", "nsp";
|
||||
|
||||
interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
|
||||
memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user