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i2c: rcar: improve accuracy for R-Car Gen3+
With some new registers, SCL can be calculated to be closer to the desired rate. Apply the new formula for R-Car Gen3 device types. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Wolfram Sang
Wolfram Sang
parent
0e864b552b
commit
54c76ed330
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@ -41,6 +41,10 @@
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#define ICSAR 0x1C /* slave address */
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#define ICMAR 0x20 /* master address */
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#define ICRXTX 0x24 /* data port */
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#define ICCCR2 0x28 /* Clock control 2 */
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#define ICMPR 0x2C /* SCL mask control */
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#define ICHPR 0x30 /* SCL HIGH control */
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#define ICLPR 0x34 /* SCL LOW control */
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#define ICFBSCR 0x38 /* first bit setup cycle (Gen3) */
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#define ICDMAER 0x3c /* DMA enable (Gen3) */
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@ -84,11 +88,25 @@
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#define RMDMAE BIT(1) /* DMA Master Received Enable */
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#define TMDMAE BIT(0) /* DMA Master Transmitted Enable */
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/* ICCCR2 */
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#define CDFD BIT(2) /* CDF Disable */
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#define HLSE BIT(1) /* HIGH/LOW Separate Control Enable */
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#define SME BIT(0) /* SCL Mask Enable */
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/* ICFBSCR */
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#define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
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#define RCAR_MIN_DMA_LEN 8
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/* SCL low/high ratio 5:4 to meet all I2C timing specs (incl safety margin) */
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#define RCAR_SCLD_RATIO 5
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#define RCAR_SCHD_RATIO 4
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/*
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* SMD should be smaller than SCLD/SCHD and is always around 20 in the docs.
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* Thus, we simply use 20 which works for low and high speeds.
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*/
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#define RCAR_DEFAULT_SMD 20
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#define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
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#define RCAR_BUS_PHASE_DATA (MDBS | MIE)
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#define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
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@ -128,6 +146,8 @@ struct rcar_i2c_priv {
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int pos;
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u32 icccr;
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u16 schd;
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u16 scld;
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u8 recovery_icmcr; /* protected by adapter lock */
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enum rcar_i2c_type devtype;
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struct i2c_client *slave;
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@ -216,11 +236,16 @@ static void rcar_i2c_init(struct rcar_i2c_priv *priv)
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rcar_i2c_write(priv, ICMCR, MDBS);
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rcar_i2c_write(priv, ICMSR, 0);
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/* start clock */
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rcar_i2c_write(priv, ICCCR, priv->icccr);
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if (priv->devtype == I2C_RCAR_GEN3)
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if (priv->devtype < I2C_RCAR_GEN3) {
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rcar_i2c_write(priv, ICCCR, priv->icccr);
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} else {
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rcar_i2c_write(priv, ICCCR2, CDFD | HLSE | SME);
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rcar_i2c_write(priv, ICCCR, priv->icccr);
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rcar_i2c_write(priv, ICMPR, RCAR_DEFAULT_SMD);
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rcar_i2c_write(priv, ICHPR, priv->schd);
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rcar_i2c_write(priv, ICLPR, priv->scld);
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rcar_i2c_write(priv, ICFBSCR, TCYC17);
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}
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}
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static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
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@ -241,7 +266,7 @@ static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
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static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
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{
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u32 scgd, cdf, round, ick, sum, scl, cdf_width;
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u32 cdf, round, ick, sum, scl, cdf_width;
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unsigned long rate;
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struct device *dev = rcar_i2c_priv_to_dev(priv);
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struct i2c_timings t = {
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@ -254,27 +279,17 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
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/* Fall back to previously used values if not supplied */
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i2c_parse_fw_timings(dev, &t, false);
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switch (priv->devtype) {
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case I2C_RCAR_GEN1:
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cdf_width = 2;
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break;
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case I2C_RCAR_GEN2:
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case I2C_RCAR_GEN3:
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cdf_width = 3;
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break;
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default:
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dev_err(dev, "device type error\n");
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return -EIO;
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}
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/*
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* calculate SCL clock
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* see
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* ICCCR
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* ICCCR (and ICCCR2 for Gen3+)
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*
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* ick = clkp / (1 + CDF)
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* SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
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*
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* for Gen3+:
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* SCL = clkp / (8 + SMD * 2 + SCLD + SCHD +F[(ticf + tr + intd) * clkp])
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*
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* ick : I2C internal clock < 20 MHz
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* ticf : I2C SCL falling time
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* tr : I2C SCL rising time
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@ -284,11 +299,12 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
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*/
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rate = clk_get_rate(priv->clk);
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cdf = rate / 20000000;
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if (cdf >= 1U << cdf_width) {
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dev_err(dev, "Input clock %lu too high\n", rate);
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return -EIO;
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}
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ick = rate / (cdf + 1);
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cdf_width = (priv->devtype == I2C_RCAR_GEN1) ? 2 : 3;
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if (cdf >= 1U << cdf_width)
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goto err_no_val;
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/* On Gen3+, we use cdf only for the filters, not as a SCL divider */
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ick = rate / (priv->devtype < I2C_RCAR_GEN3 ? (cdf + 1) : 1);
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/*
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* It is impossible to calculate a large scale number on u32. Separate it.
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@ -301,24 +317,58 @@ static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
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round = DIV_ROUND_CLOSEST(ick, 1000000);
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round = DIV_ROUND_CLOSEST(round * sum, 1000);
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/*
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* SCL = ick / (20 + 8 * SCGD + F[(ticf + tr + intd) * ick])
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* 20 + 8 * SCGD + F[...] = ick / SCL
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* SCGD = ((ick / SCL) - 20 - F[...]) / 8
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* Result (= SCL) should be less than bus_speed for hardware safety
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*/
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scgd = DIV_ROUND_UP(ick, t.bus_freq_hz ?: 1);
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scgd = DIV_ROUND_UP(scgd - 20 - round, 8);
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scl = ick / (20 + 8 * scgd + round);
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if (priv->devtype < I2C_RCAR_GEN3) {
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u32 scgd;
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/*
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* SCL = ick / (20 + 8 * SCGD + F[(ticf + tr + intd) * ick])
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* 20 + 8 * SCGD + F[...] = ick / SCL
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* SCGD = ((ick / SCL) - 20 - F[...]) / 8
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* Result (= SCL) should be less than bus_speed for hardware safety
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*/
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scgd = DIV_ROUND_UP(ick, t.bus_freq_hz ?: 1);
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scgd = DIV_ROUND_UP(scgd - 20 - round, 8);
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scl = ick / (20 + 8 * scgd + round);
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if (scgd > 0x3f)
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goto err_no_val;
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if (scgd > 0x3f)
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goto err_no_val;
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dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u, SCGD: %u\n",
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scl, t.bus_freq_hz, rate, round, cdf, scgd);
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dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u, SCGD: %u\n",
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scl, t.bus_freq_hz, rate, round, cdf, scgd);
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/* keep icccr value */
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priv->icccr = scgd << cdf_width | cdf;
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priv->icccr = scgd << cdf_width | cdf;
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} else {
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u32 x, sum_ratio = RCAR_SCHD_RATIO + RCAR_SCLD_RATIO;
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/*
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* SCLD/SCHD ratio and SMD default value are explained above
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* where they are defined. With these definitions, we can compute
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* x as a base value for the SCLD/SCHD ratio:
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*
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* SCL = clkp / (8 + 2 * SMD + SCLD + SCHD + F[(ticf + tr + intd) * clkp])
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* SCL = clkp / (8 + 2 * RCAR_DEFAULT_SMD + RCAR_SCLD_RATIO * x
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* + RCAR_SCHD_RATIO * x + F[...])
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*
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* with: sum_ratio = RCAR_SCLD_RATIO + RCAR_SCHD_RATIO
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* and: smd = RCAR_DEFAULT_SMD
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*
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* SCL = clkp / (8 + 2 * smd + sum_ratio * x + F[...])
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* 8 + 2 * smd + sum_ratio * x + F[...] = clkp / SCL
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* x = ((clkp / SCL) - 8 - 2 * smd - F[...]) / sum_ratio
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*/
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x = DIV_ROUND_UP(rate, t.bus_freq_hz ?: 1);
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x = DIV_ROUND_UP(x - 8 - 2 * RCAR_DEFAULT_SMD - round, sum_ratio);
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scl = rate / (8 + 2 * RCAR_DEFAULT_SMD + sum_ratio * x + round);
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/* Bail out if values don't fit into 16 bit or SMD became too large */
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if (x * RCAR_SCLD_RATIO > 0xffff || RCAR_DEFAULT_SMD > x * RCAR_SCHD_RATIO)
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goto err_no_val;
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priv->icccr = cdf;
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priv->schd = RCAR_SCHD_RATIO * x;
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priv->scld = RCAR_SCLD_RATIO * x;
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dev_dbg(dev, "clk %u/%u(%lu), round %u, CDF: %u SCHD %u SCLD %u\n",
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scl, t.bus_freq_hz, rate, round, cdf, priv->schd, priv->scld);
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}
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return 0;
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