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x86/bugs: Move the X86_FEATURE_USE_IBPB check into callers

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indirect_branch_prediction_barrier() only performs the MSR write if
X86_FEATURE_USE_IBPB is set, using alternative_msr_write(). In
preparation for removing X86_FEATURE_USE_IBPB, move the feature check
into the callers so that they can be addressed one-by-one, and use
X86_FEATURE_IBPB instead to guard the MSR write.

Signed-off-by: Yosry Ahmed <yosry.ahmed@linux.dev>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Josh Poimboeuf <jpoimboe@kernel.org>
Acked-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20250227012712.3193063-2-yosry.ahmed@linux.dev
This commit is contained in:
Yosry Ahmed 2025-02-27 01:27:07 +00:00 committed by Ingo Molnar
parent 8442df2b49
commit 549435aab4
6 changed files with 12 additions and 8 deletions
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2
arch/x86/include/asm/nospec-branch.h
View File

@ -515,7 +515,7 @@ extern u64 x86_pred_cmd;
static inline void indirect_branch_prediction_barrier(void)
{
alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_USE_IBPB);
alternative_msr_write(MSR_IA32_PRED_CMD, x86_pred_cmd, X86_FEATURE_IBPB);
}
/* The Intel SPEC CTRL MSR base value cache */

2
arch/x86/kernel/cpu/bugs.c
View File

@ -2272,7 +2272,7 @@ static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
if (ctrl == PR_SPEC_FORCE_DISABLE)
task_set_spec_ib_force_disable(task);
task_update_spec_tif(task);
if (task == current)
if (task == current && cpu_feature_enabled(X86_FEATURE_USE_IBPB))
indirect_branch_prediction_barrier();
break;
default:

3
arch/x86/kvm/svm/svm.c
View File

@ -1565,7 +1565,8 @@ static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
if (sd->current_vmcb != svm->vmcb) {
sd->current_vmcb = svm->vmcb;
if (!cpu_feature_enabled(X86_FEATURE_IBPB_ON_VMEXIT))
if (!cpu_feature_enabled(X86_FEATURE_IBPB_ON_VMEXIT) &&
cpu_feature_enabled(X86_FEATURE_USE_IBPB))
indirect_branch_prediction_barrier();
}
if (kvm_vcpu_apicv_active(vcpu))

3
arch/x86/kvm/vmx/nested.c
View File

@ -5026,7 +5026,8 @@ void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason,
* doesn't isolate different VMCSs, i.e. in this case, doesn't provide
* separate modes for L2 vs L1.
*/
if (guest_cpu_cap_has(vcpu, X86_FEATURE_SPEC_CTRL))
if (guest_cpu_cap_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
cpu_feature_enabled(X86_FEATURE_USE_IBPB))
indirect_branch_prediction_barrier();
/* Update any VMCS fields that might have changed while L2 ran */

3
arch/x86/kvm/vmx/vmx.c
View File

@ -1477,7 +1477,8 @@ void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
* performs IBPB on nested VM-Exit (a single nested transition
* may switch the active VMCS multiple times).
*/
if (!buddy || WARN_ON_ONCE(buddy->vmcs != prev))
if (cpu_feature_enabled(X86_FEATURE_USE_IBPB) &&
(!buddy || WARN_ON_ONCE(buddy->vmcs != prev)))
indirect_branch_prediction_barrier();
}

7
arch/x86/mm/tlb.c
View File

@ -437,7 +437,8 @@ static void cond_mitigation(struct task_struct *next)
* both have the IBPB bit set.
*/
if (next_mm != prev_mm &&
(next_mm | prev_mm) & LAST_USER_MM_IBPB)
(next_mm | prev_mm) & LAST_USER_MM_IBPB &&
cpu_feature_enabled(X86_FEATURE_USE_IBPB))
indirect_branch_prediction_barrier();
}
@ -447,8 +448,8 @@ static void cond_mitigation(struct task_struct *next)
* different context than the user space task which ran
* last on this CPU.
*/
if ((prev_mm & ~LAST_USER_MM_SPEC_MASK) !=
(unsigned long)next->mm)
if ((prev_mm & ~LAST_USER_MM_SPEC_MASK) != (unsigned long)next->mm &&
cpu_feature_enabled(X86_FEATURE_USE_IBPB))
indirect_branch_prediction_barrier();
}