From 5480662e110786daf49bbb6eaa29a45717490249 Mon Sep 17 00:00:00 2001
From: Ryan Chen <ryan_chen@aspeedtech.com>
Date: Wed, 24 Nov 2021 13:24:31 +0800
Subject: [PATCH] clk:ast2600 update AXI/AHB clock frequency ratio

Change-Id: I7c5e77ed669a35ba5574a2f796ac4e28719db8ff
---
 drivers/clk/clk-ast2600.c | 33 +++++++++++++++------------------
 1 file changed, 15 insertions(+), 18 deletions(-)

diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
index 94c1b3668f24..1af06a43b246 100644
--- a/drivers/clk/clk-ast2600.c
+++ b/drivers/clk/clk-ast2600.c
@@ -773,14 +773,14 @@ static int __init aspeed_g6_clk_init(void)
 core_initcall(aspeed_g6_clk_init);
 
 static const u32 ast2600_a0_axi_ahb_div_table[] = {
-	2, 2, 3, 5,
+	2, 2, 3, 4,
 };
 
-static const u32 ast2600_a1_axi_ahb_div0_tbl[] = {
+static u32 ast2600_a1_axi_ahb_div0_tbl[] = {
 	3, 2, 3, 4,
 };
 
-static const u32 ast2600_a1_axi_ahb_div1_tbl[] = {
+static u32 ast2600_a1_axi_ahb_div1_tbl[] = {
 	3, 4, 6, 8,
 };
 
@@ -814,27 +814,24 @@ static void __init aspeed_g6_cc(struct regmap *map)
 	regmap_read(map, ASPEED_APLL_PARAM, &val);
 	aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
 
-	/* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
-	regmap_read(map, ASPEED_G6_STRAP1, &val);
-	if (val & BIT(16))
-		axi_div = 1;
-	else
-		axi_div = 2;
 
+	regmap_read(map, ASPEED_G6_STRAP1, &val);
 	divbits = (val >> 11) & 0x3;
 	regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
-	if (chip_id & BIT(16)) {
-		if (!divbits) {
-			ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];
-			if (val & BIT(16))
-				ahb_div *= 2;
+	if ((chip_id & CHIP_REVISION_ID) >> 16) {
+		//ast2600a1
+		if (val & BIT(16)) {
+			ast2600_a1_axi_ahb_div1_tbl[0] = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x7] * 2;
+			axi_div = 1;
+			ahb_div = ast2600_a1_axi_ahb_div1_tbl[divbits];
 		} else {
-			if (val & BIT(16))
-				ahb_div = ast2600_a1_axi_ahb_div1_tbl[divbits];
-			else
-				ahb_div = ast2600_a1_axi_ahb_div0_tbl[divbits];
+			ast2600_a1_axi_ahb_div0_tbl[0] = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x7];
+			axi_div = 2;
+			ahb_div = ast2600_a1_axi_ahb_div0_tbl[divbits];
 		}
 	} else {
+		//ast2600a0 : fix axi = hpll/2
+		axi_div = 2;
 		ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
 	}