github-mirror/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux.git synced 2026-07-27 09:36:22 +02:00
Code Issues Actions Packages Projects Releases Wiki Activity Graph

drm/msm/registers: Add perfcntr json

Browse Source 
Pull in perfcntr json and wire up generation of perfcntr tables.

Sync from mesa commit a573e25b6dcd ("freedreno/registers: Gen8 perfcntr
fixes")

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/728204/
Message-ID: <20260526145137.160554-6-robin.clark@oss.qualcomm.com>
This commit is contained in:
Rob Clark 2026-05-26 07:50:39 -07:00
parent 510fad8aa4
commit 5442bafd7d
7 changed files with 891 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
drivers/gpu/drm/msm/Makefile
View File

@ -176,6 +176,11 @@ quiet_cmd_headergen = GENHDR $@
cmd_headergen = mkdir -p $(obj)/generated && $(PYTHON3) $(src)/registers/gen_header.py \
$(headergen-opts) --rnn $(src)/registers --xml $< c-defines > $@
# TODO how to do this for a2xx/a5xx which have different .xml arg?
quiet_cmd_headergen_json = GENHDRJSN $@
cmd_headergen_json = mkdir -p $(obj)/generated && $(PYTHON3) $(src)/registers/gen_header.py \
$(headergen-opts) --rnn $(src)/registers --xml $(filter %.xml,$^) perfcntrs --json $< > $@
$(obj)/generated/%.xml.h: $(src)/registers/adreno/%.xml \
$(src)/registers/adreno/adreno_common.xml \
$(src)/registers/adreno/adreno_pm4.xml \
@ -192,6 +197,24 @@ $(obj)/generated/%.xml.h: $(src)/registers/display/%.xml \
FORCE
$(call if_changed,headergen)
ADRENO_PERFCNTRS =
define adreno_perfcntrs
ADRENO_PERFCNTRS += generated/$(1)_perfcntrs.json.c
$$(obj)/generated/$(1)_perfcntrs.json.c: $$(src)/registers/adreno/$(1)_perfcntrs.json \
$$(src)/registers/adreno/$(2).xml \
FORCE
$$(call if_changed,headergen_json)
endef
$(eval $(call adreno_perfcntrs,a2xx,a2xx))
$(eval $(call adreno_perfcntrs,a5xx,a5xx))
$(eval $(call adreno_perfcntrs,a6xx,a6xx))
$(eval $(call adreno_perfcntrs,a7xx,a6xx))
$(eval $(call adreno_perfcntrs,a8xx,a6xx))
adreno-y += $(ADRENO_PERFCNTRS:.c=.o)
ADRENO_HEADERS = \
generated/a2xx.xml.h \
generated/a3xx.xml.h \
@ -223,7 +246,7 @@ DISPLAY_HEADERS = \
generated/mdss.xml.h \
generated/sfpb.xml.h
$(addprefix $(obj)/,$(adreno-y)): $(addprefix $(obj)/,$(ADRENO_HEADERS))
$(addprefix $(obj)/,$(msm-y)): $(addprefix $(obj)/,$(ADRENO_HEADERS))
$(addprefix $(obj)/,$(msm-display-y)): $(addprefix $(obj)/,$(DISPLAY_HEADERS))
targets += $(ADRENO_HEADERS) $(DISPLAY_HEADERS)
targets += $(ADRENO_HEADERS) $(DISPLAY_HEADERS) $(ADRENO_PERFCNTRS)

48
drivers/gpu/drm/msm/msm_perfcntr.h Normal file
View File

@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef __MSM_PERFCNTR_H__
#define __MSM_PERFCNTR_H__
#include "linux/array_size.h"
#include "adreno_common.xml.h"
/*
* This is a subset of the tables used by mesa. We don't need to
* enumerate the countables on the kernel side.
*/
/* Describes a single counter: */
struct msm_perfcntr_counter {
/* offset of the SELect register to choose what to count: */
unsigned select_reg;
/* additional SEL regs to enable slice counters (gen8+) */
unsigned slice_select_regs[2];
/* offset of the lo/hi 32b to read current counter value: */
unsigned counter_reg_lo;
unsigned counter_reg_hi;
/* TODO some counters have enable/clear registers */
};
/* Describes an entire counter group: */
struct msm_perfcntr_group {
const char *name;
enum adreno_pipe pipe;
unsigned num_counters;
const struct msm_perfcntr_counter *counters;
};
#define GROUP(_name, _pipe, _counters, _countables) { \
.name = _name, \
.pipe = _pipe, \
.num_counters = ARRAY_SIZE(_counters), \
.counters = _counters, \
}
#define fd_perfcntr_counter msm_perfcntr_counter
#define fd_perfcntr_group msm_perfcntr_group
#endif /* __MSM_PERFCNTR_H__ */

109
drivers/gpu/drm/msm/registers/adreno/a2xx_perfcntrs.json Normal file
View File

@ -0,0 +1,109 @@
{
"chip": "A2XX",
"groups": [
{
"name": "CP",
"num": 1,
"select": "CP_PERFCOUNTER_SELECT",
"counter_lo": "CP_PERFCOUNTER_LO",
"counter_hi": "CP_PERFCOUNTER_HI",
"countable_type": "a2xx_cp_perfcount_sel"
},
{
"name": "PA_SU",
"num": 4,
"select": "PA_SU_PERFCOUNTER{}_SELECT",
"counter_lo": "PA_SU_PERFCOUNTER{}_LOW",
"counter_hi": "PA_SU_PERFCOUNTER{}_HI",
"countable_type": "a2xx_su_perfcnt_select"
},
{
"name": "PA_SC",
"num": 1,
"select": "PA_SC_PERFCOUNTER{}_SELECT",
"counter_lo": "PA_SC_PERFCOUNTER{}_LOW",
"counter_hi": "PA_SC_PERFCOUNTER{}_HI",
"countable_type": "a2xx_sc_perfcnt_select"
},
{
"name": "VGT",
"num": 4,
"select": "VGT_PERFCOUNTER{}_SELECT",
"counter_lo": "VGT_PERFCOUNTER{}_LOW",
"counter_hi": "VGT_PERFCOUNTER{}_HI",
"countable_type": "a2xx_vgt_perfcount_select"
},
{
"name": "TCR",
"num": 2,
"select": "TCR_PERFCOUNTER{}_SELECT",
"counter_lo": "TCR_PERFCOUNTER{}_LOW",
"counter_hi": "TCR_PERFCOUNTER{}_HI",
"countable_type": "a2xx_tcr_perfcount_select"
},
{
"name": "TP0",
"num": 2,
"select": "TP0_PERFCOUNTER{}_SELECT",
"counter_lo": "TP0_PERFCOUNTER{}_LOW",
"counter_hi": "TP0_PERFCOUNTER{}_HI",
"countable_type": "a2xx_tp_perfcount_select"
},
{
"name": "TCM",
"num": 2,
"select": "TCM_PERFCOUNTER{}_SELECT",
"counter_lo": "TCM_PERFCOUNTER{}_LOW",
"counter_hi": "TCM_PERFCOUNTER{}_HI",
"countable_type": "a2xx_tcm_perfcount_select"
},
{
"name": "TCF",
"num": 12,
"select": "TCF_PERFCOUNTER{}_SELECT",
"counter_lo": "TCF_PERFCOUNTER{}_LOW",
"counter_hi": "TCF_PERFCOUNTER{}_HI",
"countable_type": "a2xx_tcf_perfcount_select"
},
{
"name": "SQ",
"num": 4,
"select": "SQ_PERFCOUNTER{}_SELECT",
"counter_lo": "SQ_PERFCOUNTER{}_LOW",
"counter_hi": "SQ_PERFCOUNTER{}_HI",
"countable_type": "a2xx_sq_perfcnt_select"
},
{
"name": "SX",
"num": 1,
"select": "SX_PERFCOUNTER{}_SELECT",
"counter_lo": "SX_PERFCOUNTER{}_LOW",
"counter_hi": "SX_PERFCOUNTER{}_HI",
"countable_type": "a2xx_sx_perfcnt_select"
},
{
"name": "MH",
"num": 2,
"select": "MH_PERFCOUNTER{}_SELECT",
"counter_lo": "MH_PERFCOUNTER{}_LOW",
"counter_hi": "MH_PERFCOUNTER{}_HI",
"countable_type": "a2xx_mh_perfcnt_select"
},
{
"name": "RBBM",
"num": 2,
"select": "RBBM_PERFCOUNTER{}_SELECT",
"counter_lo": "RBBM_PERFCOUNTER{}_LO",
"counter_hi": "RBBM_PERFCOUNTER{}_HI",
"countable_type": "a2xx_rbbm_perfcount1_sel"
},
{
"name": "RB",
"num": 4,
"select": "RB_PERFCOUNTER{}_SELECT",
"counter_lo": "RB_PERFCOUNTER{}_LOW",
"counter_hi": "RB_PERFCOUNTER{}_HI",
"countable_type": "a2xx_rb_perfcnt_select"
}
]
}

128
drivers/gpu/drm/msm/registers/adreno/a5xx_perfcntrs.json Normal file
View File

@ -0,0 +1,128 @@
{
"chip": "A5XX",
"groups": [
{
"name": "CP",
"num": 8,
"reserved": [ 0 ],
"select": "CP_PERFCTR_CP_SEL_{}",
"counter_lo": "RBBM_PERFCTR_CP_{}_LO",
"counter_hi": "RBBM_PERFCTR_CP_{}_HI",
"countable_type": "a5xx_cp_perfcounter_select"
},
{
"name": "CCU",
"num": 4,
"select": "RB_PERFCTR_CCU_SEL_{}",
"counter_lo": "RBBM_PERFCTR_CCU_{}_LO",
"counter_hi": "RBBM_PERFCTR_CCU_{}_HI",
"countable_type": "a5xx_ccu_perfcounter_select"
},
{
"name": "TSE",
"num": 4,
"select": "GRAS_PERFCTR_TSE_SEL_{}",
"counter_lo": "RBBM_PERFCTR_TSE_{}_LO",
"counter_hi": "RBBM_PERFCTR_TSE_{}_HI",
"countable_type": "a5xx_tse_perfcounter_select"
},
{
"name": "RAS",
"num": 4,
"select": "GRAS_PERFCTR_RAS_SEL_{}",
"counter_lo": "RBBM_PERFCTR_RAS_{}_LO",
"counter_hi": "RBBM_PERFCTR_RAS_{}_HI",
"countable_type": "a5xx_ras_perfcounter_select"
},
{
"name": "LRZ",
"num": 4,
"select": "GRAS_PERFCTR_LRZ_SEL_{}",
"counter_lo": "RBBM_PERFCTR_LRZ_{}_LO",
"counter_hi": "RBBM_PERFCTR_LRZ_{}_HI",
"countable_type": "a5xx_lrz_perfcounter_select"
},
{
"name": "HLSQ",
"num": 8,
"select": "HLSQ_PERFCTR_HLSQ_SEL_{}",
"counter_lo": "RBBM_PERFCTR_HLSQ_{}_LO",
"counter_hi": "RBBM_PERFCTR_HLSQ_{}_HI",
"countable_type": "a5xx_hlsq_perfcounter_select"
},
{
"name": "PC",
"num": 8,
"select": "PC_PERFCTR_PC_SEL_{}",
"counter_lo": "RBBM_PERFCTR_PC_{}_LO",
"counter_hi": "RBBM_PERFCTR_PC_{}_HI",
"countable_type": "a5xx_pc_perfcounter_select"
},
{
"name": "RB",
"num": 8,
"select": "RB_PERFCTR_RB_SEL_{}",
"counter_lo": "RBBM_PERFCTR_RB_{}_LO",
"counter_hi": "RBBM_PERFCTR_RB_{}_HI",
"countable_type": "a5xx_rb_perfcounter_select"
},
{
"name": "RBBM",
"num": 4,
"reserved": [ 0 ],
"select": "RBBM_PERFCTR_RBBM_SEL_{}",
"counter_lo": "RBBM_PERFCTR_RBBM_{}_LO",
"counter_hi": "RBBM_PERFCTR_RBBM_{}_HI",
"countable_type": "a5xx_rbbm_perfcounter_select"
},
{
"name": "SP",
"num": 12,
"reserved": [ 0 ],
"select": "SP_PERFCTR_SP_SEL_{}",
"counter_lo": "RBBM_PERFCTR_SP_{}_LO",
"counter_hi": "RBBM_PERFCTR_SP_{}_HI",
"countable_type": "a5xx_sp_perfcounter_select"
},
{
"name": "TP",
"num": 8,
"select": "TPL1_PERFCTR_TP_SEL_{}",
"counter_lo": "RBBM_PERFCTR_TP_{}_LO",
"counter_hi": "RBBM_PERFCTR_TP_{}_HI",
"countable_type": "a5xx_tp_perfcounter_select"
},
{
"name": "UCHE",
"num": 8,
"select": "UCHE_PERFCTR_UCHE_SEL_{}",
"counter_lo": "RBBM_PERFCTR_UCHE_{}_LO",
"counter_hi": "RBBM_PERFCTR_UCHE_{}_HI",
"countable_type": "a5xx_uche_perfcounter_select"
},
{
"name": "VFD",
"num": 8,
"select": "VFD_PERFCTR_VFD_SEL_{}",
"counter_lo": "RBBM_PERFCTR_VFD_{}_LO",
"counter_hi": "RBBM_PERFCTR_VFD_{}_HI",
"countable_type": "a5xx_vfd_perfcounter_select"
},
{
"name": "VPC",
"num": 4,
"select": "VPC_PERFCTR_VPC_SEL_{}",
"counter_lo": "RBBM_PERFCTR_VPC_{}_LO",
"counter_hi": "RBBM_PERFCTR_VPC_{}_HI",
"countable_type": "a5xx_vpc_perfcounter_select"
},
{
"name": "VSC",
"num": 2,
"select": "VSC_PERFCTR_VSC_SEL_{}",
"counter_lo": "RBBM_PERFCTR_VSC_{}_LO",
"counter_hi": "RBBM_PERFCTR_VSC_{}_HI",
"countable_type": "a5xx_vsc_perfcounter_select"
}
]
}

112
drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json Normal file
View File

@ -0,0 +1,112 @@
{
"chip": "A6XX",
"groups": [
{
"name": "CP",
"num": 14,
"reserved": [ 0 ],
"select": "CP_PERFCTR_CP_SEL",
"counter": "RBBM_PERFCTR_CP",
"countable_type": "a6xx_cp_perfcounter_select"
},
{
"name": "CCU",
"num": 5,
"select": "RB_PERFCTR_CCU_SEL",
"counter": "RBBM_PERFCTR_CCU",
"countable_type": "a6xx_ccu_perfcounter_select"
},
{
"name": "TSE",
"num": 4,
"select": "GRAS_PERFCTR_TSE_SEL",
"counter": "RBBM_PERFCTR_TSE",
"countable_type": "a6xx_tse_perfcounter_select"
},
{
"name": "RAS",
"num": 4,
"select": "GRAS_PERFCTR_RAS_SEL",
"counter": "RBBM_PERFCTR_RAS",
"countable_type": "a6xx_ras_perfcounter_select"
},
{
"name": "LRZ",
"num": 4,
"select": "GRAS_PERFCTR_LRZ_SEL",
"counter": "RBBM_PERFCTR_LRZ",
"countable_type": "a6xx_lrz_perfcounter_select"
},
{
"name": "CMP",
"num": 4,
"select": "RB_PERFCTR_CMP_SEL",
"counter": "RBBM_PERFCTR_CMP",
"countable_type": "a6xx_cmp_perfcounter_select"
},
{
"name": "HLSQ",
"num": 6,
"select": "HLSQ_PERFCTR_HLSQ_SEL",
"counter": "RBBM_PERFCTR_HLSQ",
"countable_type": "a6xx_hlsq_perfcounter_select"
},
{
"name": "PC",
"num": 8,
"select": "PC_PERFCTR_PC_SEL",
"counter": "RBBM_PERFCTR_PC",
"countable_type": "a6xx_pc_perfcounter_select"
},
{
"name": "RB",
"num": 8,
"select": "RB_PERFCTR_RB_SEL",
"counter": "RBBM_PERFCTR_RB",
"countable_type": "a6xx_rb_perfcounter_select"
},
{
"name": "SP",
"num": 24,
"reserved": [ 0 ],
"select": "SP_PERFCTR_SP_SEL",
"counter": "RBBM_PERFCTR_SP",
"countable_type": "a6xx_sp_perfcounter_select"
},
{
"name": "TP",
"num": 12,
"select": "TPL1_PERFCTR_TP_SEL",
"counter": "RBBM_PERFCTR_TP",
"countable_type": "a6xx_tp_perfcounter_select"
},
{
"name": "UCHE",
"num": 12,
"select": "UCHE_PERFCTR_UCHE_SEL",
"counter": "RBBM_PERFCTR_UCHE",
"countable_type": "a6xx_uche_perfcounter_select"
},
{
"name": "VFD",
"num": 8,
"select": "VFD_PERFCTR_VFD_SEL",
"counter": "RBBM_PERFCTR_VFD",
"countable_type": "a6xx_vfd_perfcounter_select"
},
{
"name": "VPC",
"num": 6,
"select": "VPC_PERFCTR_VPC_SEL",
"counter": "RBBM_PERFCTR_VPC",
"countable_type": "a6xx_vpc_perfcounter_select"
},
{
"name": "VSC",
"num": 2,
"select": "VSC_PERFCTR_VSC_SEL",
"counter": "RBBM_PERFCTR_VSC",
"countable_type": "a6xx_vsc_perfcounter_select"
}
]
}

228
drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json Normal file
View File

@ -0,0 +1,228 @@
{
"chip": "A7XX",
"groups": [
{
"name": "CP",
"num": 14,
"reserved": [ 0 ],
"select": "CP_PERFCTR_CP_SEL",
"counter": "RBBM_PERFCTR_CP",
"countable_type": "a7xx_cp_perfcounter_select"
},
{
"name": "RBBM",
"num": 4,
"select": "RBBM_PERFCTR_RBBM_SEL",
"counter": "RBBM_PERFCTR_RBBM",
"countable_type": "a7xx_rbbm_perfcounter_select"
},
{
"name": "PC",
"pipe": "BR",
"num": 8,
"select": "PC_PERFCTR_PC_SEL",
"counter": "RBBM_PERFCTR_PC",
"countable_type": "a7xx_pc_perfcounter_select"
},
{
"name": "VFD",
"pipe": "BR",
"num": 8,
"select": "VFD_PERFCTR_VFD_SEL",
"counter": "RBBM_PERFCTR_VFD",
"countable_type": "a7xx_vfd_perfcounter_select"
},
{
"name": "HLSQ",
"pipe": "BR",
"num": 6,
"select": "SP_PERFCTR_HLSQ_SEL",
"counter": "RBBM_PERFCTR_HLSQ",
"countable_type": "a7xx_hlsq_perfcounter_select"
},
{
"name": "VPC",
"pipe": "BR",
"num": 6,
"select": "VPC_PERFCTR_VPC_SEL",
"counter": "RBBM_PERFCTR_VPC",
"countable_type": "a7xx_vpc_perfcounter_select"
},
{
"name": "TSE",
"pipe": "BR",
"num": 4,
"select": "GRAS_PERFCTR_TSE_SEL",
"counter": "RBBM_PERFCTR_TSE",
"countable_type": "a7xx_tse_perfcounter_select"
},
{
"name": "RAS",
"pipe": "BR",
"num": 4,
"select": "GRAS_PERFCTR_RAS_SEL",
"counter": "RBBM_PERFCTR_RAS",
"countable_type": "a7xx_ras_perfcounter_select"
},
{
"name": "UCHE",
"num": 12,
"select": "UCHE_PERFCTR_UCHE_SEL",
"counter": "RBBM_PERFCTR_UCHE",
"countable_type": "a7xx_uche_perfcounter_select"
},
{
"name": "TP",
"pipe": "BR",
"num": 12,
"select": "TPL1_PERFCTR_TP_SEL",
"counter": "RBBM_PERFCTR_TP",
"countable_type": "a7xx_tp_perfcounter_select"
},
{
"name": "SP",
"pipe": "BR",
"num": 24,
"select": "SP_PERFCTR_SP_SEL",
"counter": "RBBM_PERFCTR_SP",
"countable_type": "a7xx_sp_perfcounter_select"
},
{
"name": "RB",
"num": 8,
"select": "RB_PERFCTR_RB_SEL",
"counter": "RBBM_PERFCTR_RB",
"countable_type": "a7xx_rb_perfcounter_select"
},
{
"name": "VSC",
"num": 2,
"select": "VSC_PERFCTR_VSC_SEL",
"counter": "RBBM_PERFCTR_VSC",
"countable_type": "a7xx_vsc_perfcounter_select"
},
{
"name": "CCU",
"num": 5,
"select": "RB_PERFCTR_CCU_SEL",
"counter": "RBBM_PERFCTR_CCU",
"countable_type": "a7xx_ccu_perfcounter_select"
},
{
"name": "LRZ",
"pipe": "BR",
"num": 4,
"select": "GRAS_PERFCTR_LRZ_SEL",
"counter": "RBBM_PERFCTR_LRZ",
"countable_type": "a7xx_lrz_perfcounter_select"
},
{
"name": "CMP",
"num": 4,
"select": "RB_PERFCTR_CMP_SEL",
"counter": "RBBM_PERFCTR_CMP",
"countable_type": "a7xx_cmp_perfcounter_select"
},
{
"name": "UFC",
"pipe": "BR",
"num": 4,
"select": "RB_PERFCTR_UFC_SEL",
"counter": "RBBM_PERFCTR_UFC",
"countable_type": "a7xx_ufc_perfcounter_select"
},
{
"name": "BV_CP",
"num": 7,
"select": "CP_BV_PERFCTR_CP_SEL",
"counter": "RBBM_PERFCTR2_CP",
"countable_type": "a7xx_cp_perfcounter_select"
},
{
"name": "BV_PC",
"pipe": "BV",
"num": 8,
"select_offset": 8,
"select": "PC_PERFCTR_PC_SEL",
"counter": "RBBM_PERFCTR_BV_PC",
"countable_type": "a7xx_pc_perfcounter_select"
},
{
"name": "BV_VFD",
"pipe": "BV",
"num": 8,
"select_offset": 8,
"select": "VFD_PERFCTR_VFD_SEL",
"counter": "RBBM_PERFCTR_BV_VFD",
"countable_type": "a7xx_vfd_perfcounter_select"
},
{
"name": "BV_VPC",
"pipe": "BV",
"num": 6,
"select_offset": 6,
"select": "VPC_PERFCTR_VPC_SEL",
"counter": "RBBM_PERFCTR_BV_VPC",
"countable_type": "a7xx_vpc_perfcounter_select"
},
{
"name": "BV_TP",
"pipe": "BV",
"num": 6,
"select_offset": 12,
"select": "TPL1_PERFCTR_TP_SEL",
"counter": "RBBM_PERFCTR2_TP",
"countable_type": "a7xx_tp_perfcounter_select"
},
{
"name": "BV_SP",
"pipe": "BV",
"num": 12,
"select_offset": 24,
"select": "SP_PERFCTR_SP_SEL",
"counter": "RBBM_PERFCTR2_SP",
"countable_type": "a7xx_sp_perfcounter_select"
},
{
"name": "BV_UFC",
"pipe": "BV",
"num": 2,
"select_offset": 4,
"select": "RB_PERFCTR_UFC_SEL",
"counter": "RBBM_PERFCTR2_UFC",
"countable_type": "a7xx_ufc_perfcounter_select"
},
{
"name": "BV_TSE",
"pipe": "BV",
"num": 4,
"select": "GRAS_PERFCTR_TSE_SEL",
"counter": "RBBM_PERFCTR_BV_TSE",
"countable_type": "a7xx_tse_perfcounter_select"
},
{
"name": "BV_RAS",
"pipe": "BV",
"num": 4,
"select": "GRAS_PERFCTR_RAS_SEL",
"counter": "RBBM_PERFCTR_BV_RAS",
"countable_type": "a7xx_ras_perfcounter_select"
},
{
"name": "BV_LRZ",
"pipe": "BV",
"num": 4,
"select": "GRAS_PERFCTR_LRZ_SEL",
"counter": "RBBM_PERFCTR_BV_LRZ",
"countable_type": "a7xx_lrz_perfcounter_select"
},
{
"name": "BV_HLSQ",
"pipe": "BV",
"num": 6,
"select": "SP_PERFCTR_HLSQ_SEL",
"counter": "RBBM_PERFCTR2_HLSQ",
"countable_type": "a7xx_hlsq_perfcounter_select"
}
]
}

241
drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json Normal file
View File

@ -0,0 +1,241 @@
{
"chip": "A8XX",
"groups": [
{
"name": "CP",
"num": 14,
"reserved": [ 0 ],
"select": "CP_PERFCTR_CP_SEL",
"counter": "RBBM_PERFCTR_CP",
"countable_type": "a8xx_cp_perfcounter_select"
},
{
"name": "RBBM",
"num": 4,
"select": "RBBM_PERFCTR_RBBM_SEL",
"slice_select": [ "RBBM_SLICE_PERFCTR_RBBM_SEL" ],
"counter": "RBBM_PERFCTR_RBBM",
"countable_type": "a8xx_rbbm_perfcounter_select"
},
{
"name": "PC",
"pipe": "BR",
"num": 8,
"select": "PC_PERFCTR_PC_SEL",
"slice_select": [ "PC_SLICE_PERFCTR_PC_SEL" ],
"counter": "RBBM_PERFCTR_PC",
"countable_type": "a8xx_pc_perfcounter_select"
},
{
"name": "VFD",
"pipe": "BR",
"num": 8,
"select": "VFD_PERFCTR_VFD_SEL",
"counter": "RBBM_PERFCTR_VFD",
"countable_type": "a8xx_vfd_perfcounter_select"
},
{
"name": "HLSQ",
"pipe": "BR",
"num": 6,
"select": "SP_PERFCTR_HLSQ_SEL",
"slice_select": [ "SP_PERFCTR_HLSQ_SEL_2" ],
"counter": "RBBM_PERFCTR_HLSQ",
"countable_type": "a8xx_hlsq_perfcounter_select"
},
{
"name": "VPC",
"pipe": "BR",
"num": 6,
"select": "VPC_PERFCTR_VPC_SEL",
"slice_select": [ "VPC_PERFCTR_VPC_SEL_1", "VPC_PERFCTR_VPC_SEL_2" ],
"counter": "RBBM_PERFCTR_VPC",
"countable_type": "a8xx_vpc_perfcounter_select"
},
{
"name": "TSE",
"pipe": "BR",
"num": 4,
"select": "GRAS_PERFCTR_TSE_SEL",
"slice_select": [ "GRAS_PERFCTR_TSEFE_SEL" ],
"counter": "RBBM_PERFCTR_TSE",
"countable_type": "a8xx_tse_perfcounter_select"
},
{
"name": "RAS",
"pipe": "BR",
"num": 4,
"select": "GRAS_PERFCTR_RAS_SEL",
"counter": "RBBM_PERFCTR_RAS",
"countable_type": "a8xx_ras_perfcounter_select"
},
{
"name": "UCHE",
"num": 24,
"select": "UCHE_PERFCTR_UCHE_SEL",
"counter": "RBBM_PERFCTR_UCHE",
"countable_type": "a8xx_uche_perfcounter_select"
},
{
"name": "TP",
"pipe": "BR",
"num": 12,
"select": "TPL1_PERFCTR_TP_SEL",
"counter": "RBBM_PERFCTR_TP",
"countable_type": "a8xx_tp_perfcounter_select"
},
{
"name": "SP",
"pipe": "BR",
"num": 24,
"select": "SP_PERFCTR_SP_SEL",
"counter": "RBBM_PERFCTR_SP",
"countable_type": "a8xx_sp_perfcounter_select"
},
{
"name": "RB",
"pipe": "BR",
"num": 8,
"select": "RB_PERFCTR_RB_SEL",
"counter": "RBBM_PERFCTR_RB",
"countable_type": "a8xx_rb_perfcounter_select"
},
{
"name": "VSC",
"num": 2,
"select": "VSC_PERFCTR_VSC_SEL",
"counter": "RBBM_PERFCTR_VSC",
"countable_type": "a8xx_vsc_perfcounter_select"
},
{
"name": "CCU",
"pipe": "BR",
"num": 5,
"select": "RB_PERFCTR_CCU_SEL",
"counter": "RBBM_PERFCTR_CCU",
"countable_type": "a8xx_ccu_perfcounter_select"
},
{
"name": "LRZ",
"pipe": "BR",
"num": 4,
"select": "GRAS_PERFCTR_LRZ_SEL",
"counter": "RBBM_PERFCTR_LRZ",
"countable_type": "a8xx_lrz_perfcounter_select"
},
{
"name": "CMP",
"pipe": "BR",
"num": 4,
"select": "RB_PERFCTR_CMP_SEL",
"counter": "RBBM_PERFCTR_CMP",
"countable_type": "a8xx_cmp_perfcounter_select"
},
{
"name": "UFC",
"pipe": "BR",
"num": 4,
"select": "RB_PERFCTR_UFC_SEL",
"counter": "RBBM_PERFCTR_UFC",
"countable_type": "a8xx_ufc_perfcounter_select"
},
{
"name": "BV_CP",
"num": 7,
"select_offset": 14,
"select": "CP_PERFCTR_CP_SEL",
"counter": "RBBM_PERFCTR2_CP",
"countable_type": "a8xx_cp_perfcounter_select"
},
{
"name": "BV_PC",
"pipe": "BV",
"num": 8,
"select_offset": 8,
"select": "PC_PERFCTR_PC_SEL",
"slice_select": [ "PC_SLICE_PERFCTR_PC_SEL" ],
"counter": "RBBM_PERFCTR_BV_PC",
"countable_type": "a8xx_pc_perfcounter_select"
},
{
"name": "BV_VFD",
"pipe": "BV",
"num": 8,
"select_offset": 8,
"select": "VFD_PERFCTR_VFD_SEL",
"counter": "RBBM_PERFCTR_BV_VFD",
"countable_type": "a8xx_vfd_perfcounter_select"
},
{
"name": "BV_VPC",
"pipe": "BV",
"num": 6,
"select_offset": 6,
"select": "VPC_PERFCTR_VPC_SEL",
"slice_select": [ "VPC_PERFCTR_VPC_SEL_1", "VPC_PERFCTR_VPC_SEL_2" ],
"counter": "RBBM_PERFCTR_BV_VPC",
"countable_type": "a8xx_vpc_perfcounter_select"
},
{
"name": "BV_TP",
"pipe": "BV",
"num": 8,
"select_offset": 12,
"select": "TPL1_PERFCTR_TP_SEL",
"counter": "RBBM_PERFCTR2_TP",
"countable_type": "a8xx_tp_perfcounter_select"
},
{
"name": "BV_SP",
"pipe": "BV",
"num": 12,
"select_offset": 24,
"select": "SP_PERFCTR_SP_SEL",
"counter": "RBBM_PERFCTR2_SP",
"countable_type": "a8xx_sp_perfcounter_select"
},
{
"name": "BV_UFC",
"pipe": "BV",
"num": 2,
"select_offset": 4,
"select": "RB_PERFCTR_UFC_SEL",
"counter": "RBBM_PERFCTR2_UFC",
"countable_type": "a8xx_ufc_perfcounter_select"
},
{
"name": "BV_TSE",
"pipe": "BV",
"num": 4,
"select": "GRAS_PERFCTR_TSE_SEL",
"slice_select": [ "GRAS_PERFCTR_TSEFE_SEL" ],
"counter": "RBBM_PERFCTR_BV_TSE",
"countable_type": "a8xx_tse_perfcounter_select"
},
{
"name": "BV_RAS",
"pipe": "BV",
"num": 4,
"select": "GRAS_PERFCTR_RAS_SEL",
"counter": "RBBM_PERFCTR_BV_RAS",
"countable_type": "a8xx_ras_perfcounter_select"
},
{
"name": "BV_LRZ",
"pipe": "BV",
"num": 4,
"select": "GRAS_PERFCTR_LRZ_SEL",
"counter": "RBBM_PERFCTR_BV_LRZ",
"countable_type": "a8xx_lrz_perfcounter_select"
},
{
"name": "BV_HLSQ",
"pipe": "BV",
"num": 6,
"select": "SP_PERFCTR_HLSQ_SEL",
"slice_select": [ "SP_PERFCTR_HLSQ_SEL_2" ],
"counter": "RBBM_PERFCTR2_HLSQ",
"countable_type": "a8xx_hlsq_perfcounter_select"
}
]
}