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net: phy: dp83822: Add support for GPIO2 clock output

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The GPIO2 pin on the DP83822 can be configured as clock output. Add support
for configuration via DT.

Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dimitri Fedrau 2024-12-12 09:44:07 +01:00 committed by David S. Miller
parent a2d8af5745
commit 53e3b54095
1 changed files with 48 additions and 0 deletions
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48
drivers/net/phy/dp83822.c
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@ -30,6 +30,7 @@
#define MII_DP83822_FCSCR 0x14
#define MII_DP83822_RCSR 0x17
#define MII_DP83822_RESET_CTRL 0x1f
#define MII_DP83822_IOCTRL2 0x463
#define MII_DP83822_GENCFG 0x465
#define MII_DP83822_SOR1 0x467
@ -104,6 +105,18 @@
#define DP83822_RX_CLK_SHIFT BIT(12)
#define DP83822_TX_CLK_SHIFT BIT(11)
/* IOCTRL2 bits */
#define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4)
#define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0)
#define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF GENMASK(1, 0)
#define DP83822_CLK_SRC_MAC_IF 0x0
#define DP83822_CLK_SRC_XI 0x1
#define DP83822_CLK_SRC_INT_REF 0x2
#define DP83822_CLK_SRC_RMII_MASTER_MODE_REF 0x4
#define DP83822_CLK_SRC_FREE_RUNNING 0x6
#define DP83822_CLK_SRC_RECOVERED 0x7
/* SOR1 mode */
#define DP83822_STRAP_MODE1 0
#define DP83822_STRAP_MODE2 BIT(0)
@ -139,6 +152,8 @@ struct dp83822_private {
u8 cfg_dac_minus;
u8 cfg_dac_plus;
struct ethtool_wolinfo wol;
bool set_gpio2_clk_out;
u32 gpio2_clk_out;
};
static int dp83822_config_wol(struct phy_device *phydev,
@ -413,6 +428,15 @@ static int dp83822_config_init(struct phy_device *phydev)
int err = 0;
int bmcr;
if (dp83822->set_gpio2_clk_out)
phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2,
DP83822_IOCTRL2_GPIO2_CTRL |
DP83822_IOCTRL2_GPIO2_CLK_SRC,
FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL,
DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF) |
FIELD_PREP(DP83822_IOCTRL2_GPIO2_CLK_SRC,
dp83822->gpio2_clk_out));
if (phy_interface_is_rgmii(phydev)) {
rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
true);
@ -611,6 +635,7 @@ static int dp83822_of_init(struct phy_device *phydev)
{
struct dp83822_private *dp83822 = phydev->priv;
struct device *dev = &phydev->mdio.dev;
const char *of_val;
/* Signal detection for the PHY is only enabled if the FX_EN and the
* SD_EN pins are strapped. Signal detection can only enabled if FX_EN
@ -623,6 +648,29 @@ static int dp83822_of_init(struct phy_device *phydev)
dp83822->fx_enabled = device_property_present(dev,
"ti,fiber-mode");
if (!device_property_read_string(dev, "ti,gpio2-clk-out", &of_val)) {
if (strcmp(of_val, "mac-if") == 0) {
dp83822->gpio2_clk_out = DP83822_CLK_SRC_MAC_IF;
} else if (strcmp(of_val, "xi") == 0) {
dp83822->gpio2_clk_out = DP83822_CLK_SRC_XI;
} else if (strcmp(of_val, "int-ref") == 0) {
dp83822->gpio2_clk_out = DP83822_CLK_SRC_INT_REF;
} else if (strcmp(of_val, "rmii-master-mode-ref") == 0) {
dp83822->gpio2_clk_out = DP83822_CLK_SRC_RMII_MASTER_MODE_REF;
} else if (strcmp(of_val, "free-running") == 0) {
dp83822->gpio2_clk_out = DP83822_CLK_SRC_FREE_RUNNING;
} else if (strcmp(of_val, "recovered") == 0) {
dp83822->gpio2_clk_out = DP83822_CLK_SRC_RECOVERED;
} else {
phydev_err(phydev,
"Invalid value for ti,gpio2-clk-out property (%s)\n",
of_val);
return -EINVAL;
}
dp83822->set_gpio2_clk_out = true;
}
return 0;
}