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drm/amd/display: Expose mall capability

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[Why&How]
Export a debugfs file to report whether MALL cache is supported by the
asic or not.

Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aurabindo Pillai 2023-08-04 11:07:59 -04:00 committed by Alex Deucher
parent c183060031
commit 53d8e3beea
1 changed files with 19 additions and 0 deletions
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19
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
View File

@ -3605,6 +3605,23 @@ static int disable_hpd_get(void *data, u64 *val)
DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
disable_hpd_set, "%llu\n");
/*
* Returns 1 if hardware supports MALL cache
* 0 otherwise.
*/
static int capabilities_show(struct seq_file *m, void *unused)
{
struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
struct dc_caps caps = adev->dm.dc->caps;
bool mall_supported = caps.mall_size_total;
seq_printf(m, "mall: %s\n", mall_supported ? "yes" : "no");
return 0;
}
DEFINE_SHOW_ATTRIBUTE(capabilities);
/*
* Temporary w/a to force sst sequence in M42D DP2 mst receiver
* Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
@ -3798,6 +3815,8 @@ void dtn_debugfs_init(struct amdgpu_device *adev)
debugfs_create_file("amdgpu_mst_topology", 0444, root,
adev, &mst_topo_fops);
debugfs_create_file("amdgpu_dm_capabilities", 0444, root,
adev, &capabilities_fops);
debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
&dtn_log_fops);
debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,