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Amlogic ARM64 DT for v6.16:

Browse Source 
- Amlogic A4 Pinctrl support
 - UART RX/TX pull-up pinconf properties for all SoCs
 - SARADC support for the S905L SoC variant
 - Drop clock-latency in CPU node
 - Amlogic clk measure support for S4 & C3 Socs
 - Amlogic S6/S7/S7D initial support
 - I2C default pull-up bias pinconf property on Amlogic GXL based boards
 - Amlogic A4 & A5 Reset Controller support
 - New Boards:
   - Amlogic S6 BL209 Reference Board
   - Amlogic S7 BP201 Reference Board
   - Amlogic S7D BM202 Reference Board
   - Amlogic S805Y xiaomi-aquaman/Mi TV Stick
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Merge tag 'amlogic-arm64-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt

Amlogic ARM64 DT for v6.16:
- Amlogic A4 Pinctrl support
- UART RX/TX pull-up pinconf properties for all SoCs
- SARADC support for the S905L SoC variant
- Drop clock-latency in CPU node
- Amlogic clk measure support for S4 & C3 Socs
- Amlogic S6/S7/S7D initial support
- I2C default pull-up bias pinconf property on Amlogic GXL based boards
- Amlogic A4 & A5 Reset Controller support
- New Boards:
  - Amlogic S6 BL209 Reference Board
  - Amlogic S7 BP201 Reference Board
  - Amlogic S7D BM202 Reference Board
  - Amlogic S805Y xiaomi-aquaman/Mi TV Stick

* tag 'amlogic-arm64-dt-for-v6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: (21 commits)
  arm64: dts: amlogic: Add A5 Reset Controller
  arm64: dts: amlogic: Add A4 Reset Controller
  arm64: dts: amlogic: add support for xiaomi-aquaman/Mi TV Stick
  dt-bindings: arm: amlogic: add S805Y and Mi TV Stick
  arm64: dts: amlogic: gxl: set i2c bias to pull-up
  arm64: dts: add support for S7D based Amlogic BM202
  arm64: dts: add support for S7 based Amlogic BP201
  arm64: dts: add support for S6 based Amlogic BL209
  dt-bindings: arm: amlogic: add S7D support
  dt-bindings: arm: amlogic: add S7 support
  dt-bindings: arm: amlogic: add S6 support
  arm64: dts: amlogic: S4: Add clk-measure controller node
  arm64: dts: amlogic: C3: Add clk-measure controller node
  arm64: dts: amlogic: Drop redundant CPU "clock-latency"
  arm64: dts: amlogic: gxlx-s905l-p271: add saradc compatible
  arm64: dts: amlogic: a1: enable UART RX and TX pull up by default
  arm64: dts: amlogic: axg: enable UART RX and TX pull up by default
  arm64: dts: amlogic: g12: enable UART RX and TX pull up by default
  arm64: dts: amlogic: gxl: enable UART RX and TX pull up by default
  arm64: dts: amlogic: gxbb: enable UART RX and TX pull up by default
  ...

Link: https://lore.kernel.org/r/5f7d3fa4-2d9d-450b-b384-abdd903284dc@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-05-21 19:12:38 +02:00
commit 53c3712fd5
45 changed files with 1097 additions and 119 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
Documentation/devicetree/bindings/arm/amlogic.yaml
View File

@ -74,6 +74,13 @@ properties:
- const: amlogic,s805x
- const: amlogic,meson-gxl
- description: Boards with the Amlogic Meson GXL S805Y SoC
items:
- enum:
- xiaomi,aquaman
- const: amlogic,s805y
- const: amlogic,meson-gxl
- description: Boards with the Amlogic Meson GXL S905W SoC
items:
- enum:
@ -238,6 +245,24 @@ properties:
- amlogic,aq222
- const: amlogic,s4
- description: Boards with the Amlogic S6 S905X5 SoC
items:
- enum:
- amlogic,bl209
- const: amlogic,s6
- description: Boards with the Amlogic S7 S805X3 SoC
items:
- enum:
- amlogic,bp201
- const: amlogic,s7
- description: Boards with the Amlogic S7D S905X5M SoC
items:
- enum:
- amlogic,bm202
- const: amlogic,s7d
- description: Boards with the Amlogic T7 A311D2 SoC
items:
- enum:

4
arch/arm64/boot/dts/amlogic/Makefile
View File

@ -3,6 +3,9 @@ dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-a5-a113x2-av400.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c308l-aw419.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-s6-s905x5-bl209.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-s7-s805x3-bp201.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-s7d-s905x5m-bm202.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb
dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
@ -49,6 +52,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-libretech-ac.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805y-xiaomi-aquaman.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-kii-pro.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb

93
arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h Normal file
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@ -0,0 +1,93 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
*/
#ifndef __DTS_AMLOGIC_A4_RESET_H
#define __DTS_AMLOGIC_A4_RESET_H
/* RESET0 */
/* 0-3 */
#define RESET_USB 4
/* 5-6*/
#define RESET_U2PHY22 7
#define RESET_USBPHY20 8
#define RESET_U2PHY21 9
#define RESET_USB2DRD 10
#define RESET_U2H 11
#define RESET_LED_CTRL 12
/* 13-31 */
/* RESET1 */
#define RESET_AUDIO 32
#define RESET_AUDIO_VAD 33
/* 34*/
#define RESET_DDR_APB 35
#define RESET_DDR 36
#define RESET_VOUT_VENC 37
#define RESET_VOUT 38
/* 39-47 */
#define RESET_ETHERNET 48
/* 49-63 */
/* RESET2 */
#define RESET_DEVICE_MMC_ARB 64
#define RESET_IRCTRL 65
/* 66*/
#define RESET_TS_PLL 67
/* 68-72*/
#define RESET_SPICC_0 73
#define RESET_SPICC_1 74
/* 75-79*/
#define RESET_MSR_CLK 80
/* 81*/
#define RESET_SAR_ADC 82
/* 83-87*/
#define RESET_ACODEC 88
/* 89-90*/
#define RESET_WATCHDOG 91
/* 92-95*/
/* RESET3 */
/* 96-127 */
/* RESET4 */
/* 128-131 */
#define RESET_PWM_AB 132
#define RESET_PWM_CD 133
#define RESET_PWM_EF 134
#define RESET_PWM_GH 135
/* 136-137*/
#define RESET_UART_A 138
#define RESET_UART_B 139
/* 140*/
#define RESET_UART_D 141
#define RESET_UART_E 142
/* 143-144*/
#define RESET_I2C_M_A 145
#define RESET_I2C_M_B 146
#define RESET_I2C_M_C 147
#define RESET_I2C_M_D 148
/* 149-151*/
#define RESET_SDEMMC_A 152
/* 153*/
#define RESET_SDEMMC_C 154
/* 155-159*/
/* RESET5 */
/* 160-175*/
#define RESET_BRG_AO_NIC_SYS 176
/* 177*/
#define RESET_BRG_AO_NIC_MAIN 178
#define RESET_BRG_AO_NIC_AUDIO 179
/* 180-183*/
#define RESET_BRG_AO_NIC_ALL 184
/* 185*/
#define RESET_BRG_NIC_SDIO 186
#define RESET_BRG_NIC_EMMC 187
#define RESET_BRG_NIC_DSU 188
#define RESET_BRG_NIC_CLK81 189
#define RESET_BRG_NIC_MAIN 190
#define RESET_BRG_NIC_ALL 191
#endif

133
arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
View File

@ -4,7 +4,9 @@
*/
#include "amlogic-a4-common.dtsi"
#include "amlogic-a4-reset.h"
#include <dt-bindings/power/amlogic,a4-pwrc.h>
#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
/ {
cpus {
#address-cells = <2>;
@ -50,6 +52,114 @@ pwrc: power-controller {
};
&apb {
reset: reset-controller@2000 {
compatible = "amlogic,a4-reset",
"amlogic,meson-s4-reset";
reg = <0x0 0x2000 0x0 0x98>;
#reset-cells = <1>;
};
periphs_pinctrl: pinctrl@4000 {
compatible = "amlogic,pinctrl-a4";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x4000 0x0 0x280>;
gpiox: gpio@100 {
reg = <0 0x100 0 0x40>, <0 0xc 0 0xc>;
reg-names = "gpio", "mux";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 18>;
};
gpiot: gpio@140 {
reg = <0 0x140 0 0x40>, <0 0x2c 0 0xc>;
reg-names = "gpio", "mux";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_T<<8) 23>;
};
gpiod: gpio@180 {
reg = <0 0x180 0 0x40>, <0 0x40 0 0x8>;
reg-names = "gpio", "mux";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 16>;
};
gpioe: gpio@1c0 {
reg = <0 0x1c0 0 0x40>, <0 0x48 0 0x4>;
reg-names = "gpio", "mux";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>;
};
gpiob: gpio@240 {
reg = <0 0x240 0 0x40>, <0 0 0 0x8>;
reg-names = "gpio", "mux";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>;
};
func-uart-a {
uart_a_default: group-uart-a-pins1 {
pinmux = <AML_PINMUX(AMLOGIC_GPIO_X, 11, 1)>,
<AML_PINMUX(AMLOGIC_GPIO_X, 12, 1)>,
<AML_PINMUX(AMLOGIC_GPIO_X, 13, 1)>,
<AML_PINMUX(AMLOGIC_GPIO_X, 14, 1)>;
};
group-uart-a-pins2 {
pinmux = <AML_PINMUX(AMLOGIC_GPIO_D, 2, 3)>,
<AML_PINMUX(AMLOGIC_GPIO_D, 3, 3)>;
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
func-uart-b {
uart_b_default: group-uart-b-pins {
pinmux = <AML_PINMUX(AMLOGIC_GPIO_E, 0, 3)>,
<AML_PINMUX(AMLOGIC_GPIO_E, 1, 3)>;
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
func-uart-d {
uart_d_default: group-uart-d-pins1 {
pinmux = <AML_PINMUX(AMLOGIC_GPIO_T, 18, 4)>,
<AML_PINMUX(AMLOGIC_GPIO_T, 19, 4)>;
bias-pull-up;
drive-strength-microamp = <4000>;
};
group-uart-d-pins2 {
pinmux = <AML_PINMUX(AMLOGIC_GPIO_T, 7, 2)>,
<AML_PINMUX(AMLOGIC_GPIO_T, 8, 2)>,
<AML_PINMUX(AMLOGIC_GPIO_T, 9, 2)>,
<AML_PINMUX(AMLOGIC_GPIO_T, 10, 2)>;
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
func-uart-e {
uart_e_default: group-uart-e-pins {
pinmux = <AML_PINMUX(AMLOGIC_GPIO_T, 14, 3)>,
<AML_PINMUX(AMLOGIC_GPIO_T, 15, 3)>,
<AML_PINMUX(AMLOGIC_GPIO_T, 16, 3)>,
<AML_PINMUX(AMLOGIC_GPIO_T, 17, 3)>;
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
};
gpio_intc: interrupt-controller@4080 {
compatible = "amlogic,a4-gpio-intc",
"amlogic,meson-gpio-intc";
@ -60,6 +170,29 @@ gpio_intc: interrupt-controller@4080 {
<10 11 12 13 14 15 16 17 18 19 20 21>;
};
ao_pinctrl: pinctrl@8e700 {
compatible = "amlogic,pinctrl-a4";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x8e700 0x0 0x80>;
gpioao: gpio@4 {
reg = <0 0x4 0 0x16>, <0 0 0 0x4>;
reg-names = "gpio", "mux";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_AO<<8) 7>;
};
test_n: gpio@44 {
reg = <0 0x44 0 0x20>;
reg-names = "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>;
};
};
gpio_ao_intc: interrupt-controller@8e72c {
compatible = "amlogic,a4-gpio-ao-intc",
"amlogic,meson-gpio-intc";

95
arch/arm64/boot/dts/amlogic/amlogic-a5-reset.h Normal file
View File

@ -0,0 +1,95 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (c) 2024 Amlogic, Inc. All rights reserved.
*/
#ifndef __DTS_AMLOGIC_A5_RESET_H
#define __DTS_AMLOGIC_A5_RESET_H
/* RESET0 */
/* 0-3 */
#define RESET_USB 4
/* 5-7 */
#define RESET_USBPHY20 8
/* 9 */
#define RESET_USB2DRD 10
/* 11-31 */
/* RESET1 */
#define RESET_AUDIO 32
#define RESET_AUDIO_VAD 33
/* 34 */
#define RESET_DDR_APB 35
#define RESET_DDR 36
/* 37-40 */
#define RESET_DSPA_DEBUG 41
/* 42 */
#define RESET_DSPA 43
/* 44-46 */
#define RESET_NNA 47
#define RESET_ETHERNET 48
/* 49-63 */
/* RESET2 */
#define RESET_ABUS_ARB 64
#define RESET_IRCTRL 65
/* 66 */
#define RESET_TS_PLL 67
/* 68-72 */
#define RESET_SPICC_0 73
#define RESET_SPICC_1 74
#define RESET_RSA 75
/* 76-79 */
#define RESET_MSR_CLK 80
#define RESET_SPIFC 81
#define RESET_SAR_ADC 82
/* 83-90 */
#define RESET_WATCHDOG 91
/* 92-95 */
/* RESET3 */
/* 96-127 */
/* RESET4 */
#define RESET_RTC 128
/* 129-131 */
#define RESET_PWM_AB 132
#define RESET_PWM_CD 133
#define RESET_PWM_EF 134
#define RESET_PWM_GH 135
/* 104-105 */
#define RESET_UART_A 138
#define RESET_UART_B 139
#define RESET_UART_C 140
#define RESET_UART_D 141
#define RESET_UART_E 142
/* 143*/
#define RESET_I2C_S_A 144
#define RESET_I2C_M_A 145
#define RESET_I2C_M_B 146
#define RESET_I2C_M_C 147
#define RESET_I2C_M_D 148
/* 149-151 */
#define RESET_SDEMMC_A 152
/* 153 */
#define RESET_SDEMMC_C 154
/* 155-159*/
/* RESET5 */
/* 160-175 */
#define RESET_BRG_AO_NIC_SYS 176
#define RESET_BRG_AO_NIC_DSPA 177
#define RESET_BRG_AO_NIC_MAIN 178
#define RESET_BRG_AO_NIC_AUDIO 179
/* 180-183 */
#define RESET_BRG_AO_NIC_ALL 184
#define RESET_BRG_NIC_NNA 185
#define RESET_BRG_NIC_SDIO 186
#define RESET_BRG_NIC_EMMC 187
#define RESET_BRG_NIC_DSU 188
#define RESET_BRG_NIC_SYSCLK 189
#define RESET_BRG_NIC_MAIN 190
#define RESET_BRG_NIC_ALL 191
#endif

8
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
View File

@ -4,6 +4,7 @@
*/
#include "amlogic-a4-common.dtsi"
#include "amlogic-a5-reset.h"
#include <dt-bindings/power/amlogic,a5-pwrc.h>
/ {
cpus {
@ -50,6 +51,13 @@ pwrc: power-controller {
};
&apb {
reset: reset-controller@2000 {
compatible = "amlogic,a5-reset",
"amlogic,meson-s4-reset";
reg = <0x0 0x2000 0x0 0x98>;
#reset-cells = <1>;
};
gpio_intc: interrupt-controller@4080 {
compatible = "amlogic,a5-gpio-intc",
"amlogic,meson-gpio-intc";

5
arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
View File

@ -760,6 +760,11 @@ internal_ephy: ethernet_phy@8 {
};
};
clk_msr: clock-measure@48000 {
compatible = "amlogic,c3-clk-measure";
reg = <0x0 0x48000 0x0 0x1c>;
};
spicc0: spi@50000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x50000 0x0 0x44>;

42
arch/arm64/boot/dts/amlogic/amlogic-s6-s905x5-bl209.dts Normal file
View File

@ -0,0 +1,42 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
*/
/dts-v1/;
#include "amlogic-s6.dtsi"
/ {
model = "Amlogic S905X5 BL209 Development Board";
compatible = "amlogic,bl209", "amlogic,s6";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart_b;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x000000 0x0 0xe0000000>,
<0x1 0x000000 0x0 0x20000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 27 MiB reserved for ARM Trusted Firmware */
secmon_reserved: secmon@5000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x05000000 0x0 0x1b00000>;
no-map;
};
};
};
&uart_b {
status = "okay";
};

97
arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi Normal file
View File

@ -0,0 +1,97 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
/ {
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0x0 0x100>;
enable-method = "psci";
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0x0 0x200>;
enable-method = "psci";
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a510";
reg = <0x0 0x300>;
enable-method = "psci";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@ff200000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xff200000 0 0x10000>,
<0x0 0xff240000 0 0x80000>;
interrupts = <GIC_PPI 9 0xf04>;
};
apb: bus@fe000000 {
compatible = "simple-bus";
reg = <0x0 0xfe000000 0x0 0x480000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
uart_b: serial@7a000 {
compatible = "amlogic,s6-uart",
"amlogic,meson-s4-uart";
reg = <0x0 0x7a000 0x0 0x18>;
interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&xtal>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
};
};
};

41
arch/arm64/boot/dts/amlogic/amlogic-s7-s805x3-bp201.dts Normal file
View File

@ -0,0 +1,41 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
*/
/dts-v1/;
#include "amlogic-s7.dtsi"
/ {
model = "Amlogic S805X3 BP201 Development Board";
compatible = "amlogic,bp201", "amlogic,s7";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart_b;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 35 MiB reserved for ARM Trusted Firmware */
secmon_reserved: secmon@5000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x05000000 0x0 0x2300000>;
no-map;
};
};
};
&uart_b {
status = "okay";
};

99
arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi Normal file
View File

@ -0,0 +1,99 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
/ {
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@fff01000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xfff01000 0 0x1000>,
<0x0 0xfff02000 0 0x0100>;
interrupts = <GIC_PPI 9 0xf04>;
};
apb: bus@fe000000 {
compatible = "simple-bus";
reg = <0x0 0xfe000000 0x0 0x480000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
uart_b: serial@7a000 {
compatible = "amlogic,s7-uart",
"amlogic,meson-s4-uart";
reg = <0x0 0x7a000 0x0 0x18>;
interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&xtal>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
};
};
};

41
arch/arm64/boot/dts/amlogic/amlogic-s7d-s905x5m-bm202.dts Normal file
View File

@ -0,0 +1,41 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
*/
/dts-v1/;
#include "amlogic-s7d.dtsi"
/ {
model = "Amlogic S905X5M BM202 Development Board";
compatible = "amlogic,bm202", "amlogic,s7d";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart_b;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 36 MiB reserved for ARM Trusted Firmware */
secmon_reserved: secmon@5000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x05000000 0x0 0x2400000>;
no-map;
};
};
};
&uart_b {
status = "okay";
};

99
arch/arm64/boot/dts/amlogic/amlogic-s7d.dtsi Normal file
View File

@ -0,0 +1,99 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
/ {
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@fff01000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xfff01000 0 0x1000>,
<0x0 0xfff02000 0 0x0100>;
interrupts = <GIC_PPI 9 0xf04>;
};
apb: bus@fe000000 {
compatible = "simple-bus";
reg = <0x0 0xfe000000 0x0 0x480000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
uart_b: serial@7a000 {
compatible = "amlogic,s7d-uart",
"amlogic,meson-s4-uart";
reg = <0x0 0x7a000 0x0 0x18>;
interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&xtal>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
};
};
};

1
arch/arm64/boot/dts/amlogic/meson-a1.dtsi
View File

@ -233,6 +233,7 @@ mux {
groups = "uart_a_tx",
"uart_a_rx";
function = "uart_a";
bias-pull-up;
};
};

12
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
View File

@ -1164,7 +1164,7 @@ mux {
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
bias-disable;
bias-pull-up;
};
};
@ -1182,7 +1182,7 @@ mux {
groups = "uart_tx_b_x",
"uart_rx_b_x";
function = "uart_b";
bias-disable;
bias-pull-up;
};
};
@ -1200,7 +1200,7 @@ mux {
groups = "uart_tx_b_z",
"uart_rx_b_z";
function = "uart_b";
bias-disable;
bias-pull-up;
};
};
@ -1218,7 +1218,7 @@ mux {
groups = "uart_ao_tx_b_z",
"uart_ao_rx_b_z";
function = "uart_ao_b_z";
bias-disable;
bias-pull-up;
};
};
@ -1654,7 +1654,7 @@ mux {
groups = "uart_ao_tx_a",
"uart_ao_rx_a";
function = "uart_ao_a";
bias-disable;
bias-pull-up;
};
};
@ -1672,7 +1672,7 @@ mux {
groups = "uart_ao_tx_b",
"uart_ao_rx_b";
function = "uart_ao_b";
bias-disable;
bias-pull-up;
};
};

10
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
View File

@ -1503,7 +1503,7 @@ mux {
groups = "uart_a_tx",
"uart_a_rx";
function = "uart_a";
bias-disable;
bias-pull-up;
};
};
@ -1521,7 +1521,7 @@ mux {
groups = "uart_b_tx",
"uart_b_rx";
function = "uart_b";
bias-disable;
bias-pull-up;
};
};
@ -1918,7 +1918,7 @@ mux {
groups = "uart_ao_a_tx",
"uart_ao_a_rx";
function = "uart_ao_a";
bias-disable;
bias-pull-up;
};
};
@ -1936,7 +1936,7 @@ mux {
groups = "uart_ao_b_tx_2",
"uart_ao_b_rx_3";
function = "uart_ao_b";
bias-disable;
bias-pull-up;
};
};
@ -1945,7 +1945,7 @@ mux {
groups = "uart_ao_b_tx_8",
"uart_ao_b_rx_9";
function = "uart_ao_b";
bias-disable;
bias-pull-up;
};
};

4
arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts
View File

@ -267,28 +267,24 @@ &cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&ethmac {

4
arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts
View File

@ -220,28 +220,24 @@ &cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cvbs_vdac_port {

4
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
View File

@ -314,28 +314,24 @@ &cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cvbs_vdac_port {

4
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
View File

@ -407,28 +407,24 @@ &cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&clkc_audio {

4
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
View File

@ -263,28 +263,24 @@ &cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cvbs_vdac_port {

1
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
View File

@ -62,6 +62,7 @@ cpu_opp_table: opp-table {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <731000>;
clock-latency-ns = <50000>;
};
opp-1200000000 {

6
arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts
View File

@ -76,42 +76,36 @@ &cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&pwm_ab {

2
arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi
View File

@ -14,6 +14,7 @@ cpu_opp_table_0: opp-table-0 {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <761000>;
clock-latency-ns = <50000>;
};
opp-1200000000 {
@ -54,6 +55,7 @@ cpub_opp_table_1: opp-table-1 {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <731000>;
clock-latency-ns = <50000>;
};
opp-1200000000 {

6
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi
View File

@ -155,42 +155,36 @@ &cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&ext_mdio {

6
arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi
View File

@ -263,42 +263,36 @@ &cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&ethmac {

6
arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
View File

@ -51,42 +51,36 @@ &cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&pwm_ab {

6
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts
View File

@ -281,42 +281,36 @@ &cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
/* RK817 only supports 12.5mV steps, round up the values */

6
arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi
View File

@ -227,42 +227,36 @@ &cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu_thermal {

6
arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts
View File

@ -259,42 +259,36 @@ &cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu_thermal {

2
arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi
View File

@ -14,6 +14,7 @@ cpu_opp_table_0: opp-table-0 {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <731000>;
clock-latency-ns = <50000>;
};
opp-1200000000 {
@ -59,6 +60,7 @@ cpub_opp_table_1: opp-table-1 {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <771000>;
clock-latency-ns = <50000>;
};
opp-1200000000 {

6
arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
View File

@ -213,42 +213,36 @@ &cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table_0>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu100 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu101 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu102 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cpu103 {
cpu-supply = <&vddcpu_a>;
operating-points-v2 = <&cpub_opp_table_1>;
clocks = <&clkc CLKID_CPUB_CLK>;
clock-latency = <50000>;
};
&cvbs_vdac_port {

10
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View File

@ -105,7 +105,7 @@ uart_ao_a_pins: uart_ao_a {
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
function = "uart_ao";
bias-disable;
bias-pull-up;
};
};
@ -122,7 +122,7 @@ uart_ao_b_pins: uart_ao_b {
mux {
groups = "uart_tx_ao_b", "uart_rx_ao_b";
function = "uart_ao_b";
bias-disable;
bias-pull-up;
};
};
@ -520,7 +520,7 @@ mux {
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
bias-disable;
bias-pull-up;
};
};
@ -538,7 +538,7 @@ mux {
groups = "uart_tx_b",
"uart_rx_b";
function = "uart_b";
bias-disable;
bias-pull-up;
};
};
@ -556,7 +556,7 @@ mux {
groups = "uart_tx_c",
"uart_rx_c";
function = "uart_c";
bias-disable;
bias-pull-up;
};
};

262
arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts Normal file
View File

@ -0,0 +1,262 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Ferass El Hafidi <funderscore@postmarketos.org>
* Heavily based on meson-gxl-s805x-p241.dtb:
* - Copyright (c) 2018 BayLibre, SAS.
* Author: Neil Armstrong <narmstrong@baylibre.com>
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/sound/meson-aiu.h>
#include "meson-gxl-s805y.dtsi"
/ {
compatible = "xiaomi,aquaman", "amlogic,s805y", "amlogic,meson-gxl";
model = "Xiaomi Mi TV Stick (aquaman)";
aliases {
serial0 = &uart_AO;
serial1 = &uart_A;
};
chosen {
stdout-path = "serial0:115200n8";
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_tmds_out>;
};
};
};
leds {
compatible = "gpio-leds";
led-white {
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_POWER;
gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
default-state = "on";
panic-indicator;
};
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
vddio_boot: regulator-vddio-boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddao_3v3: regulator-vddao-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vddio_ao18: regulator-vddio-ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: regulator-vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc_5v: regulator-vcc-5v {
compatible = "regulator-fixed";
regulator-name = "VCC_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
clocks = <&wifi32k>;
clock-names = "ext_clock";
};
sound {
compatible = "amlogic,gx-sound-card";
model = "XIAOMI-AQUAMAN";
clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clocks = <&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <294912000>,
<270950400>,
<393216000>;
dai-link-0 {
sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>;
};
dai-link-1 {
sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>;
dai-format = "i2s";
mclk-fs = <256>;
codec-0 {
sound-dai = <&aiu AIU_HDMI CTRL_I2S>;
};
};
dai-link-2 {
sound-dai = <&aiu AIU_HDMI CTRL_OUT>;
codec-0 {
sound-dai = <&hdmi_tx>;
};
};
};
};
&aiu {
status = "okay";
};
&cec_AO {
status = "okay";
pinctrl-0 = <&ao_cec_pins>;
pinctrl-names = "default";
hdmi-phandle = <&hdmi_tx>;
};
&hdmi_tx {
status = "okay";
pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
pinctrl-names = "default";
hdmi-supply = <&vcc_5v>;
};
&hdmi_tx_tmds_port {
hdmi_tx_tmds_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
};
/* Wireless SDIO Module (Amlogic W155S1 / Realtek RTL8821CS) */
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <50000000>;
non-removable;
disable-wp;
/* WiFi firmware requires power to be kept while in suspend */
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
vqmmc-supply = <&vddio_boot>;
sdio: wifi@1 {
reg = <1>;
};
};
/* eMMC */
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&pwm_ef {
status = "okay";
pinctrl-0 = <&pwm_e_pins>;
pinctrl-names = "default";
};
/*
* This is connected to the Bluetooth module
* Note: There's no driver for the Bluetooth module of some variants yet.
*/
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
pinctrl-names = "default";
uart-has-rtscts;
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&usb {
status = "okay";
dr_mode = "otg";
vbus-supply = <&vcc_5v>;
};

10
arch/arm64/boot/dts/amlogic/meson-gxl-s805y.dtsi Normal file
View File

@ -0,0 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2025 Ferass El Hafidi <funderscore@postmarketos.org>
*/
#include "meson-gxl-s805x.dtsi"
/ {
compatible = "amlogic,s805y", "amlogic,meson-gxl";
};

22
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@ -163,7 +163,7 @@ uart_ao_a_pins: uart_ao_a {
mux {
groups = "uart_tx_ao_a", "uart_rx_ao_a";
function = "uart_ao";
bias-disable;
bias-pull-up;
};
};
@ -180,7 +180,7 @@ uart_ao_b_pins: uart_ao_b {
mux {
groups = "uart_tx_ao_b", "uart_rx_ao_b";
function = "uart_ao_b";
bias-disable;
bias-pull-up;
};
};
@ -188,7 +188,7 @@ uart_ao_b_0_1_pins: uart_ao_b_0_1 {
mux {
groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
function = "uart_ao_b";
bias-disable;
bias-pull-up;
};
};
@ -214,7 +214,7 @@ mux {
groups = "i2c_sck_ao",
"i2c_sda_ao";
function = "i2c_ao";
bias-disable;
bias-pull-up;
};
};
@ -522,7 +522,7 @@ mux {
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
bias-disable;
bias-pull-up;
};
};
@ -540,7 +540,7 @@ mux {
groups = "uart_tx_b",
"uart_rx_b";
function = "uart_b";
bias-disable;
bias-pull-up;
};
};
@ -558,7 +558,7 @@ mux {
groups = "uart_tx_c",
"uart_rx_c";
function = "uart_c";
bias-disable;
bias-pull-up;
};
};
@ -576,7 +576,7 @@ mux {
groups = "i2c_sck_a",
"i2c_sda_a";
function = "i2c_a";
bias-disable;
bias-pull-up;
};
};
@ -585,7 +585,7 @@ mux {
groups = "i2c_sck_b",
"i2c_sda_b";
function = "i2c_b";
bias-disable;
bias-pull-up;
};
};
@ -594,7 +594,7 @@ mux {
groups = "i2c_sck_c",
"i2c_sda_c";
function = "i2c_c";
bias-disable;
bias-pull-up;
};
};
@ -603,7 +603,7 @@ mux {
groups = "i2c_sck_c_dv19",
"i2c_sda_c_dv18";
function = "i2c_c";
bias-disable;
bias-pull-up;
};
};

4
arch/arm64/boot/dts/amlogic/meson-gxlx-s905l-p271.dts
View File

@ -38,6 +38,10 @@ mali: gpu@c0000 {
};
};
&saradc {
compatible = "amlogic,meson-gxlx-saradc", "amlogic,meson-saradc";
};
&usb {
dr_mode = "host";
};

5
arch/arm64/boot/dts/amlogic/meson-s4.dtsi
View File

@ -629,6 +629,11 @@ internal_ephy: ethernet-phy@8 {
};
};
clk_msr: clock-measure@48000 {
compatible = "amlogic,s4-clk-measure";
reg = <0x0 0x48000 0x0 0x1c>;
};
spicc0: spi@50000 {
compatible = "amlogic,meson-g12a-spicc";
reg = <0x0 0x50000 0x0 0x44>;

4
arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi
View File

@ -147,28 +147,24 @@ &cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
clock-latency = <50000>;
};
&cvbs_vdac_port {

4
arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
View File

@ -185,28 +185,24 @@ &cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
clock-latency = <50000>;
};
&ext_mdio {

4
arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts
View File

@ -51,28 +51,24 @@ &cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
clock-latency = <50000>;
};
&pwm_AO_cd {

4
arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi
View File

@ -250,28 +250,24 @@ &cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
clock-latency = <50000>;
};
&ext_mdio {

4
arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts
View File

@ -64,26 +64,22 @@ &cpu0 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu_b>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
clock-latency = <50000>;
};

4
arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts
View File

@ -359,28 +359,24 @@ &cpu0 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU_CLK>;
clock-latency = <50000>;
};
&cpu1 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU1_CLK>;
clock-latency = <50000>;
};
&cpu2 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU2_CLK>;
clock-latency = <50000>;
};
&cpu3 {
cpu-supply = <&vddcpu>;
operating-points-v2 = <&cpu_opp_table>;
clocks = <&clkc CLKID_CPU3_CLK>;
clock-latency = <50000>;
};
&ethmac {

1
arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
View File

@ -100,6 +100,7 @@ cpu_opp_table: opp-table {
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <770000>;
clock-latency-ns = <50000>;
};
opp-1200000000 {