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drm/i915/dsi: account for DSC in horizontal timings

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When DSC is enabled, we need to adjust the horizontal timings to account
for the compressed (and therefore reduced) link speed.

The compressed frequency ratio simplifies down to the ratio between
compressed and non-compressed bpp.

Bspec: 49263
Suggested-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/fecebdc2719dd0c78eaf8f4d3225bb185956d7db.1575974743.git.jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2019-12-10 12:50:58 +02:00
parent 38b898810a
commit 53693f02d8
1 changed files with 19 additions and 5 deletions
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24
drivers/gpu/drm/i915/display/icl_dsi.c
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@ -785,12 +785,12 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
static void static void
gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config) const struct intel_crtc_state *crtc_state)
{ {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
const struct drm_display_mode *adjusted_mode = const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode; &crtc_state->hw.adjusted_mode;
enum port port; enum port port;
enum transcoder dsi_trans; enum transcoder dsi_trans;
/* horizontal timings */ /* horizontal timings */
@ -798,11 +798,25 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
u16 hback_porch; u16 hback_porch;
/* vertical timings */ /* vertical timings */
u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
int mul = 1, div = 1;
/*
* Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
* for slower link speed if DSC is enabled.
*
* The compression frequency ratio is the ratio between compressed and
* non-compressed link speeds, and simplifies down to the ratio between
* compressed and non-compressed bpp.
*/
if (crtc_state->dsc.compression_enable) {
mul = crtc_state->dsc.compressed_bpp;
div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
}
hactive = adjusted_mode->crtc_hdisplay; hactive = adjusted_mode->crtc_hdisplay;
htotal = adjusted_mode->crtc_htotal; htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
hsync_start = adjusted_mode->crtc_hsync_start; hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
hsync_end = adjusted_mode->crtc_hsync_end; hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
hsync_size = hsync_end - hsync_start; hsync_size = hsync_end - hsync_start;
hback_porch = (adjusted_mode->crtc_htotal - hback_porch = (adjusted_mode->crtc_htotal -
adjusted_mode->crtc_hsync_end); adjusted_mode->crtc_hsync_end);