From 5344a8bb51e4b0ec2ae7270b941e40983d37d485 Mon Sep 17 00:00:00 2001 From: Uma Shankar Date: Thu, 5 Feb 2026 15:13:35 +0530 Subject: [PATCH] drm/i915: Remove i915_reg.h from intel_rom.c Make intel_rom.c free from including i915_reg.h. v5: Use SPDX (Jani) v4: Move oprom reg to separate header (Ville) v3: Update patch header v2: Use display header instead of gmd common include (Jani) Reviewed-by: Jani Nikula Signed-off-by: Uma Shankar Link: https://patch.msgid.link/20260205094341.1882816-15-uma.shankar@intel.com --- drivers/gpu/drm/i915/display/intel_oprom_regs.h | 15 +++++++++++++++ drivers/gpu/drm/i915/display/intel_rom.c | 3 +-- drivers/gpu/drm/i915/i915_reg.h | 8 -------- 3 files changed, 16 insertions(+), 10 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_oprom_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_oprom_regs.h b/drivers/gpu/drm/i915/display/intel_oprom_regs.h new file mode 100644 index 000000000000..e6a6fb51b90c --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_oprom_regs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2026 Intel Corporation */ + +#ifndef _INTEL_OPROM_REGS_H_ +#define _INTEL_OPROM_REGS_H_ + +#define PRIMARY_SPI_TRIGGER _MMIO(0x102040) +#define PRIMARY_SPI_ADDRESS _MMIO(0x102080) +#define PRIMARY_SPI_REGIONID _MMIO(0x102084) +#define SPI_STATIC_REGIONS _MMIO(0x102090) +#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) +#define OROM_OFFSET _MMIO(0x1020c0) +#define OROM_OFFSET_MASK REG_GENMASK(20, 16) + +#endif diff --git a/drivers/gpu/drm/i915/display/intel_rom.c b/drivers/gpu/drm/i915/display/intel_rom.c index c8f615315310..024db7b1a1c6 100644 --- a/drivers/gpu/drm/i915/display/intel_rom.c +++ b/drivers/gpu/drm/i915/display/intel_rom.c @@ -7,10 +7,9 @@ #include -#include "i915_reg.h" - #include "intel_rom.h" #include "intel_uncore.h" +#include "intel_oprom_regs.h" struct intel_rom { /* for PCI ROM */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2c279bd3342d..9cb753b65bc2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -892,14 +892,6 @@ #define SGGI_DIS REG_BIT(15) #define SGR_DIS REG_BIT(13) -#define PRIMARY_SPI_TRIGGER _MMIO(0x102040) -#define PRIMARY_SPI_ADDRESS _MMIO(0x102080) -#define PRIMARY_SPI_REGIONID _MMIO(0x102084) -#define SPI_STATIC_REGIONS _MMIO(0x102090) -#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0) -#define OROM_OFFSET _MMIO(0x1020c0) -#define OROM_OFFSET_MASK REG_GENMASK(20, 16) - #define MTL_MEDIA_GSI_BASE 0x380000 #endif /* _I915_REG_H_ */