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RDMA/bng_re: Allocate required memory resources for Firmware channel
Allocate required memory resources for Firmware channel. Signed-off-by: Siva Reddy Kallam <siva.kallam@broadcom.com> Link: https://patch.msgid.link/20251117171136.128193-5-siva.kallam@broadcom.com Reviewed-by: Usman Ansari <usman.ansari@broadcom.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
This commit is contained in:
Siva Reddy Kallam
Leon Romanovsky
parent
745065770c
commit
53310b698f
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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ccflags-y := -I $(srctree)/drivers/net/ethernet/broadcom/bnge
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ccflags-y := -I $(srctree)/drivers/net/ethernet/broadcom/bnge -I $(srctree)/drivers/infiniband/hw/bnxt_re
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obj-$(CONFIG_INFINIBAND_BNG_RE) += bng_re.o
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bng_re-y := bng_dev.o
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bng_re-y := bng_dev.o bng_fw.o \
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bng_res.o
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@ -8,6 +8,7 @@
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#include <rdma/ib_verbs.h>
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#include "bng_res.h"
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#include "bng_fw.h"
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#include "bng_re.h"
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#include "bnge.h"
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#include "bnge_hwrm.h"
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@ -56,6 +57,9 @@ static void bng_re_destroy_chip_ctx(struct bng_re_dev *rdev)
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chip_ctx = rdev->chip_ctx;
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rdev->chip_ctx = NULL;
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rdev->rcfw.res = NULL;
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rdev->bng_res.cctx = NULL;
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rdev->bng_res.pdev = NULL;
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kfree(chip_ctx);
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}
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@ -65,7 +69,8 @@ static int bng_re_setup_chip_ctx(struct bng_re_dev *rdev)
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struct bnge_auxr_dev *aux_dev;
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aux_dev = rdev->aux_dev;
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rdev->bng_res.pdev = aux_dev->pdev;
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rdev->rcfw.res = &rdev->bng_res;
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chip_ctx = kzalloc(sizeof(*chip_ctx), GFP_KERNEL);
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if (!chip_ctx)
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return -ENOMEM;
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@ -73,6 +78,7 @@ static int bng_re_setup_chip_ctx(struct bng_re_dev *rdev)
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chip_ctx->hw_stats_size = aux_dev->hw_ring_stats_size;
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rdev->chip_ctx = chip_ctx;
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rdev->bng_res.cctx = rdev->chip_ctx;
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return 0;
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}
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@ -131,6 +137,14 @@ static void bng_re_query_hwrm_version(struct bng_re_dev *rdev)
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cctx->hwrm_cmd_max_timeout = BNG_ROCE_FW_MAX_TIMEOUT;
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}
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static void bng_re_dev_uninit(struct bng_re_dev *rdev)
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{
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bng_re_free_rcfw_channel(&rdev->rcfw);
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bng_re_destroy_chip_ctx(rdev);
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if (test_and_clear_bit(BNG_RE_FLAG_NETDEV_REGISTERED, &rdev->flags))
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bnge_unregister_dev(rdev->aux_dev);
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}
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static int bng_re_dev_init(struct bng_re_dev *rdev)
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{
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int rc;
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@ -166,14 +180,18 @@ static int bng_re_dev_init(struct bng_re_dev *rdev)
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bng_re_query_hwrm_version(rdev);
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return 0;
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}
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rc = bng_re_alloc_fw_channel(&rdev->bng_res, &rdev->rcfw);
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if (rc) {
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ibdev_err(&rdev->ibdev,
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"Failed to allocate RCFW Channel: %#x\n", rc);
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goto fail;
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}
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static void bng_re_dev_uninit(struct bng_re_dev *rdev)
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{
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bng_re_destroy_chip_ctx(rdev);
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if (test_and_clear_bit(BNG_RE_FLAG_NETDEV_REGISTERED, &rdev->flags))
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bnge_unregister_dev(rdev->aux_dev);
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return 0;
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fail:
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bng_re_dev_uninit(rdev);
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return rc;
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}
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static int bng_re_add_device(struct auxiliary_device *adev)
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70
drivers/infiniband/hw/bng_re/bng_fw.c
Normal file
70
drivers/infiniband/hw/bng_re/bng_fw.c
Normal file
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@ -0,0 +1,70 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2025 Broadcom.
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#include <linux/pci.h>
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#include "bng_res.h"
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#include "bng_fw.h"
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void bng_re_free_rcfw_channel(struct bng_re_rcfw *rcfw)
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{
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kfree(rcfw->crsqe_tbl);
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bng_re_free_hwq(rcfw->res, &rcfw->cmdq.hwq);
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bng_re_free_hwq(rcfw->res, &rcfw->creq.hwq);
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rcfw->pdev = NULL;
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}
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int bng_re_alloc_fw_channel(struct bng_re_res *res,
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struct bng_re_rcfw *rcfw)
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{
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struct bng_re_hwq_attr hwq_attr = {};
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struct bng_re_sg_info sginfo = {};
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struct bng_re_cmdq_ctx *cmdq;
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struct bng_re_creq_ctx *creq;
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rcfw->pdev = res->pdev;
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cmdq = &rcfw->cmdq;
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creq = &rcfw->creq;
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rcfw->res = res;
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sginfo.pgsize = PAGE_SIZE;
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sginfo.pgshft = PAGE_SHIFT;
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hwq_attr.sginfo = &sginfo;
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hwq_attr.res = rcfw->res;
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hwq_attr.depth = BNG_FW_CREQE_MAX_CNT;
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hwq_attr.stride = BNG_FW_CREQE_UNITS;
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hwq_attr.type = BNG_HWQ_TYPE_QUEUE;
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if (bng_re_alloc_init_hwq(&creq->hwq, &hwq_attr)) {
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dev_err(&rcfw->pdev->dev,
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"HW channel CREQ allocation failed\n");
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goto fail;
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}
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rcfw->cmdq_depth = BNG_FW_CMDQE_MAX_CNT;
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sginfo.pgsize = bng_fw_cmdqe_page_size(rcfw->cmdq_depth);
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hwq_attr.depth = rcfw->cmdq_depth & 0x7FFFFFFF;
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hwq_attr.stride = BNG_FW_CMDQE_UNITS;
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hwq_attr.type = BNG_HWQ_TYPE_CTX;
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if (bng_re_alloc_init_hwq(&cmdq->hwq, &hwq_attr)) {
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dev_err(&rcfw->pdev->dev,
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"HW channel CMDQ allocation failed\n");
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goto fail;
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}
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rcfw->crsqe_tbl = kcalloc(cmdq->hwq.max_elements,
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sizeof(*rcfw->crsqe_tbl), GFP_KERNEL);
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if (!rcfw->crsqe_tbl)
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goto fail;
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spin_lock_init(&rcfw->tbl_lock);
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rcfw->max_timeout = res->cctx->hwrm_cmd_max_timeout;
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return 0;
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fail:
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bng_re_free_rcfw_channel(rcfw);
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return -ENOMEM;
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}
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69
drivers/infiniband/hw/bng_re/bng_fw.h
Normal file
69
drivers/infiniband/hw/bng_re/bng_fw.h
Normal file
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@ -0,0 +1,69 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (c) 2025 Broadcom.
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#ifndef __BNG_FW_H__
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#define __BNG_FW_H__
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/* CREQ */
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#define BNG_FW_CREQE_MAX_CNT (64 * 1024)
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#define BNG_FW_CREQE_UNITS 16
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/* CMDQ */
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struct bng_fw_cmdqe {
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u8 data[16];
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};
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#define BNG_FW_CMDQE_MAX_CNT 8192
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#define BNG_FW_CMDQE_UNITS sizeof(struct bng_fw_cmdqe)
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#define BNG_FW_CMDQE_BYTES(depth) ((depth) * BNG_FW_CMDQE_UNITS)
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static inline u32 bng_fw_cmdqe_npages(u32 depth)
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{
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u32 npages;
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npages = BNG_FW_CMDQE_BYTES(depth) / PAGE_SIZE;
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if (BNG_FW_CMDQE_BYTES(depth) % PAGE_SIZE)
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npages++;
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return npages;
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}
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static inline u32 bng_fw_cmdqe_page_size(u32 depth)
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{
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return (bng_fw_cmdqe_npages(depth) * PAGE_SIZE);
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}
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/* HWQ */
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struct bng_re_cmdq_ctx {
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struct bng_re_hwq hwq;
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};
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struct bng_re_creq_ctx {
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struct bng_re_hwq hwq;
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};
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struct bng_re_crsqe {
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struct creq_qp_event *resp;
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u32 req_size;
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/* Free slots at the time of submission */
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u32 free_slots;
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u8 opcode;
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};
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/* RoCE FW Communication Channels */
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struct bng_re_rcfw {
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struct pci_dev *pdev;
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struct bng_re_res *res;
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struct bng_re_cmdq_ctx cmdq;
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struct bng_re_creq_ctx creq;
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struct bng_re_crsqe *crsqe_tbl;
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/* To synchronize the qp-handle hash table */
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spinlock_t tbl_lock;
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u32 cmdq_depth;
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/* cached from chip cctx for quick reference in slow path */
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u16 max_timeout;
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};
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void bng_re_free_rcfw_channel(struct bng_re_rcfw *rcfw);
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int bng_re_alloc_fw_channel(struct bng_re_res *res,
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struct bng_re_rcfw *rcfw);
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#endif
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@ -26,6 +26,8 @@ struct bng_re_dev {
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struct bnge_auxr_dev *aux_dev;
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struct bng_re_chip_ctx *chip_ctx;
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int fn_id;
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struct bng_re_res bng_res;
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struct bng_re_rcfw rcfw;
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};
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#endif
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250
drivers/infiniband/hw/bng_re/bng_res.c
Normal file
250
drivers/infiniband/hw/bng_re/bng_res.c
Normal file
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@ -0,0 +1,250 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2025 Broadcom.
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#include <linux/pci.h>
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#include <linux/vmalloc.h>
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#include <rdma/ib_umem.h>
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#include "bng_res.h"
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#include "roce_hsi.h"
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static void bng_free_pbl(struct bng_re_res *res, struct bng_re_pbl *pbl)
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{
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struct pci_dev *pdev = res->pdev;
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int i;
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for (i = 0; i < pbl->pg_count; i++) {
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if (pbl->pg_arr[i])
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dma_free_coherent(&pdev->dev, pbl->pg_size,
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(void *)((unsigned long)
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pbl->pg_arr[i] &
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PAGE_MASK),
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pbl->pg_map_arr[i]);
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else
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dev_warn(&pdev->dev,
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"PBL free pg_arr[%d] empty?!\n", i);
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pbl->pg_arr[i] = NULL;
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}
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vfree(pbl->pg_arr);
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pbl->pg_arr = NULL;
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vfree(pbl->pg_map_arr);
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pbl->pg_map_arr = NULL;
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pbl->pg_count = 0;
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pbl->pg_size = 0;
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}
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static int bng_alloc_pbl(struct bng_re_res *res,
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struct bng_re_pbl *pbl,
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struct bng_re_sg_info *sginfo)
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{
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struct pci_dev *pdev = res->pdev;
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u32 pages;
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int i;
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if (sginfo->nopte)
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return 0;
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pages = sginfo->npages;
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/* page ptr arrays */
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pbl->pg_arr = vmalloc_array(pages, sizeof(void *));
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if (!pbl->pg_arr)
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return -ENOMEM;
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pbl->pg_map_arr = vmalloc_array(pages, sizeof(dma_addr_t));
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if (!pbl->pg_map_arr) {
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vfree(pbl->pg_arr);
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pbl->pg_arr = NULL;
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return -ENOMEM;
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}
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pbl->pg_count = 0;
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pbl->pg_size = sginfo->pgsize;
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for (i = 0; i < pages; i++) {
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pbl->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
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pbl->pg_size,
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&pbl->pg_map_arr[i],
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GFP_KERNEL);
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if (!pbl->pg_arr[i])
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goto fail;
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pbl->pg_count++;
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}
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return 0;
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fail:
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bng_free_pbl(res, pbl);
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return -ENOMEM;
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}
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void bng_re_free_hwq(struct bng_re_res *res,
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struct bng_re_hwq *hwq)
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{
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int i;
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if (!hwq->max_elements)
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return;
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if (hwq->level >= BNG_PBL_LVL_MAX)
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return;
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for (i = 0; i < hwq->level + 1; i++)
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bng_free_pbl(res, &hwq->pbl[i]);
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hwq->level = BNG_PBL_LVL_MAX;
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hwq->max_elements = 0;
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hwq->element_size = 0;
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hwq->prod = 0;
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hwq->cons = 0;
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}
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/* All HWQs are power of 2 in size */
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int bng_re_alloc_init_hwq(struct bng_re_hwq *hwq,
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struct bng_re_hwq_attr *hwq_attr)
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{
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u32 npages, pg_size;
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struct bng_re_sg_info sginfo = {};
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u32 depth, stride, npbl, npde;
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dma_addr_t *src_phys_ptr, **dst_virt_ptr;
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struct bng_re_res *res;
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struct pci_dev *pdev;
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int i, rc, lvl;
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|
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res = hwq_attr->res;
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pdev = res->pdev;
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pg_size = hwq_attr->sginfo->pgsize;
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hwq->level = BNG_PBL_LVL_MAX;
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depth = roundup_pow_of_two(hwq_attr->depth);
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stride = roundup_pow_of_two(hwq_attr->stride);
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|
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npages = (depth * stride) / pg_size;
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if ((depth * stride) % pg_size)
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npages++;
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if (!npages)
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return -EINVAL;
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hwq_attr->sginfo->npages = npages;
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|
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if (npages == MAX_PBL_LVL_0_PGS && !hwq_attr->sginfo->nopte) {
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/* This request is Level 0, map PTE */
|
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rc = bng_alloc_pbl(res, &hwq->pbl[BNG_PBL_LVL_0], hwq_attr->sginfo);
|
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if (rc)
|
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goto fail;
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hwq->level = BNG_PBL_LVL_0;
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goto done;
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}
|
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|
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if (npages >= MAX_PBL_LVL_0_PGS) {
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if (npages > MAX_PBL_LVL_1_PGS) {
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u32 flag = PTU_PTE_VALID;
|
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/* 2 levels of indirection */
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npbl = npages >> MAX_PBL_LVL_1_PGS_SHIFT;
|
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if (npages % BIT(MAX_PBL_LVL_1_PGS_SHIFT))
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npbl++;
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npde = npbl >> MAX_PDL_LVL_SHIFT;
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if (npbl % BIT(MAX_PDL_LVL_SHIFT))
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npde++;
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/* Alloc PDE pages */
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sginfo.pgsize = npde * pg_size;
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sginfo.npages = 1;
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rc = bng_alloc_pbl(res, &hwq->pbl[BNG_PBL_LVL_0], &sginfo);
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if (rc)
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goto fail;
|
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/* Alloc PBL pages */
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sginfo.npages = npbl;
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sginfo.pgsize = PAGE_SIZE;
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rc = bng_alloc_pbl(res, &hwq->pbl[BNG_PBL_LVL_1], &sginfo);
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if (rc)
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goto fail;
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/* Fill PDL with PBL page pointers */
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dst_virt_ptr =
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(dma_addr_t **)hwq->pbl[BNG_PBL_LVL_0].pg_arr;
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src_phys_ptr = hwq->pbl[BNG_PBL_LVL_1].pg_map_arr;
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for (i = 0; i < hwq->pbl[BNG_PBL_LVL_1].pg_count; i++)
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dst_virt_ptr[0][i] = src_phys_ptr[i] | flag;
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|
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/* Alloc or init PTEs */
|
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rc = bng_alloc_pbl(res, &hwq->pbl[BNG_PBL_LVL_2],
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hwq_attr->sginfo);
|
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if (rc)
|
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goto fail;
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hwq->level = BNG_PBL_LVL_2;
|
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if (hwq_attr->sginfo->nopte)
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goto done;
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/* Fill PBLs with PTE pointers */
|
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dst_virt_ptr =
|
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(dma_addr_t **)hwq->pbl[BNG_PBL_LVL_1].pg_arr;
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src_phys_ptr = hwq->pbl[BNG_PBL_LVL_2].pg_map_arr;
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for (i = 0; i < hwq->pbl[BNG_PBL_LVL_2].pg_count; i++) {
|
||||
dst_virt_ptr[PTR_PG(i)][PTR_IDX(i)] =
|
||||
src_phys_ptr[i] | PTU_PTE_VALID;
|
||||
}
|
||||
if (hwq_attr->type == BNG_HWQ_TYPE_QUEUE) {
|
||||
/* Find the last pg of the size */
|
||||
i = hwq->pbl[BNG_PBL_LVL_2].pg_count;
|
||||
dst_virt_ptr[PTR_PG(i - 1)][PTR_IDX(i - 1)] |=
|
||||
PTU_PTE_LAST;
|
||||
if (i > 1)
|
||||
dst_virt_ptr[PTR_PG(i - 2)]
|
||||
[PTR_IDX(i - 2)] |=
|
||||
PTU_PTE_NEXT_TO_LAST;
|
||||
}
|
||||
} else { /* pages < 512 npbl = 1, npde = 0 */
|
||||
u32 flag = PTU_PTE_VALID;
|
||||
|
||||
/* 1 level of indirection */
|
||||
npbl = npages >> MAX_PBL_LVL_1_PGS_SHIFT;
|
||||
if (npages % BIT(MAX_PBL_LVL_1_PGS_SHIFT))
|
||||
npbl++;
|
||||
sginfo.npages = npbl;
|
||||
sginfo.pgsize = PAGE_SIZE;
|
||||
/* Alloc PBL page */
|
||||
rc = bng_alloc_pbl(res, &hwq->pbl[BNG_PBL_LVL_0], &sginfo);
|
||||
if (rc)
|
||||
goto fail;
|
||||
/* Alloc or init PTEs */
|
||||
rc = bng_alloc_pbl(res, &hwq->pbl[BNG_PBL_LVL_1],
|
||||
hwq_attr->sginfo);
|
||||
if (rc)
|
||||
goto fail;
|
||||
hwq->level = BNG_PBL_LVL_1;
|
||||
if (hwq_attr->sginfo->nopte)
|
||||
goto done;
|
||||
/* Fill PBL with PTE pointers */
|
||||
dst_virt_ptr =
|
||||
(dma_addr_t **)hwq->pbl[BNG_PBL_LVL_0].pg_arr;
|
||||
src_phys_ptr = hwq->pbl[BNG_PBL_LVL_1].pg_map_arr;
|
||||
for (i = 0; i < hwq->pbl[BNG_PBL_LVL_1].pg_count; i++)
|
||||
dst_virt_ptr[PTR_PG(i)][PTR_IDX(i)] =
|
||||
src_phys_ptr[i] | flag;
|
||||
if (hwq_attr->type == BNG_HWQ_TYPE_QUEUE) {
|
||||
/* Find the last pg of the size */
|
||||
i = hwq->pbl[BNG_PBL_LVL_1].pg_count;
|
||||
dst_virt_ptr[PTR_PG(i - 1)][PTR_IDX(i - 1)] |=
|
||||
PTU_PTE_LAST;
|
||||
if (i > 1)
|
||||
dst_virt_ptr[PTR_PG(i - 2)]
|
||||
[PTR_IDX(i - 2)] |=
|
||||
PTU_PTE_NEXT_TO_LAST;
|
||||
}
|
||||
}
|
||||
}
|
||||
done:
|
||||
hwq->prod = 0;
|
||||
hwq->cons = 0;
|
||||
hwq->pdev = pdev;
|
||||
hwq->depth = hwq_attr->depth;
|
||||
hwq->max_elements = hwq->depth;
|
||||
hwq->element_size = stride;
|
||||
/* For direct access to the elements */
|
||||
lvl = hwq->level;
|
||||
if (hwq_attr->sginfo->nopte && hwq->level)
|
||||
lvl = hwq->level - 1;
|
||||
hwq->pbl_ptr = hwq->pbl[lvl].pg_arr;
|
||||
hwq->pbl_dma_ptr = hwq->pbl[lvl].pg_map_arr;
|
||||
spin_lock_init(&hwq->lock);
|
||||
|
||||
return 0;
|
||||
fail:
|
||||
bng_re_free_hwq(res, hwq);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
|
@ -6,6 +6,18 @@
|
|||
|
||||
#define BNG_ROCE_FW_MAX_TIMEOUT 60
|
||||
|
||||
#define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *))
|
||||
#define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1)
|
||||
#define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
|
||||
#define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG)
|
||||
|
||||
#define MAX_PBL_LVL_0_PGS 1
|
||||
#define MAX_PBL_LVL_1_PGS 512
|
||||
#define MAX_PBL_LVL_1_PGS_SHIFT 9
|
||||
#define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256
|
||||
#define MAX_PBL_LVL_2_PGS (256 * 512)
|
||||
#define MAX_PDL_LVL_SHIFT 9
|
||||
|
||||
struct bng_re_chip_ctx {
|
||||
u16 chip_num;
|
||||
u16 hw_stats_size;
|
||||
|
|
@ -13,4 +25,68 @@ struct bng_re_chip_ctx {
|
|||
u16 hwrm_cmd_max_timeout;
|
||||
};
|
||||
|
||||
struct bng_re_pbl {
|
||||
u32 pg_count;
|
||||
u32 pg_size;
|
||||
void **pg_arr;
|
||||
dma_addr_t *pg_map_arr;
|
||||
};
|
||||
|
||||
enum bng_re_pbl_lvl {
|
||||
BNG_PBL_LVL_0,
|
||||
BNG_PBL_LVL_1,
|
||||
BNG_PBL_LVL_2,
|
||||
BNG_PBL_LVL_MAX
|
||||
};
|
||||
|
||||
enum bng_re_hwq_type {
|
||||
BNG_HWQ_TYPE_CTX,
|
||||
BNG_HWQ_TYPE_QUEUE
|
||||
};
|
||||
|
||||
struct bng_re_sg_info {
|
||||
u32 npages;
|
||||
u32 pgshft;
|
||||
u32 pgsize;
|
||||
bool nopte;
|
||||
};
|
||||
|
||||
struct bng_re_hwq_attr {
|
||||
struct bng_re_res *res;
|
||||
struct bng_re_sg_info *sginfo;
|
||||
enum bng_re_hwq_type type;
|
||||
u32 depth;
|
||||
u32 stride;
|
||||
u32 aux_stride;
|
||||
u32 aux_depth;
|
||||
};
|
||||
|
||||
struct bng_re_hwq {
|
||||
struct pci_dev *pdev;
|
||||
/* lock to protect hwq */
|
||||
spinlock_t lock;
|
||||
struct bng_re_pbl pbl[BNG_PBL_LVL_MAX + 1];
|
||||
/* Valid values: 0, 1, 2 */
|
||||
enum bng_re_pbl_lvl level;
|
||||
/* PBL entries */
|
||||
void **pbl_ptr;
|
||||
/* PBL dma_addr */
|
||||
dma_addr_t *pbl_dma_ptr;
|
||||
u32 max_elements;
|
||||
u32 depth;
|
||||
u16 element_size;
|
||||
u32 prod;
|
||||
u32 cons;
|
||||
};
|
||||
|
||||
struct bng_re_res {
|
||||
struct pci_dev *pdev;
|
||||
struct bng_re_chip_ctx *cctx;
|
||||
};
|
||||
|
||||
void bng_re_free_hwq(struct bng_re_res *res,
|
||||
struct bng_re_hwq *hwq);
|
||||
|
||||
int bng_re_alloc_init_hwq(struct bng_re_hwq *hwq,
|
||||
struct bng_re_hwq_attr *hwq_attr);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user