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drm/amdkfd: Do not include VGPR MSBs in saved PC during save
The current trap handler uses the top bits of ttmp1 to store a copy of sq_wave_mode.*vgpr_msb (except for src2_vgpr_msb). This is so the effective values in sq_wave_mode can be cleared to ensure correct behavior of the trap handler. When saving sq_wave_mode, the trap handler correctly rebuilds the expected value (with *vgpr_msb restored), so the save area is correct. However, the PC itself is copied from ttmp[0:1], which contains the wave's PC as well as the saved MSBs. The debugger reads the PC from the save area and is confused when non-0 values from VGPR_MSBs are present. This patch fixes this by saving the PC in the save area's PC slot, not the composite of the PC and VGPR_MSBs. On restore, the VGPR_MSBs are restored from sq_wave_mode. Signed-off-by: Lancelot Six <lancelot.six@amd.com> Tested-by: Alexey Kondratiev <Alexey.Kondratiev@amd.com> Reviewed-by: Jay Cornwall <jay.cornwall@amd.com> Cc: Vladimir Indic <vladimir.indic@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3760,8 +3760,8 @@ static const uint32_t cwsr_trap_gfx12_hex[] = {
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0xb8faf804, 0x8b7a847a,
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0x91788478, 0x8c787a78,
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0xd7610002, 0x0000fa6c,
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0x807d817d, 0x917aff6d,
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0x80000000, 0xd7610002,
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0x807d817d, 0x8b7aff6d,
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0x0000ffff, 0xd7610002,
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0x0000fa7a, 0x807d817d,
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0xd7610002, 0x0000fa6e,
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0x807d817d, 0xd7610002,
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@ -4848,7 +4848,7 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = {
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0x9178ff78, 0x0001000c,
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0x8c787a78, 0xd7610002,
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0x0000fa6c, 0x807d817d,
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0x917aff6d, 0x80000000,
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0x8b7aff6d, 0x01ffffff,
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0xd7610002, 0x0000fa7a,
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0x807d817d, 0xd7610002,
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0x0000fa6e, 0x807d817d,
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@ -547,7 +547,7 @@ L_SAVE_HWREG:
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s_or_b32 s_save_state_priv, s_save_state_priv, s_save_tmp
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write_hwreg_to_v2(s_save_pc_lo)
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s_andn2_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK
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s_and_b32 s_save_tmp, s_save_pc_hi, ADDRESS_HI32_MASK
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write_hwreg_to_v2(s_save_tmp)
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write_hwreg_to_v2(s_save_exec_lo)
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#if WAVE32_ONLY
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