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Update devfreq next for v6.18

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Detailed description for this pull request:
 - Add support for LPDDR5 for Rockhip RK3588 SoC on rockchip-dfi devfreq driver.
 
 - Fix an issue where DDR cycle counts on RK3588/RK3528 with LPDDR4(X)
   are reported as half by adding a cycle multiplier to the DFI driver
   on rockchip-dfi devfreq-event driver.
 
 - Fix missing error pointer dereference of regulator instance
   and remove redundant condition on on mtk-cci-devfreq.c devfreq driver.
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Merge tag 'devfreq-next-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux

Merge devfreq updates for v6.18 from Chanwoo Choi:

"- Add support for LPDDR5 for Rockhip RK3588 SoC on rockchip-dfi devfreq
   driver.

 - Fix an issue where DDR cycle counts on RK3588/RK3528 with LPDDR4(X)
   are reported as half by adding a cycle multiplier to the DFI driver
   on rockchip-dfi devfreq-event driver.

 - Fix missing error pointer dereference of regulator instance
   and remove redundant condition on on mtk-cci-devfreq.c devfreq
   driver."

* tag 'devfreq-next-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux:
  PM / devfreq: rockchip-dfi: add support for LPDDR5
  PM / devfreq: rockchip-dfi: double count on RK3588
  PM / devfreq: mtk-cci: avoid redundant conditions
  PM / devfreq: mtk-cci: Fix potential error pointer dereference in probe()
This commit is contained in:
Rafael J. Wysocki 2025-09-11 18:08:45 +02:00
commit 531453a36c
4 changed files with 82 additions and 23 deletions
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91
drivers/devfreq/event/rockchip-dfi.c
View File

@ -34,15 +34,18 @@
/* DDRMON_CTRL */
#define DDRMON_CTRL 0x04
#define DDRMON_CTRL_LPDDR5 BIT(6)
#define DDRMON_CTRL_DDR4 BIT(5)
#define DDRMON_CTRL_LPDDR4 BIT(4)
#define DDRMON_CTRL_HARDWARE_EN BIT(3)
#define DDRMON_CTRL_LPDDR23 BIT(2)
#define DDRMON_CTRL_SOFTWARE_EN BIT(1)
#define DDRMON_CTRL_TIMER_CNT_EN BIT(0)
#define DDRMON_CTRL_DDR_TYPE_MASK (DDRMON_CTRL_DDR4 | \
#define DDRMON_CTRL_DDR_TYPE_MASK (DDRMON_CTRL_LPDDR5 | \
DDRMON_CTRL_DDR4 | \
DDRMON_CTRL_LPDDR4 | \
DDRMON_CTRL_LPDDR23)
#define DDRMON_CTRL_LP5_BANK_MODE_MASK GENMASK(8, 7)
#define DDRMON_CH0_WR_NUM 0x20
#define DDRMON_CH0_RD_NUM 0x24
@ -116,12 +119,60 @@ struct rockchip_dfi {
int buswidth[DMC_MAX_CHANNELS];
int ddrmon_stride;
bool ddrmon_ctrl_single;
u32 lp5_bank_mode;
bool lp5_ckr; /* true if in 4:1 command-to-data clock ratio mode */
unsigned int count_multiplier; /* number of data clocks per count */
};
static int rockchip_dfi_ddrtype_to_ctrl(struct rockchip_dfi *dfi, u32 *ctrl,
u32 *mask)
{
u32 ddrmon_ver;
*mask = DDRMON_CTRL_DDR_TYPE_MASK;
switch (dfi->ddr_type) {
case ROCKCHIP_DDRTYPE_LPDDR2:
case ROCKCHIP_DDRTYPE_LPDDR3:
*ctrl = DDRMON_CTRL_LPDDR23;
break;
case ROCKCHIP_DDRTYPE_LPDDR4:
case ROCKCHIP_DDRTYPE_LPDDR4X:
*ctrl = DDRMON_CTRL_LPDDR4;
break;
case ROCKCHIP_DDRTYPE_LPDDR5:
ddrmon_ver = readl_relaxed(dfi->regs);
if (ddrmon_ver < 0x40) {
*ctrl = DDRMON_CTRL_LPDDR5 | dfi->lp5_bank_mode;
*mask |= DDRMON_CTRL_LP5_BANK_MODE_MASK;
break;
}
/*
* As it is unknown whether the unpleasant special case
* behaviour used by the vendor kernel is needed for any
* shipping hardware, ask users to report if they have
* some of that hardware.
*/
dev_err(&dfi->edev->dev,
"unsupported DDRMON version 0x%04X, please let linux-rockchip know!\n",
ddrmon_ver);
return -EOPNOTSUPP;
default:
dev_err(&dfi->edev->dev, "unsupported memory type 0x%X\n",
dfi->ddr_type);
return -EOPNOTSUPP;
}
return 0;
}
static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
{
void __iomem *dfi_regs = dfi->regs;
int i, ret = 0;
u32 ctrl;
u32 ctrl_mask;
mutex_lock(&dfi->mutex);
@ -135,8 +186,11 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
goto out;
}
ret = rockchip_dfi_ddrtype_to_ctrl(dfi, &ctrl, &ctrl_mask);
if (ret)
goto out;
for (i = 0; i < dfi->max_channels; i++) {
u32 ctrl = 0;
if (!(dfi->channel_mask & BIT(i)))
continue;
@ -146,21 +200,7 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
DDRMON_CTRL_SOFTWARE_EN | DDRMON_CTRL_HARDWARE_EN),
dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
/* set ddr type to dfi */
switch (dfi->ddr_type) {
case ROCKCHIP_DDRTYPE_LPDDR2:
case ROCKCHIP_DDRTYPE_LPDDR3:
ctrl = DDRMON_CTRL_LPDDR23;
break;
case ROCKCHIP_DDRTYPE_LPDDR4:
case ROCKCHIP_DDRTYPE_LPDDR4X:
ctrl = DDRMON_CTRL_LPDDR4;
break;
default:
break;
}
writel_relaxed(HIWORD_UPDATE(ctrl, DDRMON_CTRL_DDR_TYPE_MASK),
writel_relaxed(HIWORD_UPDATE(ctrl, ctrl_mask),
dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
/* enable count, use software mode */
@ -435,7 +475,7 @@ static u64 rockchip_ddr_perf_event_get_count(struct perf_event *event)
switch (event->attr.config) {
case PERF_EVENT_CYCLES:
count = total.c[0].clock_cycles;
count = total.c[0].clock_cycles * dfi->count_multiplier;
break;
case PERF_EVENT_READ_BYTES:
for (i = 0; i < dfi->max_channels; i++)
@ -651,10 +691,14 @@ static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi)
break;
case ROCKCHIP_DDRTYPE_LPDDR4:
case ROCKCHIP_DDRTYPE_LPDDR4X:
case ROCKCHIP_DDRTYPE_LPDDR5:
dfi->burst_len = 16;
break;
}
if (!dfi->count_multiplier)
dfi->count_multiplier = 1;
ret = perf_pmu_register(pmu, "rockchip_ddr", -1);
if (ret)
return ret;
@ -726,7 +770,7 @@ static int rk3568_dfi_init(struct rockchip_dfi *dfi)
static int rk3588_dfi_init(struct rockchip_dfi *dfi)
{
struct regmap *regmap_pmu = dfi->regmap_pmu;
u32 reg2, reg3, reg4;
u32 reg2, reg3, reg4, reg6;
regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, &reg2);
regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG3, &reg3);
@ -751,6 +795,15 @@ static int rk3588_dfi_init(struct rockchip_dfi *dfi)
dfi->max_channels = 4;
dfi->ddrmon_stride = 0x4000;
dfi->count_multiplier = 2;
if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR5) {
regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG6, &reg6);
dfi->lp5_bank_mode = FIELD_GET(RK3588_PMUGRF_OS_REG6_LP5_BANK_MODE, reg6) << 7;
dfi->lp5_ckr = FIELD_GET(RK3588_PMUGRF_OS_REG6_LP5_CKR, reg6);
if (dfi->lp5_ckr)
dfi->count_multiplier *= 2;
}
return 0;
};

5
drivers/devfreq/mtk-cci-devfreq.c
View File

@ -86,7 +86,7 @@ static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv, int new_voltage)
soc_data->sram_max_volt);
return ret;
}
} else if (pre_voltage > new_voltage) {
} else {
voltage = max(new_voltage,
pre_vsram - soc_data->max_volt_shift);
ret = regulator_set_voltage(drv->proc_reg, voltage,
@ -386,7 +386,8 @@ static int mtk_ccifreq_probe(struct platform_device *pdev)
out_free_resources:
if (regulator_is_enabled(drv->proc_reg))
regulator_disable(drv->proc_reg);
if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
if (!IS_ERR_OR_NULL(drv->sram_reg) &&
regulator_is_enabled(drv->sram_reg))
regulator_disable(drv->sram_reg);
return ret;

8
include/soc/rockchip/rk3588_grf.h
View File

@ -12,7 +12,11 @@
#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3 GENMASK(13, 12)
#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION GENMASK(31, 28)
#define RK3588_PMUGRF_OS_REG4 0x210
#define RK3588_PMUGRF_OS_REG5 0x214
#define RK3588_PMUGRF_OS_REG4 0x210
#define RK3588_PMUGRF_OS_REG5 0x214
#define RK3588_PMUGRF_OS_REG6 0x218
#define RK3588_PMUGRF_OS_REG6_LP5_BANK_MODE GENMASK(2, 1)
/* Whether the LPDDR5 is in 2:1 (= 0) or 4:1 (= 1) CKR a.k.a. DQS mode */
#define RK3588_PMUGRF_OS_REG6_LP5_CKR BIT(0)
#endif /* __SOC_RK3588_GRF_H */

1
include/soc/rockchip/rockchip_grf.h
View File

@ -13,6 +13,7 @@ enum {
ROCKCHIP_DDRTYPE_LPDDR3 = 6,
ROCKCHIP_DDRTYPE_LPDDR4 = 7,
ROCKCHIP_DDRTYPE_LPDDR4X = 8,
ROCKCHIP_DDRTYPE_LPDDR5 = 9,
};
#endif /* __SOC_ROCKCHIP_GRF_H */