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arm64: dts: qcom: kodiak: Fix the PCIe iommu-map entries

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The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe
iommu-map entries specify only one cell for the SID, omitting the SID
mask. This went unnoticed until the OF core started warning with commit
ccb2fd725d ("of: Respect #{iommu,msi}-cells in maps"):

  iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output

So fix the entries to match the provider's '#iommu-cells' property.

Fixes: f8328b7549 ("arm64: dts: qcom: sc7280: Describe the first PCIe controller and PHY")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-2-83405d37ba41@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Manivannan Sadhasivam 2026-07-30 13:55:43 +02:00 committed by Bjorn Andersson
parent 35eda0e5f8
commit 52dac5bda2
1 changed files with 4 additions and 4 deletions
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8
arch/arm64/boot/dts/qcom/kodiak.dtsi
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@ -2281,8 +2281,8 @@ pcie0: pcie@1c00000 {
"aggre0",
"aggre1";
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>,
<0x100 &apps_smmu 0x1c01 0x0 0x1>;
resets = <&gcc GCC_PCIE_0_BCR>;
reset-names = "pci";
@ -2423,8 +2423,8 @@ pcie1: pcie@1c08000 {
dma-coherent;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>,
<0x100 &apps_smmu 0x1c81 0x0 0x1>;
status = "disabled";