From 1cebcf9932ab76102e8cfc555879574693ba8956 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 9 Apr 2021 01:00:01 +0200 Subject: [PATCH 01/19] ARM: dts: stm32: Rework LAN8710Ai PHY reset on DHCOM SoM The Microchip LAN8710Ai PHY requires XTAL1/CLKIN external clock to be enabled when the nRST is toggled according to datasheet Microchip LAN8710A/LAN8710Ai DS00002164B page 35 section 3.8.5.1 Hardware Reset: " A Hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held low for the minimum time detailed in Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on page 59 to ensure a proper transceiver reset. During a Hardware reset, an external clock must be supplied to the XTAL1/CLKIN signal. " This is accidentally fulfilled in the current setup, where ETHCK_K is used to supply both PHY XTAL1/CLKIN and is also fed back through eth_clk_fb to supply ETHRX clock of the DWMAC. Hence, the DWMAC enables ETHRX clock, that has ETHCK_K as parent, so ETHCK_K clock are also enabled, and then the PHY reset toggles. However, this is not always the case, e.g. in case the PHY XTAL1/CLKIN clock are supplied by some other clock source than ETHCK_K or in case ETHRX clock are not supplied by ETHCK_K. In the later case, ETHCK_K would be kept disabled, while ETHRX clock would be enabled, so the PHY would not be receiving XTAL1/CLKIN clock and the reset would fail. Improve the DT by adding the PHY clock phandle into the PHY node, which then also requires moving the PHY reset GPIO specifier in the same place and that then also requires correct PHY reset GPIO timing, so add that too. A brief note regarding the timing, the datasheet says the reset should stay asserted for at least 100uS and software should wait at least 200nS after deassertion. Set both delays to 500uS which should be plenty. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 272a1a67a9ad..31d08423a32f 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -123,7 +123,6 @@ ðernet0 { max-speed = <100>; phy-handle = <&phy0>; st,eth-ref-clk-sel; - phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; mdio0 { #address-cells = <1>; @@ -132,6 +131,13 @@ mdio0 { phy0: ethernet-phy@1 { reg = <1>; + /* LAN8710Ai */ + compatible = "ethernet-phy-id0007.c0f0", + "ethernet-phy-ieee802.3-c22"; + clocks = <&rcc ETHCK_K>; + reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <500>; + reset-deassert-us = <500>; interrupt-parent = <&gpioi>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; }; From 28b9a4679d8074512f12967497c161b992eb3b75 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Apr 2021 17:00:12 +0200 Subject: [PATCH 02/19] ARM: dts: stm32: Remove extra size-cells on dhcom-pdk2 Fix make dtbs_check warning: arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dt.yaml: gpio-keys-polled: '#address-cells' is a dependency of '#size-cells' arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dt.yaml: gpio-keys: '#address-cells' is a dependency of '#size-cells' Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 5523f4138fd6..0fbf9913e8df 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -34,7 +34,6 @@ display_bl: display-bl { gpio-keys-polled { compatible = "gpio-keys-polled"; - #size-cells = <0>; poll-interval = <20>; /* @@ -60,7 +59,6 @@ button-2 { gpio-keys { compatible = "gpio-keys"; - #size-cells = <0>; button-1 { label = "TA2-GPIO-B"; From 4b5fadef3fc2ab8863ffdf31eed6a745b1bf6e61 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Apr 2021 17:00:13 +0200 Subject: [PATCH 03/19] ARM: dts: stm32: Fix touchscreen node on dhcom-pdk2 Fix make dtbs_check warning: arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dt.yaml:0:0: /soc/i2c@40015000/polytouch@38: failed to match any schema with compatible: ['edt,edt-ft5x06'] Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 0fbf9913e8df..b8c8f0b284c3 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -182,8 +182,8 @@ sgtl5000_rx_endpoint: endpoint@1 { }; - polytouch@38 { - compatible = "edt,edt-ft5x06"; + touchscreen@38 { + compatible = "edt,edt-ft5406"; reg = <0x38>; interrupt-parent = <&gpiog>; interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ From c90b2c4fc9c3f5660a359377aabc1998456ae5b1 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 26 Apr 2021 12:45:36 +0200 Subject: [PATCH 04/19] ARM: dts: stm32: Configure qspi's mdma transfer to block for stm32mp151 Configure qspi's mdma from buffer transfer (max 128 bytes) to block transfer (max 64K bytes). mtd_speedtest shows that write throughtput increases : - from 734 to 782 KiB/s (~6.5%) with s25fl512s SPI-NOR. - from 4848 to 5319 KiB/s (~9.72%) with Micron SPI-NAND. Signed-off-by: Christophe Kerello Signed-off-by: Patrice Chotard Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index fcd3230c469b..3f74d13995ac 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1369,8 +1369,8 @@ qspi: spi@58003000 { reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = ; - dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>, - <&mdma1 22 0x2 0x100008 0x0 0x0>; + dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, + <&mdma1 22 0x2 0x10100008 0x0 0x0>; dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; From 0171b07373cc8c2815ca5fa79a7308fdefa54ca4 Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Sat, 10 Apr 2021 21:35:21 +0200 Subject: [PATCH 05/19] ARM: dts: stm32: fix stm32mp157c-odyssey card detect pin MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The microSD card detect pin is physically connected to the MPU pin PI3. The Device Tree configuration of the card detect pin was wrong—it was set to pin PB7 instead. If such configuration was used, the kernel would hang on “Waiting for root device” when booting from a microSD card. Signed-off-by: Grzegorz Szymaszek Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-odyssey.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts index a7ffec8f1516..be1dd5e9e744 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts @@ -64,7 +64,7 @@ &sdmmc1 { pinctrl-0 = <&sdmmc1_b4_pins_a>; pinctrl-1 = <&sdmmc1_b4_od_pins_a>; pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + cd-gpios = <&gpioi 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; disable-wp; st,neg-edge; bus-width = <4>; From bf24b91f4baf7e421c770a1d9c7d381b10206ac9 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:25 +0200 Subject: [PATCH 06/19] ARM: dts: stm32: fix gpio-keys node on STM32 MCU boards Fix following warning observed with "make dtbs_check W=1" command. It concerns f429 eval and disco boards, f769 disco board. Warning (unit_address_vs_reg): /gpio_keys/button@0: node has a unit name, but no reg or ranges property Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32429i-eval.dts | 8 +++----- arch/arm/boot/dts/stm32746g-eval.dts | 6 ++---- arch/arm/boot/dts/stm32f429-disco.dts | 6 ++---- arch/arm/boot/dts/stm32f469-disco.dts | 6 ++---- arch/arm/boot/dts/stm32f769-disco.dts | 6 ++---- 5 files changed, 11 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 7e10ae744c9d..9ac1ffe53413 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -119,17 +119,15 @@ led-blue { }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "Wake up"; linux,code = ; gpios = <&gpioa 0 0>; }; - button@1 { + button-1 { label = "Tamper"; linux,code = ; gpios = <&gpioc 13 0>; diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index ca8c192449ee..327613fd9666 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -81,12 +81,10 @@ led-blue { }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "Wake up"; linux,code = ; gpios = <&gpioc 13 0>; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 3dc068b91ca1..075ac57d0bf4 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -81,12 +81,10 @@ led-green { }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = ; gpios = <&gpioa 0 0>; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 2e1b3bbbe4b5..8c982ae79f43 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -104,12 +104,10 @@ led-blue { }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = ; gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts index 0ce7fbc20fa4..be943b701980 100644 --- a/arch/arm/boot/dts/stm32f769-disco.dts +++ b/arch/arm/boot/dts/stm32f769-disco.dts @@ -75,12 +75,10 @@ led-red { }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + button-0 { label = "User"; linux,code = ; gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; From e4b948415a89a219d13e454011cdcf9e63ecc529 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:26 +0200 Subject: [PATCH 07/19] ARM: dts: stm32: fix RCC node name on stm32f429 MCU This prevent warning observed with "make dtbs_check W=1" Warning (simple_bus_reg): /soc/rcc@40023810: simple-bus unit address format error, expected "40023800" Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index f6530d724d00..41e0087bdbf9 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -709,7 +709,7 @@ crc: crc@40023000 { status = "disabled"; }; - rcc: rcc@40023810 { + rcc: rcc@40023800 { #reset-cells = <1>; #clock-cells = <2>; compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; From 2388f14d8747f8304e26ee870790e188c9431efd Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:27 +0200 Subject: [PATCH 08/19] ARM: dts: stm32: fix timer nodes on STM32 MCU to prevent warnings Prevent warning seen with "make dtbs_check W=1" command: Warning (avoid_unnecessary_addr_size): /soc/timers@40001c00: unnecessary address-cells/size-cells without "ranges" or child "reg" property Reviewed-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f429.dtsi | 8 -------- arch/arm/boot/dts/stm32f746.dtsi | 8 -------- arch/arm/boot/dts/stm32h743.dtsi | 4 ---- 3 files changed, 20 deletions(-) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 41e0087bdbf9..8748d5850298 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -283,8 +283,6 @@ timer@11 { }; timers13: timers@40001c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001C00 0x400>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; @@ -299,8 +297,6 @@ pwm { }; timers14: timers@40002000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; @@ -633,8 +629,6 @@ timer@8 { }; timers10: timers@40014400 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014400 0x400>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; @@ -649,8 +643,6 @@ pwm { }; timers11: timers@40014800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014800 0x400>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index e1df603fc981..72c1b76684b6 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -265,8 +265,6 @@ timer@11 { }; timers13: timers@40001c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40001C00 0x400>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; @@ -281,8 +279,6 @@ pwm { }; timers14: timers@40002000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40002000 0x400>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; @@ -531,8 +527,6 @@ timer@8 { }; timers10: timers@40014400 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014400 0x400>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; @@ -547,8 +541,6 @@ pwm { }; timers11: timers@40014800 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-timers"; reg = <0x40014800 0x400>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 05ecdf9ff03a..6e42ca2dada2 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -485,8 +485,6 @@ trigger@2 { }; lptimer4: timer@58002c00 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58002c00 0x400>; clocks = <&rcc LPTIM4_CK>; @@ -501,8 +499,6 @@ pwm { }; lptimer5: timer@58003000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x58003000 0x400>; clocks = <&rcc LPTIM5_CK>; From a52c468a9526dfe2f9a5d3c99f5dd362d0b5e3f4 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:29 +0200 Subject: [PATCH 09/19] ARM: dts: stm32: update pinctrl node name on STM32 MCU to prevent warnings Update node name to avoid a DT schema validation issue seen with "make dtbs_check W=1". It also cleans picntrl dtsi files for f429/f469 MCU. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 2 +- arch/arm/boot/dts/stm32f429-pinctrl.dtsi | 72 +++++++++++------------ arch/arm/boot/dts/stm32f469-pinctrl.dtsi | 74 +++++++++++------------- arch/arm/boot/dts/stm32f7-pinctrl.dtsi | 2 +- 4 files changed, 71 insertions(+), 79 deletions(-) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 4774163af54b..155d9ffacc83 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -45,7 +45,7 @@ / { soc { - pinctrl: pin-controller { + pinctrl: pin-controller@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; diff --git a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi index 3e7a17d9112e..e10d7a1f3207 100644 --- a/arch/arm/boot/dts/stm32f429-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f429-pinctrl.dtsi @@ -42,54 +42,50 @@ #include "stm32f4-pinctrl.dtsi" -/ { - soc { - pinctrl: pin-controller { - compatible = "st,stm32f429-pinctrl"; +&pinctrl { + compatible = "st,stm32f429-pinctrl"; - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 16>; - }; + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 16>; + }; - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 0 160 8>; - }; - }; + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 0 160 8>; }; }; diff --git a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi index fff542662eea..6bf60263dff8 100644 --- a/arch/arm/boot/dts/stm32f469-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f469-pinctrl.dtsi @@ -42,55 +42,51 @@ #include "stm32f4-pinctrl.dtsi" -/ { - soc { - pinctrl: pin-controller { - compatible = "st,stm32f469-pinctrl"; +&pinctrl { + compatible = "st,stm32f469-pinctrl"; - gpioa: gpio@40020000 { - gpio-ranges = <&pinctrl 0 0 16>; - }; + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; - gpiob: gpio@40020400 { - gpio-ranges = <&pinctrl 0 16 16>; - }; + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; - gpioc: gpio@40020800 { - gpio-ranges = <&pinctrl 0 32 16>; - }; + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; - gpiod: gpio@40020c00 { - gpio-ranges = <&pinctrl 0 48 16>; - }; + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; - gpioe: gpio@40021000 { - gpio-ranges = <&pinctrl 0 64 16>; - }; + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; - gpiof: gpio@40021400 { - gpio-ranges = <&pinctrl 0 80 16>; - }; + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; - gpiog: gpio@40021800 { - gpio-ranges = <&pinctrl 0 96 16>; - }; + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; - gpioh: gpio@40021c00 { - gpio-ranges = <&pinctrl 0 112 16>; - }; + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; - gpioi: gpio@40022000 { - gpio-ranges = <&pinctrl 0 128 16>; - }; + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; - gpioj: gpio@40022400 { - gpio-ranges = <&pinctrl 0 144 6>, - <&pinctrl 12 156 4>; - }; + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 6>, + <&pinctrl 12 156 4>; + }; - gpiok: gpio@40022800 { - gpio-ranges = <&pinctrl 3 163 5>; - }; - }; + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 3 163 5>; }; }; diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi index fe4cfda72a47..1cf8a23c2644 100644 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -9,7 +9,7 @@ / { soc { - pinctrl: pin-controller { + pinctrl: pin-controller@40020000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0x40020000 0x3000>; From ad0ed10ba5792064fc3accbf8f0341152a57eecb Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:30 +0200 Subject: [PATCH 10/19] ARM: dts: stm32: fix i2c node name on stm32f746 to prevent warnings Replace upper case by lower case in i2c nodes name. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32f746.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 72c1b76684b6..014b416f57e6 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -360,9 +360,9 @@ i2c2: i2c@40005800 { status = "disabled"; }; - i2c3: i2c@40005C00 { + i2c3: i2c@40005c00 { compatible = "st,stm32f7-i2c"; - reg = <0x40005C00 0x400>; + reg = <0x40005c00 0x400>; interrupts = <72>, <73>; resets = <&rcc STM32F7_APB1_RESET(I2C3)>; From fb1406335c067be074eab38206cf9abfdce2fb0b Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:31 +0200 Subject: [PATCH 11/19] ARM: dts: stm32: move stmmac axi config in ethernet node on stm32mp15 It fixes the following warning seen running "make dtbs_check W=1" Warning (simple_bus_reg): /soc/stmmac-axi-config: missing or empty reg/ranges property Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 3f74d13995ac..bd289bf5d269 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1416,12 +1416,6 @@ crc1: crc@58009000 { status = "disabled"; }; - stmmac_axi_config_0: stmmac-axi-config { - snps,wr_osr_lmt = <0x7>; - snps,rd_osr_lmt = <0x7>; - snps,blen = <0 0 0 0 16 8 4>; - }; - ethernet0: ethernet@5800a000 { compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; reg = <0x5800a000 0x2000>; @@ -1447,6 +1441,12 @@ ethernet0: ethernet@5800a000 { snps,axi-config = <&stmmac_axi_config_0>; snps,tso; status = "disabled"; + + stmmac_axi_config_0: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; }; usbh_ohci: usb@5800c000 { From fea99822914039c690a5322dd33d5abdc7c27ea3 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:32 +0200 Subject: [PATCH 12/19] dt-bindings: net: document ptp_ref clk in dwmac ptp_ref clk has been added in DT but not documented which makes yaml validation failed: ethernet@5800a000: clocks: [[6, 105], [6, 103], [6, 104], [6, 123], [6, 169], [6, 112]] is too long ethernet@5800a000: clock-names: ['stmmaceth', 'mac-clk-tx', 'mac-clk-rx', 'eth-ck', 'ptp_ref', 'ethstp'] is too long Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index 27eb6066793f..a1c490f3af02 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -46,17 +46,18 @@ properties: clocks: minItems: 3 - maxItems: 5 + maxItems: 6 items: - description: GMAC main clock - description: MAC TX clock - description: MAC RX clock - description: For MPU family, used for power mode - description: For MPU family, used for PHY without quartz + - description: PTP clock clock-names: minItems: 3 - maxItems: 5 + maxItems: 6 contains: enum: - stmmaceth @@ -64,6 +65,7 @@ properties: - mac-clk-rx - ethstp - eth-ck + - ptp_ref st,syscon: $ref: "/schemas/types.yaml#/definitions/phandle-array" From 11aaf2a0f8f070e87833775965950157bf57e49a Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:37 +0200 Subject: [PATCH 13/19] ARM: dts: stm32: fix ltdc pinctrl on microdev2.0-of7 It prevents the following warning: pin-controller@50002000: 'ltdc' does not match any of the regexes: '-[0-9]*$', '^gpio@[0-9a-f]*$', 'pinctrl-[0-9]+' Signed-off-by: Alexandre Torgue --- .../boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 674b2d330dc4..5670b23812a2 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -89,7 +89,7 @@ ltdc_ep0_out: endpoint@0 { }; &pinctrl { - ltdc_pins: ltdc { + ltdc_pins: ltdc-0 { pins { pinmux = , /* LTDC_B2 */ , /* LTDC_R6 */ From 02814a41529a55dbfb9fbb2a3728e78e70646ea6 Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Thu, 3 Jun 2021 17:34:18 +0200 Subject: [PATCH 14/19] ARM: dts: stm32: add a new DCMI pins group on stm32mp15 The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output. stm32mp15-pinctrl.dtsi contained one pin state definition for the DCMI interface, dcmi-0, AKA phandle dcmi_pins_a. This definition was incompatible with the pins used on the Odyssey board, where: - there are 8 data pins instead of 12, - DCMI_HSYNC is available at PA4 instead of PH8, - DCMI_D0 is at PC6 instead of PH9, - DCMI_D3 is at PE1 instead of PH12, - DCMI_D4 is at PE11 instead of PH14, - DCMI_D5 is at PD3 instead of PI4, - DCMI_D6 is at PE13 instead of PB8, - DCMI_D7 is at PB9 instead of PE6. Add the DCMI pins used on the Odyssey board as a new DCMI pin state definition, dcmi-1, AKA phandle dcmi_pins_b. Signed-off-by: Grzegorz Szymaszek Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 060baa8b7e9d..5b60ecbd718f 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -118,6 +118,39 @@ pins { }; }; + dcmi_pins_b: dcmi-1 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ;/* DCMI_D7 */ + bias-disable; + }; + }; + + dcmi_sleep_pins_b: dcmi-sleep-1 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ;/* DCMI_D7 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ From f493162319788802b6a49634f7268e691b4c10ec Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Thu, 3 Jun 2021 17:40:48 +0200 Subject: [PATCH 15/19] ARM: dts: stm32: fix the Odyssey SoM eMMC VQMMC supply MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Seeed SoM-STM32MP157C device tree had the eMMC’s (SDMMC2) VQMMC supply set to v3v3 (buck4), the same as the VMMC supply. That was incorrect, as on the SoM, the VQMMC supply is provided from vdd (buck3) instead. Signed-off-by: Grzegorz Szymaszek Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi index 6cf49a0a9e69..b5601d270c8f 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi @@ -269,7 +269,7 @@ &sdmmc2 { st,neg-edge; bus-width = <8>; vmmc-supply = <&v3v3>; - vqmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; mmc-ddr-3_3v; status = "okay"; }; From 5247a50c8b53ca214a488da648e1bb35c35c2597 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 10 Jun 2021 02:25:50 +0200 Subject: [PATCH 16/19] ARM: dts: stm32: Drop unused linux,wakeup from touchscreen node on DHCOM SoM Fix the following dtbs_check warning: touchscreen@38: 'linux,wakeup' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: kernel@dh-electronics.com Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index b8c8f0b284c3..c5ea08fec535 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -187,7 +187,6 @@ touchscreen@38 { reg = <0x38>; interrupt-parent = <&gpiog>; interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - linux,wakeup; }; }; From b586250df24226f8a257e11e1f5953054c54fd35 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 10 Jun 2021 02:25:51 +0200 Subject: [PATCH 17/19] ARM: dts: stm32: Rename eth@N to ethernet@N on DHCOM SoM Fix the following dtbs_check warning: eth@1,0: $nodename:0: 'eth@1,0' does not match '^ethernet(@.*)?$' Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: kernel@dh-electronics.com Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 31d08423a32f..c3e3466dacaa 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -150,7 +150,7 @@ &fmc { pinctrl-1 = <&fmc_sleep_pins_b>; status = "okay"; - ksz8851: ks8851mll@1,0 { + ksz8851: ethernet@1,0 { compatible = "micrel,ks8851-mll"; reg = <1 0x0 0x2>, <1 0x2 0x20000>; interrupt-parent = <&gpioc>; From 9b8a9b389d8464e1ca5a4e92c6a4422844ad4ef3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 10 Jun 2021 02:25:52 +0200 Subject: [PATCH 18/19] ARM: dts: stm32: Rename spi-flash/mx66l51235l@N to flash@N on DHCOM SoM Fix the following dtbs_check warning: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$' Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Patrice Chotard Cc: Patrick Delaunay Cc: kernel@dh-electronics.com Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 2 +- arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index c3e3466dacaa..8f4fd3a06a31 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -437,7 +437,7 @@ &qspi { #size-cells = <0>; status = "okay"; - flash0: mx66l51235l@0 { + flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index 013ae369791d..2b0ac605549d 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -198,7 +198,7 @@ &qspi { #size-cells = <0>; status = "okay"; - flash0: spi-flash@0 { + flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; From 4bf4abe19089245b7b12f35e5cafb5477b3e2c48 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 15 Apr 2021 12:10:33 +0200 Subject: [PATCH 19/19] ARM: dts: stm32: fix stpmic node for stm32mp1 boards On some STM32 MP15 boards, stpmic node is not correct which generates warnings running "make dtbs_check W=1" command. Issues are: -"regulator-active-discharge" is not a boolean but an uint32. -"regulator-over-current-protection" is not a valid entry for vref_ddr. -LDO4 has a fixed voltage (3v3) so min/max entries are not allowed. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-stinger96.dtsi | 7 ++----- arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi | 5 +---- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 5 +---- arch/arm/boot/dts/stm32mp15xx-osd32.dtsi | 7 ++----- 4 files changed, 6 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi index 113c48b2ef93..a4b14ef3caee 100644 --- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi @@ -184,8 +184,6 @@ vtt_ddr: ldo3 { vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = ; }; @@ -208,7 +206,6 @@ v1v8: ldo6 { vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -219,13 +216,13 @@ bst_out: boost { vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi index b5601d270c8f..2d9461006810 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi @@ -173,8 +173,6 @@ vtt_ddr: ldo3 { vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = ; }; @@ -197,7 +195,6 @@ v1v2_hdmi: ldo6 { vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -213,7 +210,7 @@ vbus_otg: pwr_sw1 { vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 8f4fd3a06a31..2af0a6752674 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -333,8 +333,6 @@ vtt_ddr: ldo3 { vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = ; }; @@ -356,7 +354,6 @@ v1v8: ldo6 { vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -372,7 +369,7 @@ vbus_otg: pwr_sw1 { vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi index 713485a95795..6706d8311a66 100644 --- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi @@ -146,8 +146,6 @@ vtt_ddr: ldo3 { vdd_usb: ldo4 { regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; interrupts = ; }; @@ -171,7 +169,6 @@ v1v2_hdmi: ldo6 { vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -182,13 +179,13 @@ bst_out: boost { vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = ; - regulator-active-discharge; + regulator-active-discharge = <1>; }; };