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swim: Perform ISM/IWM mode switching according to specs

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The SWIM spec says, "MOTOREN must be low to switch modes" and "after
switching from ISM to IWM, the very first command must be a clear L7".

The ISM spec says, MOTOREN "must not be cleared until after the Action
bit is cleared". Perform those operations in the correct sequence.

When switching to ISM mode, the Mode register has to be selected with a
particular sequence of bit flips. Set q7 low then q6 low then mtrOff.

Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Fixes: 8852ecd974 ("m68k: mac - Add SWIM floppy support")
Signed-off-by: Finn Thain <fthain@linux-m68k.org>
Tested-by: Stan Johnson <userm57@yahoo.com>
Link: https://patch.msgid.link/75714ecc9a12d59511967dc9e24163dc8f3bbdd8.1788513996.git.fthain@linux-m68k.org
Signed-off-by: Jens Axboe <axboe@kernel.dk>
This commit is contained in:
Finn Thain 2026-09-04 19:26:36 +10:00 committed by Jens Axboe
parent 05a7c4b197
commit 52981bb358
1 changed files with 7 additions and 3 deletions
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10
drivers/block/swim.c
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@ -149,6 +149,7 @@ struct iwm {
#define ACTION 0x08
#define WRITE_MODE 0x10
#define HEDSEL 0x20
#define ISM_SELECT 0x40
#define MOTON 0x80
/*----------------------------------------------------------------------------*/
@ -223,18 +224,21 @@ extern int swim_read_sector_data(struct swim __iomem *base,
static DEFINE_MUTEX(swim_mutex);
static inline void set_swim_mode(struct swim __iomem *base, int enable)
{
struct iwm __iomem *iwm_base;
struct iwm __iomem *iwm_base = (struct iwm __iomem *)base;
unsigned long flags;
if (!enable) {
swim_write(base, mode0, 0xf8);
swim_write(base, mode0, ACTION);
swim_write(base, mode0, ENBL1 | ENBL2 | MOTON);
swim_write(base, mode0, ISM_SELECT);
iwm_read(iwm_base, q7L);
return;
}
iwm_base = (struct iwm __iomem *)base;
local_irq_save(flags);
iwm_read(iwm_base, q7L);
iwm_read(iwm_base, q6L);
iwm_read(iwm_base, mtrOff);
iwm_read(iwm_base, q6H);