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arm64: dts: qcom: x1e80100: Affirm IDR0.CCTW on apps_smmu

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On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-11-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Konrad Dybcio 2024-09-19 00:57:24 +02:00 committed by Bjorn Andersson
parent c9ab665276
commit 5207d9c75f
1 changed files with 2 additions and 0 deletions
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arch/arm64/boot/dts/qcom/x1e80100.dtsi
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@ -5738,6 +5738,8 @@ apps_smmu: iommu@15000000 {
#iommu-cells = <2>;
#global-interrupts = <1>;
dma-coherent;
};
intc: interrupt-controller@17000000 {