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pinctrl: equilibrium: Convert to immutable irq_chip

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Convert the driver to immutable irq-chip with a bit of
intuition.

Cc: Marc Zyngier <maz@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230403-immutable-irqchips-v1-5-503788a7f6e6@linaro.org
This commit is contained in:
Linus Walleij 2023-04-04 11:43:07 +02:00
parent dcea54b7da
commit 52066a53bd
2 changed files with 14 additions and 10 deletions
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22
drivers/pinctrl/pinctrl-equilibrium.c
View File

@ -32,6 +32,7 @@ static void eqbr_gpio_disable_irq(struct irq_data *d)
raw_spin_lock_irqsave(&gctrl->lock, flags); raw_spin_lock_irqsave(&gctrl->lock, flags);
writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);
raw_spin_unlock_irqrestore(&gctrl->lock, flags); raw_spin_unlock_irqrestore(&gctrl->lock, flags);
gpiochip_disable_irq(gc, offset);
} }
static void eqbr_gpio_enable_irq(struct irq_data *d) static void eqbr_gpio_enable_irq(struct irq_data *d)
@ -42,6 +43,7 @@ static void eqbr_gpio_enable_irq(struct irq_data *d)
unsigned long flags; unsigned long flags;
gc->direction_input(gc, offset); gc->direction_input(gc, offset);
gpiochip_enable_irq(gc, offset);
raw_spin_lock_irqsave(&gctrl->lock, flags); raw_spin_lock_irqsave(&gctrl->lock, flags);
writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET);
raw_spin_unlock_irqrestore(&gctrl->lock, flags); raw_spin_unlock_irqrestore(&gctrl->lock, flags);
@ -161,6 +163,17 @@ static void eqbr_irq_handler(struct irq_desc *desc)
chained_irq_exit(ic, desc); chained_irq_exit(ic, desc);
} }
static const struct irq_chip eqbr_irq_chip = {
.name = "gpio_irq",
.irq_mask = eqbr_gpio_disable_irq,
.irq_unmask = eqbr_gpio_enable_irq,
.irq_ack = eqbr_gpio_ack_irq,
.irq_mask_ack = eqbr_gpio_mask_ack_irq,
.irq_set_type = eqbr_gpio_set_irq_type,
.flags = IRQCHIP_IMMUTABLE,
GPIOCHIP_IRQ_RESOURCE_HELPERS,
};
static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl) static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl)
{ {
struct gpio_irq_chip *girq; struct gpio_irq_chip *girq;
@ -176,15 +189,8 @@ static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl)
return 0; return 0;
} }
gctrl->ic.name = "gpio_irq";
gctrl->ic.irq_mask = eqbr_gpio_disable_irq;
gctrl->ic.irq_unmask = eqbr_gpio_enable_irq;
gctrl->ic.irq_ack = eqbr_gpio_ack_irq;
gctrl->ic.irq_mask_ack = eqbr_gpio_mask_ack_irq;
gctrl->ic.irq_set_type = eqbr_gpio_set_irq_type;
girq = &gctrl->chip.irq; girq = &gctrl->chip.irq;
girq->chip = &gctrl->ic; gpio_irq_chip_set_chip(girq, &eqbr_irq_chip);
girq->parent_handler = eqbr_irq_handler; girq->parent_handler = eqbr_irq_handler;
girq->num_parents = 1; girq->num_parents = 1;
girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL); girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL);

2
drivers/pinctrl/pinctrl-equilibrium.h
View File

@ -103,7 +103,6 @@ struct fwnode_handle;
* @fwnode: firmware node of gpio controller. * @fwnode: firmware node of gpio controller.
* @bank: pointer to corresponding pin bank. * @bank: pointer to corresponding pin bank.
* @membase: base address of the gpio controller. * @membase: base address of the gpio controller.
* @ic: irq chip.
* @name: gpio chip name. * @name: gpio chip name.
* @virq: irq number of the gpio chip to parent's irq domain. * @virq: irq number of the gpio chip to parent's irq domain.
* @lock: spin lock to protect gpio register write. * @lock: spin lock to protect gpio register write.
@ -113,7 +112,6 @@ struct eqbr_gpio_ctrl {
struct fwnode_handle *fwnode; struct fwnode_handle *fwnode;
struct eqbr_pin_bank *bank; struct eqbr_pin_bank *bank;
void __iomem *membase; void __iomem *membase;
struct irq_chip ic;
const char *name; const char *name;
unsigned int virq; unsigned int virq;
raw_spinlock_t lock; /* protect gpio register */ raw_spinlock_t lock; /* protect gpio register */