Merge branch 'pci/controller/j721e'

- Use devm_clk_get_optional_enabled() instead of open-coding
  devm_clk_get_optional() and clk_prepare_enable() (Anand Moon)

* pci/controller/j721e:
  PCI: j721e: Use 'pcie->reset_gpio' directly and drop the local variable
  PCI: j721e: Use devm_clk_get_optional_enabled() to get and enable the clock
This commit is contained in:
Bjorn Helgaas 2025-12-03 14:18:37 -06:00
commit 51f8276926

View File

@ -477,9 +477,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
struct j721e_pcie *pcie;
struct cdns_pcie_rc *rc = NULL;
struct cdns_pcie_ep *ep = NULL;
struct gpio_desc *gpiod;
void __iomem *base;
struct clk *clk;
u32 num_lanes;
u32 mode;
int ret;
@ -590,12 +588,12 @@ static int j721e_pcie_probe(struct platform_device *pdev)
switch (mode) {
case PCI_MODE_RC:
gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(gpiod)) {
ret = dev_err_probe(dev, PTR_ERR(gpiod), "Failed to get reset GPIO\n");
pcie->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(pcie->reset_gpio)) {
ret = dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
"Failed to get reset GPIO\n");
goto err_get_sync;
}
pcie->reset_gpio = gpiod;
ret = cdns_pcie_init_phy(dev, cdns_pcie);
if (ret) {
@ -603,19 +601,13 @@ static int j721e_pcie_probe(struct platform_device *pdev)
goto err_get_sync;
}
clk = devm_clk_get_optional(dev, "pcie_refclk");
if (IS_ERR(clk)) {
ret = dev_err_probe(dev, PTR_ERR(clk), "failed to get pcie_refclk\n");
pcie->refclk = devm_clk_get_optional_enabled(dev, "pcie_refclk");
if (IS_ERR(pcie->refclk)) {
ret = dev_err_probe(dev, PTR_ERR(pcie->refclk),
"failed to enable pcie_refclk\n");
goto err_pcie_setup;
}
ret = clk_prepare_enable(clk);
if (ret) {
dev_err_probe(dev, ret, "failed to enable pcie_refclk\n");
goto err_pcie_setup;
}
pcie->refclk = clk;
/*
* Section 2.2 of the PCI Express Card Electromechanical
* Specification (Revision 5.1) mandates that the deassertion
@ -623,16 +615,14 @@ static int j721e_pcie_probe(struct platform_device *pdev)
* This shall ensure that the power and the reference clock
* are stable.
*/
if (gpiod) {
if (pcie->reset_gpio) {
msleep(PCIE_T_PVPERL_MS);
gpiod_set_value_cansleep(gpiod, 1);
gpiod_set_value_cansleep(pcie->reset_gpio, 1);
}
ret = cdns_pcie_host_setup(rc);
if (ret < 0) {
clk_disable_unprepare(pcie->refclk);
if (ret < 0)
goto err_pcie_setup;
}
break;
case PCI_MODE_EP:
@ -679,7 +669,6 @@ static void j721e_pcie_remove(struct platform_device *pdev)
gpiod_set_value_cansleep(pcie->reset_gpio, 0);
clk_disable_unprepare(pcie->refclk);
cdns_pcie_disable_phy(cdns_pcie);
j721e_pcie_disable_link_irq(pcie);
pm_runtime_put(dev);