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Merge branch kvm-arm64/nv-trap-fixes into kvmarm/next
* kvm-arm64/nv-trap-fixes:
: NV trap forwarding fixes, courtesy Miguel Luis and Marc Zyngier
:
: - Explicitly define the effects of HCR_EL2.NV on EL2 sysregs in the
: NV trap encoding
:
: - Make EL2 registers that access AArch32 guest state UNDEF or RAZ/WI
: where appropriate for NV guests
KVM: arm64: Handle AArch32 SPSR_{irq,abt,und,fiq} as RAZ/WI
KVM: arm64: Do not let a L1 hypervisor access the *32_EL2 sysregs
KVM: arm64: Refine _EL2 system register list that require trap reinjection
arm64: Add missing _EL2 encodings
arm64: Add missing _EL12 encodings
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
This commit is contained in:
Oliver Upton
commit
51e6079614
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@ -270,6 +270,8 @@
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/* ETM */
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#define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
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#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
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#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
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#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
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#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
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@ -484,6 +486,7 @@
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#define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
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#define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
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#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
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#define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
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#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
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#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
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@ -497,10 +500,15 @@
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#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
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#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
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#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
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#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
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#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
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#define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
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#define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
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#define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
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#define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
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#define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
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#define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
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#define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
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#define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
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#define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
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@ -514,6 +522,18 @@
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#define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
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#define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
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#define SYS_MPAMHCR_EL2 sys_reg(3, 4, 10, 4, 0)
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#define SYS_MPAMVPMV_EL2 sys_reg(3, 4, 10, 4, 1)
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#define SYS_MPAM2_EL2 sys_reg(3, 4, 10, 5, 0)
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#define __SYS__MPAMVPMx_EL2(x) sys_reg(3, 4, 10, 6, x)
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#define SYS_MPAMVPM0_EL2 __SYS__MPAMVPMx_EL2(0)
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#define SYS_MPAMVPM1_EL2 __SYS__MPAMVPMx_EL2(1)
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#define SYS_MPAMVPM2_EL2 __SYS__MPAMVPMx_EL2(2)
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#define SYS_MPAMVPM3_EL2 __SYS__MPAMVPMx_EL2(3)
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#define SYS_MPAMVPM4_EL2 __SYS__MPAMVPMx_EL2(4)
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#define SYS_MPAMVPM5_EL2 __SYS__MPAMVPMx_EL2(5)
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#define SYS_MPAMVPM6_EL2 __SYS__MPAMVPMx_EL2(6)
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#define SYS_MPAMVPM7_EL2 __SYS__MPAMVPMx_EL2(7)
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#define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
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#define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
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@ -562,24 +582,49 @@
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#define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
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#define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
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#define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
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#define __AMEV_op2(m) (m & 0x7)
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#define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
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#define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
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#define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m)
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#define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
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#define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m)
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#define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
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#define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
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#define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
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#define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
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#define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
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#define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
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#define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
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#define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
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/* VHE encodings for architectural EL0/1 system registers */
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#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
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#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
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#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
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#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
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#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
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#define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
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#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
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#define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
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#define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
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#define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
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#define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3)
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#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
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#define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
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#define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
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#define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
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#define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
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#define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
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#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
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#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
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#define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
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#define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
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#define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
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#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
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#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
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#define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
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#define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
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#define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
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@ -648,15 +648,80 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
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SR_TRAP(SYS_APGAKEYLO_EL1, CGT_HCR_APK),
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SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK),
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/* All _EL2 registers */
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SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0),
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sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV),
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SR_TRAP(SYS_BRBCR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_VPIDR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_VMPIDR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_SCTLR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_ACTLR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_SCTLR2_EL2, CGT_HCR_NV),
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SR_RANGE_TRAP(SYS_HCR_EL2,
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SYS_HCRX_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_SMPRIMAP_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_SMCR_EL2, CGT_HCR_NV),
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SR_RANGE_TRAP(SYS_TTBR0_EL2,
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SYS_TCR2_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_VTTBR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_VTCR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_VNCR_EL2, CGT_HCR_NV),
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SR_RANGE_TRAP(SYS_HDFGRTR_EL2,
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SYS_HAFGRTR_EL2, CGT_HCR_NV),
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/* Skip the SP_EL1 encoding... */
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SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV),
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SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1),
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sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV),
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SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0),
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sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV),
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/* Skip SPSR_irq, SPSR_abt, SPSR_und, SPSR_fiq */
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SR_TRAP(SYS_AFSR0_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_AFSR1_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_ESR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_VSESR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_TFSR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_FAR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_HPFAR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_PMSCR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_MAIR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_AMAIR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_MPAMHCR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_MPAMVPMV_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_MPAM2_EL2, CGT_HCR_NV),
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SR_RANGE_TRAP(SYS_MPAMVPM0_EL2,
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SYS_MPAMVPM7_EL2, CGT_HCR_NV),
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/*
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* Note that the spec. describes a group of MEC registers
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* whose access should not trap, therefore skip the following:
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* MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2,
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* MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2,
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* VMECID_P_EL2.
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*/
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SR_RANGE_TRAP(SYS_VBAR_EL2,
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SYS_RMR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_VDISR_EL2, CGT_HCR_NV),
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/* ICH_AP0R<m>_EL2 */
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SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2,
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SYS_ICH_AP0R3_EL2, CGT_HCR_NV),
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/* ICH_AP1R<m>_EL2 */
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SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2,
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SYS_ICH_AP1R3_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_ICC_SRE_EL2, CGT_HCR_NV),
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SR_RANGE_TRAP(SYS_ICH_HCR_EL2,
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SYS_ICH_EISR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_ICH_ELRSR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_ICH_VMCR_EL2, CGT_HCR_NV),
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/* ICH_LR<m>_EL2 */
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SR_RANGE_TRAP(SYS_ICH_LR0_EL2,
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SYS_ICH_LR15_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_CONTEXTIDR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_TPIDR_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_SCXTNUM_EL2, CGT_HCR_NV),
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/* AMEVCNTVOFF0<n>_EL2, AMEVCNTVOFF1<n>_EL2 */
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SR_RANGE_TRAP(SYS_AMEVCNTVOFF0n_EL2(0),
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SYS_AMEVCNTVOFF1n_EL2(15), CGT_HCR_NV),
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/* CNT*_EL2 */
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SR_TRAP(SYS_CNTVOFF_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_CNTPOFF_EL2, CGT_HCR_NV),
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SR_TRAP(SYS_CNTHCTL_EL2, CGT_HCR_NV),
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SR_RANGE_TRAP(SYS_CNTHP_TVAL_EL2,
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SYS_CNTHP_CVAL_EL2, CGT_HCR_NV),
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SR_RANGE_TRAP(SYS_CNTHV_TVAL_EL2,
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SYS_CNTHV_CVAL_EL2, CGT_HCR_NV),
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/* All _EL02, _EL12 registers */
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SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0),
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sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV),
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@ -1795,8 +1795,8 @@ static unsigned int el2_visibility(const struct kvm_vcpu *vcpu,
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* HCR_EL2.E2H==1, and only in the sysreg table for convenience of
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* handling traps. Given that, they are always hidden from userspace.
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*/
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static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd)
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static unsigned int hidden_user_visibility(const struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd)
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{
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return REG_HIDDEN_USER;
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}
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@ -1807,7 +1807,7 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu,
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.reset = rst, \
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.reg = name##_EL1, \
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.val = v, \
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.visibility = elx2_visibility, \
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.visibility = hidden_user_visibility, \
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}
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/*
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@ -1965,7 +1965,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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// DBGDTR[TR]X_EL0 share the same encoding
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{ SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
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{ SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
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{ SYS_DESC(SYS_DBGVCR32_EL2), trap_undef, reset_val, DBGVCR32_EL2, 0 },
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{ SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
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@ -2384,18 +2384,28 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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EL2_REG(VTTBR_EL2, access_rw, reset_val, 0),
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EL2_REG(VTCR_EL2, access_rw, reset_val, 0),
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{ SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
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{ SYS_DESC(SYS_DACR32_EL2), trap_undef, reset_unknown, DACR32_EL2 },
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EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0),
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EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0),
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EL2_REG(SPSR_EL2, access_rw, reset_val, 0),
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EL2_REG(ELR_EL2, access_rw, reset_val, 0),
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{ SYS_DESC(SYS_SP_EL1), access_sp_el1},
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{ SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
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/* AArch32 SPSR_* are RES0 if trapped from a NV guest */
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{ SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi,
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.visibility = hidden_user_visibility },
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{ SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi,
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.visibility = hidden_user_visibility },
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{ SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi,
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.visibility = hidden_user_visibility },
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{ SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi,
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.visibility = hidden_user_visibility },
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{ SYS_DESC(SYS_IFSR32_EL2), trap_undef, reset_unknown, IFSR32_EL2 },
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EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
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EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
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EL2_REG(ESR_EL2, access_rw, reset_val, 0),
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{ SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
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{ SYS_DESC(SYS_FPEXC32_EL2), trap_undef, reset_val, FPEXC32_EL2, 0x700 },
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EL2_REG(FAR_EL2, access_rw, reset_val, 0),
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EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
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