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net: ethernet: mtk_eth_soc: add support for MT7988 internal 2.5G PHY
The MediaTek MT7988 SoC comes with an single built-in Ethernet PHY for 2500Base-T/1000Base-T/100Base-TX/10Base-T link partners in addition to the built-in 1GE switch. The built-in PHY only supports full duplex. Add muxes allowing to select GMAC2->2.5G PHY path and add basic support for XGMAC as the built-in 2.5G PHY is internally connected via XGMII. The XGMAC features will also be used by 5GBase-R, 10GBase-R and USXGMII SerDes modes which are going to be added once support for standalone PCS drivers is in place. In order to make use of the built-in 2.5G PHY the appropriate PHY driver as well as (proprietary) PHY firmware has to be present as well. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://patch.msgid.link/9072cefbff6db969720672ec98ed5cef65e8218c.1745715380.git.daniel@makrotopia.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Daniel Golle
Jakub Kicinski
parent
7a4f15cadc
commit
51cf06ddaf
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@ -31,6 +31,8 @@ static const char *mtk_eth_path_name(u64 path)
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return "gmac2_rgmii";
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case MTK_ETH_PATH_GMAC2_SGMII:
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return "gmac2_sgmii";
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case MTK_ETH_PATH_GMAC2_2P5GPHY:
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return "gmac2_2p5gphy";
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case MTK_ETH_PATH_GMAC2_GEPHY:
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return "gmac2_gephy";
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case MTK_ETH_PATH_GDM1_ESW:
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@ -127,6 +129,29 @@ static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path)
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return 0;
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}
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static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path)
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{
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int ret;
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if (path == MTK_ETH_PATH_GMAC2_2P5GPHY) {
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ret = regmap_clear_bits(eth->ethsys, ETHSYS_SYSCFG0,
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SYSCFG0_SGMII_GMAC2_V2);
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if (ret)
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return ret;
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/* Setup mux to 2p5g PHY */
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ret = regmap_clear_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX,
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MUX_G2_USXGMII_SEL);
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if (ret)
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return ret;
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dev_dbg(eth->dev, "path %s in %s updated\n",
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mtk_eth_path_name(path), __func__);
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}
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return 0;
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}
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static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
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{
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unsigned int val = 0;
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@ -209,6 +234,10 @@ static const struct mtk_eth_muxc mtk_eth_muxc[] = {
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.name = "mux_u3_gmac2_to_qphy",
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.cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
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.set_path = set_mux_u3_gmac2_to_qphy,
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}, {
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.name = "mux_gmac2_to_2p5gphy",
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.cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,
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.set_path = set_mux_gmac2_to_2p5gphy,
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}, {
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.name = "mux_gmac1_gmac2_to_sgmii_rgmii",
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.cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII,
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@ -260,6 +289,20 @@ int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
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return mtk_eth_mux_setup(eth, path);
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}
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int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id)
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{
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u64 path = 0;
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if (mac_id == MTK_GMAC2_ID)
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path = MTK_ETH_PATH_GMAC2_2P5GPHY;
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if (!path)
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return -EINVAL;
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/* Setup proper MUXes along the path */
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return mtk_eth_mux_setup(eth, path);
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}
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int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id)
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{
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u64 path = 0;
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@ -503,7 +503,7 @@ static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
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static void mtk_setup_bridge_switch(struct mtk_eth *eth)
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{
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/* Force Port1 XGMAC Link Up */
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mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID),
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mtk_m32(eth, 0, MTK_XGMAC_FORCE_MODE(MTK_GMAC1_ID),
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MTK_XGMAC_STS(MTK_GMAC1_ID));
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/* Adjust GSW bridge IPG to 11 */
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@ -532,6 +532,26 @@ static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
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return NULL;
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}
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static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode,
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phy_interface_t iface)
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{
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struct mtk_mac *mac = container_of(config, struct mtk_mac,
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phylink_config);
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struct mtk_eth *eth = mac->hw;
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if (mtk_interface_mode_is_xgmii(eth, iface) &&
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mac->id != MTK_GMAC1_ID) {
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mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE,
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XMAC_MCR_TRX_DISABLE, MTK_XMAC_MCR(mac->id));
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mtk_m32(mac->hw, MTK_XGMAC_FORCE_MODE(mac->id) |
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MTK_XGMAC_FORCE_LINK(mac->id),
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MTK_XGMAC_FORCE_MODE(mac->id), MTK_XGMAC_STS(mac->id));
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}
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return 0;
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}
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static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
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const struct phylink_link_state *state)
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{
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@ -573,6 +593,12 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
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}
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break;
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case PHY_INTERFACE_MODE_INTERNAL:
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if (mac->id == MTK_GMAC2_ID &&
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MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) {
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err = mtk_gmac_2p5gphy_path_setup(eth, mac->id);
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if (err)
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goto init_err;
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}
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break;
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default:
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goto err_phy;
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@ -644,12 +670,12 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
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}
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/* Setup gmac */
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if (mtk_is_netsys_v3_or_greater(eth) &&
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mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
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if (mtk_interface_mode_is_xgmii(eth, state->interface)) {
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mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
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mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
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mtk_setup_bridge_switch(eth);
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if (mac->id == MTK_GMAC1_ID)
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mtk_setup_bridge_switch(eth);
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}
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return;
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@ -696,10 +722,19 @@ static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
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{
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struct mtk_mac *mac = container_of(config, struct mtk_mac,
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phylink_config);
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u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
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mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK);
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mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
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if (!mtk_interface_mode_is_xgmii(mac->hw, interface)) {
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/* GMAC modes */
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mtk_m32(mac->hw,
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MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK, 0,
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MTK_MAC_MCR(mac->id));
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} else if (mac->id != MTK_GMAC1_ID) {
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/* XGMAC except for built-in switch */
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mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE,
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MTK_XMAC_MCR(mac->id));
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mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0,
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MTK_XGMAC_STS(mac->id));
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}
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}
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static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
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@ -771,13 +806,12 @@ static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
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mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
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}
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static void mtk_mac_link_up(struct phylink_config *config,
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struct phy_device *phy,
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unsigned int mode, phy_interface_t interface,
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int speed, int duplex, bool tx_pause, bool rx_pause)
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static void mtk_gdm_mac_link_up(struct mtk_mac *mac,
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struct phy_device *phy,
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unsigned int mode, phy_interface_t interface,
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int speed, int duplex, bool tx_pause,
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bool rx_pause)
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{
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struct mtk_mac *mac = container_of(config, struct mtk_mac,
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phylink_config);
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u32 mcr;
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mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
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@ -811,6 +845,56 @@ static void mtk_mac_link_up(struct phylink_config *config,
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mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
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}
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static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
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struct phy_device *phy,
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unsigned int mode, phy_interface_t interface,
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int speed, int duplex, bool tx_pause,
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bool rx_pause)
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{
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u32 mcr;
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if (mac->id == MTK_GMAC1_ID)
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return;
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/* Eliminate the interference(before link-up) caused by PHY noise */
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mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id));
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mdelay(20);
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mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR,
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MTK_XMAC_CNT_CTRL(mac->id));
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mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id),
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MTK_XGMAC_FORCE_LINK(mac->id), MTK_XGMAC_STS(mac->id));
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mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
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mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC |
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XMAC_MCR_TRX_DISABLE);
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/* Configure pause modes -
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* phylink will avoid these for half duplex
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*/
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if (tx_pause)
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mcr |= XMAC_MCR_FORCE_TX_FC;
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if (rx_pause)
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mcr |= XMAC_MCR_FORCE_RX_FC;
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mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
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}
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static void mtk_mac_link_up(struct phylink_config *config,
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struct phy_device *phy,
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unsigned int mode, phy_interface_t interface,
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int speed, int duplex, bool tx_pause, bool rx_pause)
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{
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struct mtk_mac *mac = container_of(config, struct mtk_mac,
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phylink_config);
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if (mtk_interface_mode_is_xgmii(mac->hw, interface))
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mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
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tx_pause, rx_pause);
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else
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mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
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tx_pause, rx_pause);
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}
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static void mtk_mac_disable_tx_lpi(struct phylink_config *config)
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{
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struct mtk_mac *mac = container_of(config, struct mtk_mac,
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@ -828,6 +912,9 @@ static int mtk_mac_enable_tx_lpi(struct phylink_config *config, u32 timer,
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struct mtk_eth *eth = mac->hw;
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u32 val;
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if (mtk_interface_mode_is_xgmii(eth, mac->interface))
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return -EOPNOTSUPP;
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/* Tx idle timer in ms */
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timer = DIV_ROUND_UP(timer, 1000);
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@ -858,6 +945,7 @@ static int mtk_mac_enable_tx_lpi(struct phylink_config *config, u32 timer,
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}
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static const struct phylink_mac_ops mtk_phylink_ops = {
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.mac_prepare = mtk_mac_prepare,
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.mac_select_pcs = mtk_mac_select_pcs,
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.mac_config = mtk_mac_config,
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.mac_finish = mtk_mac_finish,
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@ -4763,6 +4851,11 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
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mac->phylink = phylink;
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if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY) &&
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id == MTK_GMAC2_ID)
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__set_bit(PHY_INTERFACE_MODE_INTERNAL,
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mac->phylink_config.supported_interfaces);
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SET_NETDEV_DEV(eth->netdev[id], eth->dev);
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eth->netdev[id]->watchdog_timeo = 5 * HZ;
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eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
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@ -431,7 +431,8 @@
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/* XMAC status registers */
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#define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C)
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#define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15))
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#define MTK_XGMAC_FORCE_MODE(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15))
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#define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(27) : BIT(11))
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#define MTK_USXGMII_PCS_LINK BIT(8)
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#define MTK_XGMAC_RX_FC BIT(5)
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#define MTK_XGMAC_TX_FC BIT(4)
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@ -524,6 +525,21 @@
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#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
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#define INTF_MODE_RGMII_10_100 0
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/* XFI Mac control registers */
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#define MTK_XMAC_BASE(x) (0x12000 + (((x) - 1) * 0x1000))
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#define MTK_XMAC_MCR(x) (MTK_XMAC_BASE(x))
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#define XMAC_MCR_TRX_DISABLE 0xf
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#define XMAC_MCR_FORCE_TX_FC BIT(5)
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#define XMAC_MCR_FORCE_RX_FC BIT(4)
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/* XFI Mac logic reset registers */
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#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10)
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#define XMAC_LOGIC_RST BIT(0)
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/* XFI Mac count global control */
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#define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100)
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#define XMAC_GLB_CNTCLR BIT(0)
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/* GPIO port control registers for GMAC 2*/
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#define GPIO_OD33_CTRL8 0x4c0
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#define GPIO_BIAS_CTRL 0xed0
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@ -587,6 +603,10 @@
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#define GEPHY_MAC_SEL BIT(1)
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/* Top misc registers */
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#define TOP_MISC_NETSYS_PCS_MUX 0x0
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#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
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#define MUX_G2_USXGMII_SEL BIT(1)
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#define USB_PHY_SWITCH_REG 0x218
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#define QPHY_SEL_MASK GENMASK(1, 0)
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#define SGMII_QPHY_SEL 0x2
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@ -951,6 +971,7 @@ enum mkt_eth_capabilities {
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MTK_RGMII_BIT = 0,
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MTK_TRGMII_BIT,
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MTK_SGMII_BIT,
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MTK_2P5GPHY_BIT,
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MTK_ESW_BIT,
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MTK_GEPHY_BIT,
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MTK_MUX_BIT,
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@ -971,6 +992,7 @@ enum mkt_eth_capabilities {
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MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
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MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
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MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
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MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
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MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
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MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
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@ -980,6 +1002,7 @@ enum mkt_eth_capabilities {
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MTK_ETH_PATH_GMAC1_SGMII_BIT,
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MTK_ETH_PATH_GMAC2_RGMII_BIT,
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MTK_ETH_PATH_GMAC2_SGMII_BIT,
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MTK_ETH_PATH_GMAC2_2P5GPHY_BIT,
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MTK_ETH_PATH_GMAC2_GEPHY_BIT,
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MTK_ETH_PATH_GDM1_ESW_BIT,
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};
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@ -988,6 +1011,7 @@ enum mkt_eth_capabilities {
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#define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
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#define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
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#define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
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#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT)
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#define MTK_ESW BIT_ULL(MTK_ESW_BIT)
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#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
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#define MTK_MUX BIT_ULL(MTK_MUX_BIT)
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@ -1010,6 +1034,8 @@ enum mkt_eth_capabilities {
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BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
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#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
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BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
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#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \
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BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
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#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
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BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
|
||||
#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
|
||||
|
|
@ -1021,6 +1047,7 @@ enum mkt_eth_capabilities {
|
|||
#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
|
||||
#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
|
||||
#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
|
||||
#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT)
|
||||
#define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
|
||||
#define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
|
||||
|
||||
|
|
@ -1030,6 +1057,7 @@ enum mkt_eth_capabilities {
|
|||
#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
|
||||
#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
|
||||
#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
|
||||
#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
|
||||
#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
|
||||
|
||||
/* MUXes present on SoCs */
|
||||
|
|
@ -1049,6 +1077,10 @@ enum mkt_eth_capabilities {
|
|||
(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
|
||||
MTK_SHARED_SGMII)
|
||||
|
||||
/* 2: GMAC2 -> 2P5GPHY */
|
||||
#define MTK_MUX_GMAC2_TO_2P5GPHY \
|
||||
(MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA)
|
||||
|
||||
/* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
|
||||
#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
|
||||
(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
|
||||
|
|
@ -1084,8 +1116,9 @@ enum mkt_eth_capabilities {
|
|||
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
|
||||
MTK_RSTCTRL_PPE1 | MTK_SRAM)
|
||||
|
||||
#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \
|
||||
MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
|
||||
#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC2_2P5GPHY | \
|
||||
MTK_MUX_GMAC2_TO_2P5GPHY | MTK_QDMA | MTK_RSTCTRL_PPE1 | \
|
||||
MTK_RSTCTRL_PPE2 | MTK_SRAM)
|
||||
|
||||
struct mtk_tx_dma_desc_info {
|
||||
dma_addr_t addr;
|
||||
|
|
@ -1437,6 +1470,23 @@ static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth)
|
|||
return MTK_FOE_IB2_MULTICAST;
|
||||
}
|
||||
|
||||
static inline bool mtk_interface_mode_is_xgmii(struct mtk_eth *eth,
|
||||
phy_interface_t interface)
|
||||
{
|
||||
if (!mtk_is_netsys_v3_or_greater(eth))
|
||||
return false;
|
||||
|
||||
switch (interface) {
|
||||
case PHY_INTERFACE_MODE_INTERNAL:
|
||||
case PHY_INTERFACE_MODE_USXGMII:
|
||||
case PHY_INTERFACE_MODE_10GBASER:
|
||||
case PHY_INTERFACE_MODE_5GBASER:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
/* read the hardware status register */
|
||||
void mtk_stats_update_mac(struct mtk_mac *mac);
|
||||
|
||||
|
|
@ -1445,6 +1495,7 @@ u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
|
|||
u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
|
||||
|
||||
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
|
||||
int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id);
|
||||
int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
|
||||
int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user