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KVM: nVMX: Switch to vmcs01 to update TPR threshold on-demand if L2 is active
If KVM updates L1's TPR Threshold while L2 is active, temporarily load vmcs01 and immediately update TPR_THRESHOLD instead of deferring the update until the next nested VM-Exit. Deferring the TPR Threshold update is relatively straightforward, but for several APICv related updates, deferring updates creates ordering and state consistency problems, e.g. KVM at-large thinks APICv is enabled, but vmcs01 is still running with stale (and effectively unknown) state. Reviewed-by: Chao Gao <chao.gao@intel.com> Link: https://patch.msgid.link/20260109034532.1012993-4-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
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@ -2402,7 +2402,6 @@ static void prepare_vmcs02_early(struct vcpu_vmx *vmx, struct loaded_vmcs *vmcs0
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exec_control &= ~CPU_BASED_TPR_SHADOW;
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exec_control |= vmcs12->cpu_based_vm_exec_control;
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vmx->nested.l1_tpr_threshold = -1;
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if (exec_control & CPU_BASED_TPR_SHADOW)
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vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
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#ifdef CONFIG_X86_64
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@ -5123,9 +5122,6 @@ void __nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 vm_exit_reason,
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if (kvm_caps.has_tsc_control)
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vmcs_write64(TSC_MULTIPLIER, vcpu->arch.tsc_scaling_ratio);
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if (vmx->nested.l1_tpr_threshold != -1)
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vmcs_write32(TPR_THRESHOLD, vmx->nested.l1_tpr_threshold);
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if (vmx->nested.change_vmcs01_virtual_apic_mode) {
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vmx->nested.change_vmcs01_virtual_apic_mode = false;
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vmx_set_virtual_apic_mode(vcpu);
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@ -6836,11 +6836,10 @@ void vmx_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
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nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
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return;
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guard(vmx_vmcs01)(vcpu);
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tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr;
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if (is_guest_mode(vcpu))
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to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold;
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else
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vmcs_write32(TPR_THRESHOLD, tpr_threshold);
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vmcs_write32(TPR_THRESHOLD, tpr_threshold);
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}
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void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
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@ -184,9 +184,6 @@ struct nested_vmx {
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u64 pre_vmenter_ssp;
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u64 pre_vmenter_ssp_tbl;
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/* to migrate it to L1 if L2 writes to L1's CR8 directly */
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int l1_tpr_threshold;
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u16 vpid02;
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u16 last_vpid;
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