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drm/xe/irq: Clear GFX_MSTR_IRQ as part of IRQ reset

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Starting with Xe_LP+, GFX_MSTR_IRQ contains status bits that have W1C
behavior. If we do not properly reset them, we would miss delivery of
interrupts if a pending bit is set when enabling IRQs.

As an example, the display part of our probe routine contains paths
where we wait for vblank interrupts. If a display interrupt was already
pending when enabling IRQs, we would time out waiting for the vblank.

That in fact happened recently when modprobing Xe on a Lunar Lake with a
specific configuration; and that's how we found out we were missing this
step in the IRQ enabling logic.

Fix the issue by clearing GFX_MSTR_IRQ as part of the IRQ reset.

v2:
  - Make resetting GFX_MSTR_IRQ be the last step to avoid bit
    re-latching. (Ville)
v3:
  - Swap nesting order: guard loop with the IP version check instead of
    doing the check at each iteration. (Lucas)
v4:
  - Add braces for the "if" statement guarding the loop to make the
    compiler happy. (Gustavo)

BSpec: 50875, 54028, 62357
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230926221914.106843-2-gustavo.sousa@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Gustavo Sousa 2023-09-26 19:19:15 -03:00 committed by Rodrigo Vivi
parent 5fdd4b21ae
commit 51a5d65609
1 changed files with 17 additions and 0 deletions
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17
drivers/gpu/drm/xe/xe_irq.c
View File

@ -511,6 +511,13 @@ static void dg1_irq_reset(struct xe_tile *tile)
mask_and_disable(tile, PCU_IRQ_OFFSET);
}
static void dg1_irq_reset_mstr(struct xe_tile *tile)
{
struct xe_gt *mmio = tile->primary_gt;
xe_mmio_write32(mmio, GFX_MSTR_IRQ, ~0);
}
static void xe_irq_reset(struct xe_device *xe)
{
struct xe_tile *tile;
@ -525,6 +532,16 @@ static void xe_irq_reset(struct xe_device *xe)
tile = xe_device_get_root_tile(xe);
mask_and_disable(tile, GU_MISC_IRQ_OFFSET);
/*
* The tile's top-level status register should be the last one
* to be reset to avoid possible bit re-latching from lower
* level interrupts.
*/
if (GRAPHICS_VERx100(xe) >= 1210) {
for_each_tile(tile, xe, id)
dg1_irq_reset_mstr(tile);
}
}
static void xe_irq_postinstall(struct xe_device *xe)