From 9b181f4a95389163b3a6ec1dccc5c25038e16958 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Mon, 2 Dec 2024 19:20:02 +0000 Subject: [PATCH 1/6] riscv: dts: microchip: update pcie reg properties to new format The existing PolarFire SoC devicetrees all use root port instance 1, update the reg properties in PCIe nodes to use the new format that specifies the instance in use. Failing to do so would still work but produces warnings: mpfs-icicle-kit.dtb: pcie@3000000000: reg: [[48, 0, 0, 134217728], [0, 1124073472, 0, 65536]] is too short mpfs-icicle-kit.dtb: pcie@3000000000: reg-names: ['cfg', 'apb'] is too short Signed-off-by: Conor Dooley --- CC: Conor Dooley CC: Daire McNamara CC: valentina.fernandezalanis@microchip.com CC: Rob Herring CC: Krzysztof Kozlowski CC: linux-riscv@lists.infradead.org CC: devicetree@vger.kernel.org CC: linux-kernel@vger.kernel.org --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 5 +++-- arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi | 5 +++-- arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi | 5 +++-- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 1069134f2e12..a6dda55a2d1d 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -32,8 +32,9 @@ pcie: pcie@3000000000 { #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; + reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>, + <0x0 0x4300a000 0x0 0x2000>; + reg-names = "cfg", "bridge", "ctrl"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; interrupts = <119>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi index 8230f06ddf48..36a9860f31da 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi @@ -20,8 +20,9 @@ pcie: pcie@2000000000 { #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>, + <0x0 0x4300a000 0x0 0x2000>; + reg-names = "cfg", "bridge", "ctrl"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; interrupts = <119>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi index 9a56de7b91d6..a57dca891965 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -20,8 +20,9 @@ pcie: pcie@2000000000 { #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>, + <0x0 0x4300a000 0x0 0x2000>; + reg-names = "cfg", "bridge", "ctrl"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; interrupts = <119>; From 3d20e619c9c0601e147925e86086108c8e03c6ea Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Thu, 6 Feb 2025 01:16:35 +0800 Subject: [PATCH 2/6] riscv: dts: starfive: Unify regulator naming scheme Currently, there are 3 regulators defined in JH7110's common device tree, but regulator names are mixed with "-" and "_". So unify them to "_", which is more often to be seen in other dts files. Signed-off-by: Shengyu Qu Acked-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index 48fb5091b817..dd2eefc295e5 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -233,7 +233,7 @@ vdd_cpu: dcdc2 { regulator-always-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1540000>; - regulator-name = "vdd-cpu"; + regulator-name = "vdd_cpu"; }; emmc_vdd: aldo4 { From 4bdea6e33946d481d54f6903b716101dd75b884e Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Thu, 13 Feb 2025 20:03:52 +0000 Subject: [PATCH 3/6] riscv: dts: starfive: remove non-existent dac from jh7110 The jh7110 boards do not have a Rohm DAC on them as far as I can tell, and they certainly do not have a dh2228fv, as this device does not actually exist! Remove the dac nodes from the devicetrees as it is not acceptable to pretend to have a device on a board in order to bind the spidev driver in Linux. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index dd2eefc295e5..c2f70f5e2918 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -350,12 +350,6 @@ &pwm { &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - - spi_dev0: spi@0 { - compatible = "rohm,dh2228fv"; - reg = <0>; - spi-max-frequency = <10000000>; - }; }; &syscrg { From 57b5369f36686961bebddc98d894d095d0b402a8 Mon Sep 17 00:00:00 2001 From: Sandie Cao Date: Fri, 7 Feb 2025 17:36:18 +0800 Subject: [PATCH 4/6] riscv: dts: starfive: fml13v01: enable pcie1 Starfive Soc common defines GPIO28 as pcie1 reset, GPIO21 as pcie1 wakeup; But the FML13V01 board uses GPIO21 as pcie1 reset, GPIO28 as pcie1 wakeup; redefine pcie1 gpio and enable pcie1 for pcie based Wi-Fi. Signed-off-by: Sandie Cao Tested-by: Maud Spierings Signed-off-by: Conor Dooley --- .../jh7110-deepcomputing-fml13v01.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts index 30b0715196b6..8d9ce8b69a71 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts @@ -11,6 +11,40 @@ / { compatible = "deepcomputing,fml13v01", "starfive,jh7110"; }; +&pcie1 { + perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>; + phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&sysgpio { + pcie1_pins: pcie1-0 { + clkreq-pins { + pinmux = ; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = ; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; +}; + &usb0 { dr_mode = "host"; status = "okay"; From 65e8b991267093b759a03c20508d2643a41aa046 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Thu, 2 Jan 2025 10:37:36 -0800 Subject: [PATCH 5/6] riscv: dts: starfive: jh7110: pciephy0 USB 3.0 configuration registers StarFive JH7110 contains a Cadence USB2.0+USB3.0 controller IP block that may exclusively use pciephy0 for USB3.0 connectivity. Add the register offsets for the driver to enable/disable USB3.0 on pciephy0. Signed-off-by: E Shattow Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 0d8339357bad..75ff07303e8b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -611,6 +611,8 @@ usbphy0: phy@10200000 { pciephy0: phy@10210000 { compatible = "starfive,jh7110-pcie-phy"; reg = <0x0 0x10210000 0x0 0x10000>; + starfive,sys-syscon = <&sys_syscon 0x18>; + starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>; #phy-cells = <0>; }; From 38818f7c9c179351334b1faffc4d40bd28cc9c72 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Thu, 2 Jan 2025 10:37:37 -0800 Subject: [PATCH 6/6] riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port One of four USB-A ports on the Pine64 Star64 is USB 3.0 which requires to disable PCIE0 and change the mode of PCIE0 PHY to USB3.0 operation. The remaining three USB-A ports are USB 2.0 with the USB0 PHY and do not conflict with any of PCIE0 or PCIE1. PCIE1 (1-lane) routes to a PCIe X4 connector. Signed-off-by: E Shattow Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts index b764d4d92fd9..31e825be2065 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts @@ -100,3 +100,8 @@ &usb0 { pinctrl-0 = <&usb0_pins>; status = "okay"; }; + +&usb_cdns3 { + phys = <&usbphy0>, <&pciephy0>; + phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy"; +};