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New peripherals: Watchdog on RK3528, MIPI CSI-2 receiver on RK3588.

Browse Source 
Adding frl-enable-gpios to a number of boards for HDMI 2.0 support.
 And a bunch of fixes and new peripherals for a number of boards.
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Merge tag 'v7.2-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

New peripherals: Watchdog on RK3528, MIPI CSI-2 receiver on RK3588.
Adding frl-enable-gpios to a number of boards for HDMI 2.0 support.
And a bunch of fixes and new peripherals for a number of boards.

* tag 'v7.2-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (30 commits)
  arm64: dts: rockchip: Add watchdog node for RK3528
  arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3588
  arm64: dts: rockchip: fix rk809 interrupt pin on rk3566-roc-pc
  arm64: dts: rockchip: Add missing pinctrl-names to rk3588s boards
  arm64: dts: rockchip: Add missing pinctrl-names to rk3588 boards
  arm64: dts: rockchip: Add missing pinctrl-names to rk3576 boards
  arm64: dts: rockchip: Drop unnecessary #{address,size}-cells from rk3588-jaguar
  arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-roc-pc
  arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-orangepi-cm5-base
  arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-khadas-edge2
  arm64: dts: rockchip: Add frl-enable-gpios to rk3588s-gameforce-ace
  arm64: dts: rockchip: Add frl-enable-gpios to rk3588s boards
  arm64: dts: rockchip: Add frl-enable-gpios to rk3588 boards
  arm64: dts: rockchip: Add frl-enable-gpios to rk3576-nanopi-r76s
  arm64: dts: rockchip: Add frl-enable-gpios to rk3576-luckfox-core3576
  arm64: dts: rockchip: Add frl-enable-gpios to rk3576 boards
  arm64: dts: rockchip: Add AP6275P wireless support for Khadas Edge 2L
  arm64: dts: rockchip: Add HYM8563 RTC for Khadas Edge 2L
  arm64: dts: rockchip: Add #{address,size}-cells to Chromium-based /firmware
  arm64: dts: rockchip: Add HDMI and VOP support for Khadas Edge 2L
  ...

Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Linus Walleij 2026-06-02 13:27:47 +02:00
commit 513edb1496
62 changed files with 1190 additions and 89 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MAINTAINERS
View File

@ -3425,6 +3425,8 @@ F: drivers/i2c/busses/i2c-rk3x.c
F: drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
F: sound/soc/rockchip/
N: rockchip
K: \b[Rr]ock[Cc]hip\b
K: (?:\b|_)ROCKCHIP(?:\b|_)
ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES
M: Krzysztof Kozlowski <krzk@kernel.org>

2
arch/arm64/boot/dts/rockchip/px30-cobra.dtsi
View File

@ -397,7 +397,7 @@ &io_domains {
&mdio {
dp83825: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id2000.a140";
reg = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&phy_rst>;

2
arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
View File

@ -344,7 +344,7 @@ &io_domains {
&mdio {
dp83825: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id2000.a140";
reg = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&phy_rst>;

5
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
View File

@ -18,6 +18,11 @@ chosen {
stdout-path = "serial2:115200n8";
};
firmware {
#address-cells = <2>;
#size-cells = <2>;
};
/*
* Power Tree
*

8
arch/arm64/boot/dts/rockchip/rk3528.dtsi
View File

@ -983,6 +983,14 @@ pwm7: pwm@ffa98030 {
status = "disabled";
};
wdt: watchdog@ffac0000 {
compatible = "rockchip,rk3528-wdt", "snps,dw-wdt";
reg = <0x0 0xffac0000 0x0 0x100>;
clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
clock-names = "tclk", "pclk";
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
};
saradc: adc@ffae0000 {
compatible = "rockchip,rk3528-saradc";
reg = <0x0 0xffae0000 0x0 0x10000>;

2
arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
View File

@ -245,7 +245,7 @@ rk809: pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
clock-output-names = "rk808-clkout1", "rk808-clkout2";
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;

6
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
View File

@ -98,7 +98,7 @@ &mdio0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-0 = <&gmac0_rstn_gpio0_c5_pin>;
pinctrl-names = "default";
};
};
@ -132,8 +132,8 @@ &pcie3x2 {
&pinctrl {
gmac0 {
eth_phy0_reset_pin: eth-phy0-reset-pin {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
gmac0_rstn_gpio0_c5_pin: gmac0-rstn-gpio0-c5-pin {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};

20
arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
View File

@ -56,7 +56,15 @@ led-0 {
};
};
/* pi6c pcie clock generator */
/* PI6C20100 PCIe reference clock buffer */
pcie30_refclk: pcie-clock-generator {
compatible = "gated-fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "pcie30_refclk";
vdd-supply = <&vcc3v3_pi6c_03>;
};
vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
compatible = "regulator-fixed";
enable-active-high;
@ -64,8 +72,6 @@ vcc3v3_pi6c_03: regulator-3v3-vcc-pi6c-03 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pwren_h>;
regulator-name = "vcc3v3_pi6c_03";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <10000>;
@ -553,6 +559,14 @@ &pcie30phy {
};
&pcie3x2 {
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
<&cru CLK_PCIE30X2_AUX_NDFT>,
<&cru CLK_PCIE30X2_PIPE_DFT>,
<&pcie30_refclk>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux",
"pipe", "ref";
pinctrl-names = "default";
pinctrl-0 = <&pcie30x2m1_pins>;
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;

10
arch/arm64/boot/dts/rockchip/rk3576-100ask-dshanpi-a1.dts
View File

@ -278,6 +278,9 @@ &gpu {
};
&hdmi {
frl-enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -738,6 +741,12 @@ hp_det: hp-det {
};
};
hdmi {
hdmi_tx_on_h: hdmi-tx-on-h {
rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie {
pcie_reset: pcie-reset {
rockchip,pins = <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
@ -806,6 +815,7 @@ &u2phy1_otg {
&uart0 {
pinctrl-0 = <&uart0m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

10
arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts
View File

@ -304,6 +304,9 @@ &gpu {
};
&hdmi {
frl-enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -819,6 +822,12 @@ hp_det_l: hp-det-l {
};
};
hdmi {
hdmi_tx_on_h: hdmi-tx-on-h {
rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
@ -966,6 +975,7 @@ &u2phy1_otg {
&uart0 {
pinctrl-0 = <&uart0m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

9
arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts
View File

@ -370,6 +370,9 @@ &gpu {
};
&hdmi {
frl-enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -895,6 +898,12 @@ host_wake_bt: host-wake-bt {
};
};
hdmi {
hdmi_tx_on_h: hdmi-tx-on-h {
rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
rtc_int: rtc-int {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;

9
arch/arm64/boot/dts/rockchip/rk3576-evb2-v10.dts
View File

@ -375,6 +375,9 @@ &gpu {
};
&hdmi {
frl-enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -832,6 +835,12 @@ image_pwren: image-pwren {
};
};
hdmi {
hdmi_tx_on_h: hdmi-tx-on-h {
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
rtc_int: rtc-int {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;

538
arch/arm64/boot/dts/rockchip/rk3576-khadas-edge-2l.dts
View File

@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3576.dtsi"
/ {
@ -17,6 +18,528 @@ aliases {
chosen {
stdout-path = "serial0:1500000n8";
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
vcc_sys: regulator-vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v1_nldo_s3";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&vcc_sys>;
};
vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_2v0_pldo_s3";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
vin-supply = <&vcc_sys>;
};
vcc_wifi_reg_on: regulator-wifi-reg-on {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&wifi_reg_on>;
pinctrl-names = "default";
regulator-name = "wifi_reg_on";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc_1v8_s3>;
};
};
&combphy0_ps {
status = "okay";
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_b0 {
cpu-supply = <&vdd_cpu_big_s0>;
};
&gpu {
mali-supply = <&vdd_gpu_s0>;
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_in {
hdmi_in_vp0: endpoint {
remote-endpoint = <&vp0_out_hdmi>;
};
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&hdmi_sound {
status = "okay";
};
&hdptxphy {
status = "okay";
};
&i2c1 {
status = "okay";
rk806: pmic@23 {
compatible = "rockchip,rk806";
reg = <0x23>;
interrupt-parent = <&gpio0>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
system-power-controller;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
vcc7-supply = <&vcc_sys>;
vcc8-supply = <&vcc_sys>;
vcc9-supply = <&vcc_sys>;
vcc10-supply = <&vcc_sys>;
vcc11-supply = <&vcc_2v0_pldo_s3>;
vcc12-supply = <&vcc_sys>;
vcc13-supply = <&vcc_1v1_nldo_s3>;
vcc14-supply = <&vcc_1v1_nldo_s3>;
vcca-supply = <&vcc_sys>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun0";
};
rk806_dvs2_null: dvs2-null-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun0";
};
rk806_dvs3_null: dvs3-null-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun0";
};
rk806_dvs1_slp: dvs1-slp-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun1";
};
rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun2";
};
rk806_dvs1_rst: dvs1-rst-pins {
pins = "gpio_pwrctrl1";
function = "pin_fun3";
};
rk806_dvs2_slp: dvs2-slp-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun1";
};
rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun2";
};
rk806_dvs2_rst: dvs2-rst-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun3";
};
rk806_dvs2_dvs: dvs2-dvs-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun4";
};
rk806_dvs2_gpio: dvs2-gpio-pins {
pins = "gpio_pwrctrl2";
function = "pin_fun5";
};
rk806_dvs3_slp: dvs3-slp-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun1";
};
rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun2";
};
rk806_dvs3_rst: dvs3-rst-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun3";
};
rk806_dvs3_dvs: dvs3-dvs-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun4";
};
rk806_dvs3_gpio: dvs3-gpio-pins {
pins = "gpio_pwrctrl3";
function = "pin_fun5";
};
regulators {
vdd_cpu_big_s0: dcdc-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_big_s0";
regulator-enable-ramp-delay = <400>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_npu_s0: dcdc-reg2 {
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_npu_s0";
regulator-enable-ramp-delay = <400>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_lit_s0: dcdc-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_cpu_lit_s0";
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vcc_3v3_s3: dcdc-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_3v3_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd_gpu_s0: dcdc-reg5 {
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <900000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_gpu_s0";
regulator-enable-ramp-delay = <400>;
regulator-state-mem {
regulator-off-in-suspend;
regulator-suspend-microvolt = <850000>;
};
};
vddq_ddr_s0: dcdc-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vddq_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_logic_s0: dcdc-reg7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <800000>;
regulator-name = "vdd_logic_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_1v8_s3: dcdc-reg8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_1v8_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd2_ddr_s3: dcdc-reg9 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd2_ddr_s3";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vdd_ddr_s0: dcdc-reg10 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vdd_ddr_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca_1v8_s0: pldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca_1v8_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pldo2_s0: pldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_pldo2_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_1v2_s0: pldo-reg3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vdda_1v2_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca_3v3_s0: pldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcca_3v3_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vccio_sd_s0: pldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcca1v8_pldo6_s3: pldo-reg6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcca1v8_pldo6_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_0v75_s3: nldo-reg1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdd_0v75_s3";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <750000>;
};
};
vdda_ddr_pll_s0: nldo-reg2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdda_ddr_pll_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda0v75_hdmi_s0: nldo-reg3 {
regulator-boot-on;
regulator-min-microvolt = <837500>;
regulator-max-microvolt = <837500>;
regulator-name = "vdda0v75_hdmi_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v85_s0: nldo-reg4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-name = "vdda_0v85_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdda_0v75_s0: nldo-reg5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
regulator-name = "vdda_0v75_s0";
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&i2c2 {
status = "okay";
hym8563: rtc@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-output-names = "hym8563";
wakeup-source;
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_rst>;
reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_s3>;
status = "okay";
pcie@0,0 {
reg = <0x0 0 0 0 0>;
bus-range = <0x0 0xf>;
device_type = "pci";
ranges;
#address-cells = <3>;
#size-cells = <2>;
wifi: wifi@0,0 {
compatible = "pci14e4,449d";
reg = <0x10000 0 0 0 0>;
clocks = <&hym8563>;
clock-names = "lpo";
};
};
};
&pinctrl {
pcie0 {
pcie0_rst: pcie0-rst {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wifi {
wifi_reg_on: wifi-reg-on {
rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
wifi_wake_host: wifi-wake-host {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&sdhci {
@ -32,3 +555,18 @@ &sdhci {
&uart0 {
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vp0 {
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
remote-endpoint = <&hdmi_in_vp0>;
};
};

22
arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi
View File

@ -26,7 +26,6 @@ chosen {
hdmi-con {
compatible = "hdmi-connector";
hdmi-pwr-supply = <&vcc_5v0_hdmi>;
type = "a";
port {
@ -138,22 +137,6 @@ regulator-state-mem {
};
};
vcc_5v0_hdmi: regulator-vcc-5v0-hdmi {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_con_en>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vcc_5v0_hdmi";
vin-supply = <&vcc_5v0_sys>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc_5v0_host: regulator-vcc-5v0-host {
compatible = "regulator-fixed";
enable-active-high;
@ -231,6 +214,9 @@ &gpu {
};
&hdmi {
frl-enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -655,7 +641,7 @@ &pcie0 {
&pinctrl {
hdmi {
hdmi_con_en: hdmi-con-en {
hdmi_tx_on_h: hdmi-tx-on-h {
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};

9
arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts
View File

@ -327,6 +327,9 @@ &gpu {
};
&hdmi {
frl-enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -813,6 +816,12 @@ gmac1_rst: gmac1-rst {
};
};
hdmi {
hdmi_tx_on_h: hdmi-tx-on-h {
rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;

16
arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
View File

@ -70,7 +70,6 @@ led-2 {
hdmi-con {
compatible = "hdmi-connector";
hdmi-pwr-supply = <&vcc5v_hdmi_tx>;
type = "a";
port {
@ -109,18 +108,6 @@ vcc5v_dcin: regulator-vcc5v-dcin {
regulator-name = "vcc5v_dcin";
};
vcc5v_hdmi_tx: regulator-vcc5v-hdmi-tx {
compatible = "regulator-fixed";
enable-active-high;
gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_tx_on_h>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "vcc5v_hdmi_tx";
vin-supply = <&vcc5v0_sys_s5>;
};
vcc5v0_device_s0: regulator-vcc5v0-device-s0 {
compatible = "regulator-fixed";
regulator-always-on;
@ -252,6 +239,9 @@ &gpu {
};
&hdmi {
frl-enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};

10
arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts
View File

@ -283,6 +283,9 @@ &eth0m0_rgmii_bus
};
&hdmi {
frl-enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -720,6 +723,12 @@ &sdmmc {
};
&pinctrl {
hdmi {
hdmi_tx_on_h: hdmi-tx-on-h {
rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
rtc_int_l: rtc-int-l {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
@ -767,6 +776,7 @@ wd_en: wd-en {
&uart0 {
pinctrl-0 = <&uart0m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

10
arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
View File

@ -289,6 +289,9 @@ &gpu {
};
&hdmi {
frl-enable-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda &hdmi_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -720,6 +723,12 @@ &pcie0 {
};
&pinctrl {
hdmi {
hdmi_tx_on_h: hdmi-tx-on-h {
rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
@ -824,6 +833,7 @@ &u2phy1_otg {
&uart0 {
pinctrl-0 = <&uart0m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

6
arch/arm64/boot/dts/rockchip/rk3576.dtsi
View File

@ -1281,10 +1281,10 @@ gpu: gpu@27800000 {
vdec: video-codec@27b00000 {
compatible = "rockchip,rk3576-vdec";
reg = <0x0 0x27b00100 0x0 0x500>,
<0x0 0x27b00000 0x0 0x100>,
reg = <0x0 0x27b00000 0x0 0x100>,
<0x0 0x27b00100 0x0 0x500>,
<0x0 0x27b00600 0x0 0x100>;
reg-names = "function", "link", "cache";
reg-names = "link", "function", "cache";
interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>,
<&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>,

11
arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
View File

@ -177,6 +177,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -347,6 +351,12 @@ &pd_gpu {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
@ -778,6 +788,7 @@ &u2phy3_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

19
arch/arm64/boot/dts/rockchip/rk3588-armsom-w3.dts
View File

@ -162,6 +162,10 @@ &combphy2_psu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -182,6 +186,10 @@ &hdmi0_sound {
};
&hdmi1 {
frl-enable-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
&hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -330,6 +338,16 @@ &pcie3x4 {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdmi1_tx_on_h: hdmi1-tx-on-h {
rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
@ -421,6 +439,7 @@ &sdio {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

64
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
View File

@ -1355,10 +1355,10 @@ vepu121_3_mmu: iommu@fdbac800 {
vdec0: video-codec@fdc38000 {
compatible = "rockchip,rk3588-vdec";
reg = <0x0 0xfdc38100 0x0 0x500>,
<0x0 0xfdc38000 0x0 0x100>,
reg = <0x0 0xfdc38000 0x0 0x100>,
<0x0 0xfdc38100 0x0 0x500>,
<0x0 0xfdc38600 0x0 0x100>;
reg-names = "function", "link", "cache";
reg-names = "link", "function", "cache";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>,
<&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>;
@ -1387,10 +1387,10 @@ vdec0_mmu: iommu@fdc38700 {
vdec1: video-codec@fdc40000 {
compatible = "rockchip,rk3588-vdec";
reg = <0x0 0xfdc40100 0x0 0x500>,
<0x0 0xfdc40000 0x0 0x100>,
reg = <0x0 0xfdc40000 0x0 0x100>,
<0x0 0xfdc40100 0x0 0x500>,
<0x0 0xfdc40600 0x0 0x100>;
reg-names = "function", "link", "cache";
reg-names = "link", "function", "cache";
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>,
<&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>;
@ -1430,6 +1430,58 @@ av1d: video-codec@fdc70000 {
resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
};
csi2: csi@fdd30000 {
compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2";
reg = <0x0 0xfdd30000 0x0 0x10000>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "err1", "err2";
clocks = <&cru PCLK_CSI_HOST_2>;
phys = <&csi_dphy0>;
power-domains = <&power RK3588_PD_VI>;
resets = <&cru SRST_P_CSI_HOST_2>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
csi2_in: port@0 {
reg = <0>;
};
csi2_out: port@1 {
reg = <1>;
};
};
};
csi4: csi@fdd50000 {
compatible = "rockchip,rk3588-mipi-csi2", "rockchip,rk3568-mipi-csi2";
reg = <0x0 0xfdd50000 0x0 0x10000>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "err1", "err2";
clocks = <&cru PCLK_CSI_HOST_4>;
phys = <&csi_dphy1>;
power-domains = <&power RK3588_PD_VI>;
resets = <&cru SRST_P_CSI_HOST_4>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
csi4_in: port@0 {
reg = <0>;
};
csi4_out: port@1 {
reg = <1>;
};
};
};
vop: vop@fdd90000 {
compatible = "rockchip,rk3588-vop";
reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;

18
arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts
View File

@ -125,6 +125,10 @@ vcc5v0_usb30_otg: regulator-vcc5v0-usb30-otg {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -145,8 +149,10 @@ hdmi0_out_con: endpoint {
};
&hdmi1 {
frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda
&hdmi1_tx_on_h>;
pinctrl-names = "default";
pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>;
status = "okay";
};
@ -211,6 +217,16 @@ &pcie3x4 {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdmi1_tx_on_h: hdmi1-tx-on-h {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd {
lcdpwr_en: lcdpwr-en {
rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;

12
arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-genbook.dts
View File

@ -184,7 +184,10 @@ edp_out_panel: endpoint {
/* HDMI CEC is not used */
&hdmi0 {
pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>;
frl-enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda
&hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -277,6 +280,12 @@ &pcie3x4 {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd {
lcdpwr_en: lcdpwr-en {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
@ -326,6 +335,7 @@ pcie_wake: pcie-wake {
&pwm6 {
pinctrl-0 = <&pwm6m1_pins>;
pinctrl-names = "default";
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi
View File

@ -143,6 +143,7 @@ &gpu {
&i2c0 {
pinctrl-0 = <&i2c0m2_xfer>;
pinctrl-names = "default";
status = "okay";
vdd_cpu_big0_s0: regulator@42 {
@ -219,6 +220,7 @@ hym8563: rtc@51 {
&i2c7 {
pinctrl-0 = <&i2c7m0_xfer>;
pinctrl-names = "default";
status = "okay";
es8316: audio-codec@10 {
@ -244,6 +246,7 @@ &i2s0_mclk
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
pinctrl-names = "default";
status = "okay";
i2s0_8ch_p0: port {
@ -656,5 +659,6 @@ &tsadc {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

1
arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi
View File

@ -252,6 +252,7 @@ &sdmmc {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

20
arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
View File

@ -360,6 +360,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -376,6 +380,10 @@ hdmi0_out_con: endpoint {
};
&hdmi1 {
frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
&hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -502,6 +510,7 @@ &i2s0_mclk
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
pinctrl-names = "default";
status = "okay";
};
@ -612,6 +621,16 @@ rtl8211f_rst: rtl8211f-rst {
};
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdmi1_tx_on_h: hdmi1-tx-on-h {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdmirx {
hdmirx_hpd: hdmirx-5v-detection {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
@ -1368,6 +1387,7 @@ &u2phy3_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

11
arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
View File

@ -143,6 +143,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -183,6 +187,12 @@ &pd_gpu {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
@ -911,6 +921,7 @@ &u2phy3_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

1
arch/arm64/boot/dts/rockchip/rk3588-fet3588-c.dtsi
View File

@ -558,5 +558,6 @@ &tsadc {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

1
arch/arm64/boot/dts/rockchip/rk3588-firefly-core-3588j.dtsi
View File

@ -443,5 +443,6 @@ regulator-state-mem {
/* rk3588 preferred debug out */
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

1
arch/arm64/boot/dts/rockchip/rk3588-firefly-icore-3588q.dtsi
View File

@ -439,5 +439,6 @@ regulator-state-mem {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

12
arch/arm64/boot/dts/rockchip/rk3588-firefly-itx-3588j.dts
View File

@ -322,6 +322,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -487,6 +491,12 @@ dp1_hpd: dp1-hpd {
};
};
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
@ -558,11 +568,13 @@ &sata2 {
/* uart/232/485 */
&uart0 {
pinctrl-0 = <&uart0m2_xfer>;
pinctrl-names = "default";
status = "okay";
};
&uart1 {
pinctrl-0 = <&uart1m1_xfer>;
pinctrl-names = "default";
status = "okay";
};

18
arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts
View File

@ -331,6 +331,10 @@ &gpio4 {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -347,6 +351,10 @@ hdmi0_out_con: endpoint {
};
&hdmi1 {
frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
&hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -520,6 +528,16 @@ key1_pin: key1-pin {
};
};
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdmi1_tx_on_h: hdmi1-tx-on-h {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdmirx {
hdmirx_hpd: hdmirx-5v-detection {
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;

11
arch/arm64/boot/dts/rockchip/rk3588-h96-max-v58.dts
View File

@ -210,6 +210,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -339,6 +343,12 @@ &pd_gpu {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
@ -774,6 +784,7 @@ &u2phy1_otg {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

24
arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts
View File

@ -278,8 +278,10 @@ &gpu {
&hdmi0 {
/* No CEC on Jaguar */
frl-enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda
&hdmi0_tx_on_h>;
pinctrl-names = "default";
pinctrl-0 = <&hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>;
status = "okay";
};
@ -305,6 +307,7 @@ &hdptxphy0 {
&i2c0 {
pinctrl-0 = <&i2c0m2_xfer>;
pinctrl-names = "default";
status = "okay";
fan@18 {
@ -415,10 +418,12 @@ regulator-state-mem {
&i2c1 {
pinctrl-0 = <&i2c1m4_xfer>;
pinctrl-names = "default";
};
&i2c6 {
pinctrl-0 = <&i2c6m4_xfer>;
pinctrl-names = "default";
};
&i2c7 {
@ -437,6 +442,7 @@ eeprom@54 {
&i2c8 {
pinctrl-0 = <&i2c8m2_xfer>;
pinctrl-names = "default";
status = "okay";
typec-portc@22 {
@ -571,6 +577,12 @@ eth_reset: eth-reset {
};
};
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
led1_pin: led1-pin {
rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
@ -1046,18 +1058,21 @@ &u2phy3_host {
/* Mule-ATtiny debug UART; typically baudrate 9600 */
&uart0 {
pinctrl-0 = <&uart0m0_xfer>;
pinctrl-names = "default";
status = "okay";
};
/* Main debug interface on P20 micro-USB B port and P21 header */
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};
/* RS485 on P19 */
&uart3 {
pinctrl-0 = <&uart3m2_xfer &uart3_rtsn>;
pinctrl-names = "default";
linux,rs485-enabled-at-boot-time;
status = "okay";
};
@ -1065,6 +1080,7 @@ &uart3 {
/* Mule-ATtiny UPDI flashing UART */
&uart7 {
pinctrl-0 = <&uart7m0_xfer>;
pinctrl-names = "default";
status = "okay";
};
@ -1134,9 +1150,6 @@ &usb_host0_xhci {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
usb_host0_xhci_drd_sw: endpoint {
remote-endpoint = <&usbc0_hs>;
};
@ -1149,9 +1162,6 @@ &usb_host1_xhci {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
usb_host1_xhci_drd_sw: endpoint {
remote-endpoint = <&usbc1_hs>;
};

12
arch/arm64/boot/dts/rockchip/rk3588-mnt-reform2.dts
View File

@ -148,6 +148,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -181,6 +185,7 @@ rgmii_phy: ethernet-phy@0 {
&pcie2x1l2 {
pinctrl-0 = <&pcie2_0_rst>;
pinctrl-names = "default";
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@ -205,6 +210,12 @@ dp1_hpd: dp1-hpd {
};
};
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
pcie2 {
pcie2_0_rst: pcie2-0-rst {
rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
@ -226,6 +237,7 @@ eth_phy_reset: eth-phy-reset {
&pwm8 {
pinctrl-0 = <&pwm8m2_pins>;
pinctrl-names = "default";
status = "okay";
};

21
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
View File

@ -361,6 +361,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -381,6 +385,10 @@ &hdmi0_sound {
};
&hdmi1 {
frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
&hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -571,6 +579,7 @@ rt5616_p0_0: endpoint {
&i2c8 {
pinctrl-0 = <&i2c8m2_xfer>;
pinctrl-names = "default";
};
&i2s0_8ch {
@ -682,6 +691,16 @@ usr_led_pin: usr-led-pin {
};
};
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdmi1_tx_on_h: hdmi1-tx-on-h {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdmirx {
hdmirx_hpd: hdmirx-5v-detection {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
@ -745,6 +764,7 @@ usbc0_int: usbc0-int {
&pwm1 {
pinctrl-0 = <&pwm1m1_pins>;
pinctrl-names = "default";
status = "okay";
};
@ -1156,6 +1176,7 @@ &tsadc {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

18
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max.dts
View File

@ -35,6 +35,10 @@ hdmi1_con_in: endpoint {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -55,9 +59,10 @@ &hdmi0_sound {
};
&hdmi1 {
pinctrl-names = "default";
frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
&hdmim1_tx1_scl &hdmim1_tx1_sda>;
&hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -102,6 +107,15 @@ &led_green_pwm {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdmi1_tx_on_h: hdmi1-tx-on-h {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
usb_otg_pwren: usb-otg-pwren {

20
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
View File

@ -121,6 +121,10 @@ &fan {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -141,6 +145,10 @@ hdmi0_out_con: endpoint {
};
&hdmi1 {
frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
&hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -278,6 +286,16 @@ &pcie2x1l2 {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdmi1_tx_on_h: hdmi1-tx-on-h {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
@ -333,6 +351,7 @@ &pwm2 {
&pwm3 {
pinctrl-0 = <&pwm3m1_pins>;
pinctrl-names = "default";
status = "okay";
};
@ -351,6 +370,7 @@ &u2phy1_otg {
&uart9 {
pinctrl-0 = <&uart9m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

11
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-ultra.dts
View File

@ -25,9 +25,10 @@ hdmi1_con_in: endpoint {
};
&hdmi1 {
pinctrl-names = "default";
frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
&hdmim1_tx1_scl &hdmim1_tx1_sda>;
&hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -64,6 +65,12 @@ &led_green_pwm {
};
&pinctrl {
hdmi {
hdmi1_tx_on_h: hdmi1-tx-on-h {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
usb_otg_pwren: usb-otg-pwren {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;

1
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi
View File

@ -822,6 +822,7 @@ &u2phy3_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

19
arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts
View File

@ -325,6 +325,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -345,6 +349,10 @@ &hdmi0_sound {
};
&hdmi1 {
frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
&hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -583,6 +591,16 @@ led_pins: led-pins {
};
};
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdmi1_tx_on_h: hdmi1-tx-on-h {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
@ -1041,6 +1059,7 @@ &u2phy3_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

47
arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
View File

@ -346,8 +346,10 @@ &gpu {
};
&hdmi1 {
frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
&hdmim1_tx1_scl &hdmim1_tx1_sda>;
&hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -433,7 +435,6 @@ vdd_npu_s0: regulator@42 {
reg = <0x42>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_npu_s0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
@ -695,7 +696,17 @@ &pd_gpu {
domain-supply = <&vdd_gpu_s0>;
};
&pd_npu {
domain-supply = <&vdd_npu_s0>;
};
&pinctrl {
hdmi {
hdmi1_tx_on_h: hdmi1-tx-on-h {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
rtc_int: rtc-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
@ -814,6 +825,36 @@ dp1_hpd: dp1-hpd {
};
};
&rknn_core_0 {
npu-supply = <&vdd_npu_s0>;
sram-supply = <&vdd_npu_s0>;
status = "okay";
};
&rknn_core_1 {
npu-supply = <&vdd_npu_s0>;
sram-supply = <&vdd_npu_s0>;
status = "okay";
};
&rknn_core_2 {
npu-supply = <&vdd_npu_s0>;
sram-supply = <&vdd_npu_s0>;
status = "okay";
};
&rknn_mmu_0 {
status = "okay";
};
&rknn_mmu_1 {
status = "okay";
};
&rknn_mmu_2 {
status = "okay";
};
&pwm14 {
pinctrl-names = "default";
pinctrl-0 = <&pwm14m1_pins>;
@ -886,6 +927,7 @@ spi_flash: flash@0 {
&spdif_tx1 {
pinctrl-0 = <&spdif1m2_tx>;
pinctrl-names = "default";
status = "okay";
};
@ -1220,6 +1262,7 @@ &tsadc {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

19
arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
View File

@ -183,6 +183,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -203,8 +207,10 @@ &hdmi0_sound {
};
&hdmi1 {
frl-enable-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
&hdmim1_tx1_scl &hdmim1_tx1_sda>;
&hdmim1_tx1_scl &hdmim1_tx1_sda &hdmi1_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -505,6 +511,16 @@ &pd_npu {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdmi1_tx_on_h: hdmi1-tx-on-h {
rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
@ -959,6 +975,7 @@ &tsadc {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts
View File

@ -172,8 +172,9 @@ &hdmi0 {
* While HDMI-CEC is present on the Q7 connector, it is not
* connected on Haikou itself.
*/
pinctrl-0 = <&hdmim0_tx0_hpd &hdmim1_tx0_scl &hdmim1_tx0_sda
&hdmi0_tx_on_h>;
pinctrl-names = "default";
pinctrl-0 = <&hdmim0_tx0_hpd &hdmim1_tx0_scl &hdmim1_tx0_sda>;
status = "okay";
};
@ -273,6 +274,7 @@ &sdmmc {
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
disable-wp;
pinctrl-0 = <&sdmmc_bus4 &sdmmc_cmd &sdmmc_clk>;
pinctrl-names = "default";
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;

20
arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi
View File

@ -148,13 +148,15 @@ &gpu {
};
&hdmi0 {
pinctrl-names = "default";
frl-enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim1_tx0_cec &hdmim0_tx0_hpd &hdmim1_tx0_scl
&hdmim1_tx0_sda>;
&hdmim1_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
};
&i2c1 {
pinctrl-0 = <&i2c1m0_xfer>;
pinctrl-names = "default";
};
&i2c1m0_xfer {
@ -167,6 +169,7 @@ &i2c1m0_xfer {
&i2c2 {
pinctrl-0 = <&i2c2m3_xfer>;
pinctrl-names = "default";
};
&i2c2m3_xfer {
@ -179,10 +182,12 @@ &i2c2m3_xfer {
&i2c3 {
pinctrl-0 = <&i2c3m0_xfer>;
pinctrl-names = "default";
};
&i2c4 {
pinctrl-0 = <&i2c4m4_xfer>;
pinctrl-names = "default";
status = "okay";
vdd_npu_s0: regulator@42 {
@ -204,6 +209,7 @@ regulator-state-mem {
&i2c5 {
pinctrl-0 = <&i2c5m1_xfer>;
pinctrl-names = "default";
};
&i2c5m1_xfer {
@ -301,6 +307,7 @@ &i2c7m0_xfer {
&i2c8 {
pinctrl-0 = <&i2c8m2_xfer>;
pinctrl-names = "default";
};
&mdio0 {
@ -349,6 +356,12 @@ eth_reset: eth-reset {
};
};
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
module_led_pin: module-led-pin {
rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
@ -434,6 +447,7 @@ &sdmmc {
&spi0 {
pinctrl-0 = <&spi0m1_cs0 &spi0m1_cs1 &spi0m3_pins>;
pinctrl-names = "default";
};
&spi2 {
@ -764,10 +778,12 @@ &tsadc {
/* Routed to UART0 on the Q7 connector */
&uart2 {
pinctrl-0 = <&uart2m2_xfer>;
pinctrl-names = "default";
};
/* Mule-ATtiny UPDI */
&uart4 {
pinctrl-0 = <&uart4m2_xfer>;
pinctrl-names = "default";
status = "okay";
};

1
arch/arm64/boot/dts/rockchip/rk3588-toybrick-x0.dts
View File

@ -675,6 +675,7 @@ &u2phy3_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

2
arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
View File

@ -704,11 +704,13 @@ &tsadc {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};
&uart9 {
pinctrl-0 = <&uart9m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

16
arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts
View File

@ -251,6 +251,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -272,6 +276,7 @@ &hdptxphy0 {
&i2c0 {
pinctrl-0 = <&i2c0m2_xfer>;
pinctrl-names = "default";
status = "okay";
vdd_cpu_big0_s0: regulator@42 {
@ -332,6 +337,7 @@ regulator-state-mem {
&i2c6 {
pinctrl-0 = <&i2c6m3_xfer>;
pinctrl-names = "default";
status = "okay";
hym8563: rtc@51 {
@ -348,6 +354,7 @@ hym8563: rtc@51 {
&i2c7 {
pinctrl-0 = <&i2c7m0_xfer>;
pinctrl-names = "default";
status = "okay";
es8316: audio-codec@10 {
@ -373,6 +380,7 @@ &i2s0_mclk
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
pinctrl-names = "default";
status = "okay";
i2s0_8ch_p0: port {
@ -396,6 +404,12 @@ &pd_gpu {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
@ -459,6 +473,7 @@ wifi_poweren_pin: wifi-poweren-pin {
&pwm2 {
pinctrl-0 = <&pwm2m1_pins>;
pinctrl-names = "default";
status = "okay";
};
@ -865,6 +880,7 @@ &u2phy3_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

1
arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts
View File

@ -457,6 +457,7 @@ usbc0_int: usbc0-int {
&pwm12 {
pinctrl-0 = <&pwm12m1_pins>;
pinctrl-names = "default";
status = "okay";
};

15
arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts
View File

@ -302,9 +302,6 @@ amp_headphone: headphone-amplifier {
hdmi0-con {
compatible = "hdmi-connector";
ddc-en-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&hdmi0_en>;
pinctrl-names = "default";
type = "d";
port {
@ -514,8 +511,9 @@ &gpu {
&hdmi0 {
no-hpd;
frl-enable-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec>, <&hdmim0_tx0_scl>,
<&hdmim0_tx0_sda>;
<&hdmim0_tx0_sda>, <&hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -616,6 +614,7 @@ touchscreen@14 {
&i2c4 {
pinctrl-0 = <&i2c4m2_xfer>;
pinctrl-names = "default";
status = "okay";
ti_adc: adc@48 {
@ -652,6 +651,7 @@ imu@68 {
&i2c6 {
pinctrl-0 = <&i2c6m3_xfer>;
pinctrl-names = "default";
status = "okay";
fusb302: typec@22 {
@ -785,6 +785,7 @@ &i2s0_mclk
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdo0>;
pinctrl-names = "default";
status = "okay";
};
@ -893,7 +894,7 @@ charger_int_h: charger-int-h {
};
hdmi {
hdmi0_en: hdmi0-en {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins =
<4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
};
@ -1028,11 +1029,13 @@ wifi_host_wake_irq: wifi-host-wake-irq {
&pwm12 {
pinctrl-0 = <&pwm12m1_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm13 {
pinctrl-0 = <&pwm13m1_pins>;
pinctrl-names = "default";
status = "okay";
};
@ -1434,11 +1437,13 @@ &u2phy0_otg {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};
&uart9 {
pinctrl-0 = <&uart9m2_xfer>, <&uart9m2_ctsn>, <&uart9m2_rtsn>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";

13
arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
View File

@ -277,8 +277,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_scl>, <&hdmim0_tx0_sda>,
<&hdmim0_tx0_hpd>, <&hdmim0_tx0_cec>;
<&hdmim0_tx0_hpd>, <&hdmim0_tx0_cec>,
<&hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -366,6 +368,7 @@ regulator-state-mem {
&i2c6 {
pinctrl-0 = <&i2c6m3_xfer>;
pinctrl-names = "default";
status = "okay";
fusb302: typec-portc@22 {
@ -438,6 +441,7 @@ rtc_hym8563: rtc@51 {
&i2c7 {
pinctrl-0 = <&i2c7m0_xfer>;
pinctrl-names = "default";
status = "okay";
es8388: audio-codec@11 {
@ -517,6 +521,12 @@ bt_wake_host: bt-wake-host {
};
};
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
@ -965,6 +975,7 @@ &u2phy3_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

15
arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
View File

@ -194,6 +194,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -217,10 +221,6 @@ &hdptxphy0 {
status = "okay";
};
&hdmi0_sound {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
@ -282,6 +282,12 @@ &pd_gpu {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
vdd_sd {
vdd_sd_en: vdd-sd-en {
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
@ -736,6 +742,7 @@ &tsadc {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

11
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
View File

@ -236,6 +236,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -404,6 +408,12 @@ lan2_led_pin: lan2-led-pin {
};
};
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
rtc_int: rtc-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
@ -841,6 +851,7 @@ &u2phy2_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

10
arch/arm64/boot/dts/rockchip/rk3588s-odroid-m2.dts
View File

@ -249,6 +249,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -438,6 +442,12 @@ &pd_gpu {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd {
lcd_pwren: lcd-pwren {
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;

11
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi
View File

@ -181,6 +181,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -381,6 +385,12 @@ &pd_npu {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
@ -837,6 +847,7 @@ &u2phy3_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

12
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts
View File

@ -143,10 +143,11 @@ &gmac1_rgmii_clk
};
&hdmi0 {
pinctrl-names = "default";
frl-enable-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda
&hdmi_frl_pin>;
&hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -172,6 +173,7 @@ &hdptxphy0 {
&i2c1 {
pinctrl-0 = <&i2c1m2_xfer>;
pinctrl-names = "default";
status = "okay";
rtc@51 {
@ -245,8 +247,8 @@ key1_pin: key1-pin {
};
hdmi {
hdmi_frl_pin: hdmi-frl-pin {
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -279,6 +281,7 @@ &pwm4 {
&pwm5 {
pinctrl-0 = <&pwm5m1_pins>;
pinctrl-names = "default";
status = "okay";
};
@ -319,6 +322,7 @@ &u2phy2_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

3
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi
View File

@ -64,6 +64,7 @@ &gpu {
&i2c0 {
pinctrl-0 = <&i2c0m2_xfer>;
pinctrl-names = "default";
status = "okay";
vdd_cpu_big0_s0: regulator@42 {
@ -142,6 +143,7 @@ &spi2 {
assigned-clock-rates = <200000000>;
num-cs = <1>;
pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
pinctrl-names = "default";
status = "okay";
pmic@0 {
@ -468,5 +470,6 @@ &tsadc {
* through the CRU.
*/
pinctrl-0 = <&tsadc_gpio_func>;
pinctrl-names = "default";
status = "okay";
};

10
arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts
View File

@ -120,6 +120,10 @@ &gmac1 {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -217,6 +221,12 @@ usbc0_int: usbc0-int {
};
};
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;

17
arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts
View File

@ -224,6 +224,10 @@ &gpu {
};
&hdmi0 {
frl-enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda &hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -367,9 +371,9 @@ &pd_gpu {
};
&pinctrl {
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@ -379,6 +383,12 @@ hp_detect: hp-detect {
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
led_pins: led-pins {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
@ -800,6 +810,7 @@ &uart2 {
&uart7 {
pinctrl-0 = <&uart7m2_xfer>;
pinctrl-names = "default";
status = "okay";
};

13
arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
View File

@ -323,11 +323,13 @@ &gmac1_rgmii_clk
};
&hdmi0 {
pinctrl-names = "default";
frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec
&hdmim1_tx0_hpd
&hdmim0_tx0_scl
&hdmim0_tx0_sda>;
&hdmim0_tx0_sda
&hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -373,6 +375,12 @@ &pd_gpu {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
io_led: io-led {
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
@ -819,6 +827,7 @@ &u2phy3_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};

13
arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
View File

@ -258,11 +258,13 @@ &gpu {
};
&hdmi0 {
pinctrl-names = "default";
frl-enable-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&hdmim0_tx0_cec
&hdmim1_tx0_hpd
&hdmim0_tx0_scl
&hdmim0_tx0_sda>;
&hdmim0_tx0_sda
&hdmi0_tx_on_h>;
pinctrl-names = "default";
status = "okay";
};
@ -461,6 +463,12 @@ &pd_gpu {
};
&pinctrl {
hdmi {
hdmi0_tx_on_h: hdmi0-tx-on-h {
rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
leds {
led_pins: led-pins {
rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
@ -922,6 +930,7 @@ &u2phy3_host {
&uart2 {
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
status = "okay";
};