mirror of
https://github.com/torvalds/linux.git
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Merge tag 'drm-msm-next-2026-04-02' of https://gitlab.freedesktop.org/drm/msm into drm-next
Changes for v7.1 CI: - Uprev mesa - Restore CI jobs for Qualcomm APQ8016 and APQ8096 devices Core: - Switched to of_get_available_child_by_name() DPU: - Fixes for DSC panels - Fixed brownout because of the frequency / OPP mismatch - Quad pipe preparation (not enabled yet) - Switched to virtual planes by default - Dropped VBIF_NRT support - Added support for Eliza platform - Reworked alpha handling - Switched to correct CWB definitions on Eliza - Dropped dummy INTF_0 on MSM8953 - Corrected INTFs related to DP-MST DP: - Removed debug prints looking into PHY internals DSI: - Fixes for DSC panels - RGB101010 support - Support for SC8280XP - Moved PHY bindings from display/ to phy/ GPU: - Preemption support for x2-85 and a840 - IFPC support for a840 - SKU detection support for x2-85 and a840 - Expose AQE support (VK ray-pipeline) - Avoid locking in VM_BIND fence signaling path - Fix to avoid reclaim in GPU snapshot path - Disallow foreign mapping of _NO_SHARE BOs - Couple a6xx gpu snapshot fixes - Various other fixes HDMI: - Fixed infoframes programming MDP5: - Dropped support for MSM8974v1 - Dropped now unused code for MSM8974 v1 and SDM660 / MSM8998 Also misc small fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <rob.clark@oss.qualcomm.com> Link: https://patch.msgid.link/CACSVV012vn73BaUfk=Hw4WkQHZNPHiqfifWEunAqMc2EGOWUEQ@mail.gmail.com
This commit is contained in:
Dave Airlie
commit
512f9f150f
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|
@ -67,6 +67,7 @@ properties:
|
|||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,eliza-dp
|
||||
- qcom,sm8750-dp
|
||||
- const: qcom,sm8650-dp
|
||||
|
||||
|
|
|
|||
|
|
@ -49,8 +49,13 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- qcom,qcs8300-dsi-ctrl
|
||||
- qcom,sc8280xp-dsi-ctrl
|
||||
- const: qcom,sa8775p-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
- items:
|
||||
- const: qcom,eliza-dsi-ctrl
|
||||
- const: qcom,sm8750-dsi-ctrl
|
||||
- const: qcom,mdss-dsi-ctrl
|
||||
- enum:
|
||||
- qcom,dsi-ctrl-6g-qcm2290
|
||||
- qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
|
||||
|
|
|
|||
|
|
@ -91,6 +91,7 @@ allOf:
|
|||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,adreno-gmu-615.0
|
||||
- qcom,adreno-gmu-618.0
|
||||
- qcom,adreno-gmu-630.2
|
||||
then:
|
||||
|
|
|
|||
|
|
@ -440,13 +440,6 @@ allOf:
|
|||
clocks: false
|
||||
clock-names: false
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: kgsl_3d0_reg_memory
|
||||
- const: cx_mem
|
||||
- const: cx_dbgc
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,494 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/qcom,eliza-mdss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Eliza SoC Display MDSS
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description:
|
||||
Eliza SoC Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU
|
||||
display controller, DSI and DP interfaces etc.
|
||||
|
||||
$ref: /schemas/display/msm/mdss-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,eliza-mdss
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Display AHB
|
||||
- description: Display hf AXI
|
||||
- description: Display core
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: Interconnect path from mdp0 port to the data bus
|
||||
- description: Interconnect path from CPU to the reg bus
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: mdp0-mem
|
||||
- const: cpu-cfg
|
||||
|
||||
patternProperties:
|
||||
"^display-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,eliza-dpu
|
||||
|
||||
"^displayport-controller@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,eliza-dp
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,eliza-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,eliza-dsi-phy-4nm
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/interconnect/qcom,icc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/phy/phy-qcom-qmp.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
|
||||
display-subsystem@ae00000 {
|
||||
compatible = "qcom,eliza-mdss";
|
||||
reg = <0x0ae00000 0x1000>;
|
||||
reg-names = "mdss";
|
||||
ranges;
|
||||
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&disp_cc_mdss_ahb_clk>,
|
||||
<&gcc_disp_hf_axi_clk>,
|
||||
<&disp_cc_mdss_mdp_clk>;
|
||||
|
||||
resets = <&disp_cc_mdss_core_bcr>;
|
||||
|
||||
interconnects = <&mmss_noc_master_mdp QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY
|
||||
&config_noc_slave_display_cfg QCOM_ICC_TAG_ACTIVE_ONLY>;
|
||||
interconnect-names = "mdp0-mem",
|
||||
"cpu-cfg";
|
||||
|
||||
power-domains = <&mdss_gdsc>;
|
||||
|
||||
iommus = <&apps_smmu 0x800 0x2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mdss_mdp: display-controller@ae01000 {
|
||||
compatible = "qcom,eliza-dpu";
|
||||
reg = <0x0ae01000 0x93000>,
|
||||
<0x0aeb0000 0x2008>;
|
||||
reg-names = "mdp",
|
||||
"vbif";
|
||||
|
||||
interrupts-extended = <&mdss 0>;
|
||||
|
||||
clocks = <&gcc_disp_hf_axi_clk>,
|
||||
<&disp_cc_mdss_ahb_clk>,
|
||||
<&disp_cc_mdss_mdp_lut_clk>,
|
||||
<&disp_cc_mdss_mdp_clk>,
|
||||
<&disp_cc_mdss_vsync_clk>;
|
||||
clock-names = "nrt_bus",
|
||||
"iface",
|
||||
"lut",
|
||||
"core",
|
||||
"vsync";
|
||||
|
||||
assigned-clocks = <&disp_cc_mdss_vsync_clk>;
|
||||
assigned-clock-rates = <19200000>;
|
||||
|
||||
operating-points-v2 = <&mdp_opp_table>;
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&mdss_dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&mdss_dsi1_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
dpu_intf0_out: endpoint {
|
||||
remote-endpoint = <&mdss_dp0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-150000000 {
|
||||
opp-hz = /bits/ 64 <150000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs_d1>;
|
||||
};
|
||||
|
||||
opp-207000000 {
|
||||
opp-hz = /bits/ 64 <207000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-342000000 {
|
||||
opp-hz = /bits/ 64 <342000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-417000000 {
|
||||
opp-hz = /bits/ 64 <417000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-532000000 {
|
||||
opp-hz = /bits/ 64 <532000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
|
||||
opp-600000000 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
required-opps = <&rpmhpd_opp_nom_l1>;
|
||||
};
|
||||
|
||||
opp-660000000 {
|
||||
opp-hz = /bits/ 64 <660000000>;
|
||||
required-opps = <&rpmhpd_opp_turbo>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi@ae94000 {
|
||||
compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae94000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupts-extended = <&mdss 4>;
|
||||
|
||||
clocks = <&disp_cc_mdss_byte0_clk>,
|
||||
<&disp_cc_mdss_byte0_intf_clk>,
|
||||
<&disp_cc_mdss_pclk0_clk>,
|
||||
<&disp_cc_mdss_esc0_clk>,
|
||||
<&disp_cc_mdss_ahb_clk>,
|
||||
<&gcc_disp_hf_axi_clk>,
|
||||
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
|
||||
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
|
||||
<&disp_cc_esync0_clk>,
|
||||
<&disp_cc_osc_clk>,
|
||||
<&disp_cc_mdss_byte0_clk_src>,
|
||||
<&disp_cc_mdss_pclk0_clk_src>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus",
|
||||
"dsi_pll_pixel",
|
||||
"dsi_pll_byte",
|
||||
"esync",
|
||||
"osc",
|
||||
"byte_src",
|
||||
"pixel_src";
|
||||
|
||||
operating-points-v2 = <&mdss_dsi_opp_table>;
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
|
||||
phys = <&mdss_dsi0_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
mdss_dsi0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf1_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mdss_dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel0_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-140630000 {
|
||||
opp-hz = /bits/ 64 <140630000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs_d1>;
|
||||
};
|
||||
|
||||
opp-187500000 {
|
||||
opp-hz = /bits/ 64 <187500000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
required-opps = <&rpmhpd_opp_svs>;
|
||||
};
|
||||
|
||||
opp-358000000 {
|
||||
opp-hz = /bits/ 64 <358000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi0_phy: phy@ae95000 {
|
||||
compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
|
||||
reg = <0x0ae95000 0x200>,
|
||||
<0x0ae95200 0x280>,
|
||||
<0x0ae95500 0x400>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
clocks = <&disp_cc_mdss_ahb_clk>,
|
||||
<&bi_tcxo_div2>;
|
||||
clock-names = "iface",
|
||||
"ref";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vdds-supply = <&vreg_l2b>;
|
||||
};
|
||||
|
||||
dsi@ae96000 {
|
||||
compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
|
||||
reg = <0x0ae96000 0x400>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
interrupts-extended = <&mdss 5>;
|
||||
|
||||
clocks = <&disp_cc_mdss_byte1_clk>,
|
||||
<&disp_cc_mdss_byte1_intf_clk>,
|
||||
<&disp_cc_mdss_pclk1_clk>,
|
||||
<&disp_cc_mdss_esc1_clk>,
|
||||
<&disp_cc_mdss_ahb_clk>,
|
||||
<&gcc_disp_hf_axi_clk>,
|
||||
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
|
||||
<&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
|
||||
<&disp_cc_esync1_clk>,
|
||||
<&disp_cc_osc_clk>,
|
||||
<&disp_cc_mdss_byte1_clk_src>,
|
||||
<&disp_cc_mdss_pclk1_clk_src>;
|
||||
clock-names = "byte",
|
||||
"byte_intf",
|
||||
"pixel",
|
||||
"core",
|
||||
"iface",
|
||||
"bus",
|
||||
"dsi_pll_pixel",
|
||||
"dsi_pll_byte",
|
||||
"esync",
|
||||
"osc",
|
||||
"byte_src",
|
||||
"pixel_src";
|
||||
|
||||
operating-points-v2 = <&mdss_dsi_opp_table>;
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
|
||||
phys = <&mdss_dsi1_phy>;
|
||||
phy-names = "dsi";
|
||||
|
||||
vdda-supply = <&vreg_l4b>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
mdss_dsi1_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf2_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mdss_dsi1_out: endpoint {
|
||||
remote-endpoint = <&panel1_in>;
|
||||
data-lanes = <0 1 2 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi1_phy: phy@ae97000 {
|
||||
compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
|
||||
reg = <0x0ae97000 0x200>,
|
||||
<0x0ae97200 0x280>,
|
||||
<0x0ae97500 0x400>;
|
||||
reg-names = "dsi_phy",
|
||||
"dsi_phy_lane",
|
||||
"dsi_pll";
|
||||
|
||||
clocks = <&disp_cc_mdss_ahb_clk>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "iface",
|
||||
"ref";
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
vdds-supply = <&vreg_l2b>;
|
||||
};
|
||||
|
||||
displayport-controller@af54000 {
|
||||
compatible = "qcom,eliza-dp", "qcom,sm8650-dp";
|
||||
reg = <0xaf54000 0x104>,
|
||||
<0xaf54200 0xc0>,
|
||||
<0xaf55000 0x770>,
|
||||
<0xaf56000 0x9c>,
|
||||
<0xaf57000 0x9c>;
|
||||
|
||||
interrupts-extended = <&mdss 12>;
|
||||
|
||||
clocks = <&disp_cc_mdss_ahb_clk>,
|
||||
<&disp_cc_mdss_dptx0_aux_clk>,
|
||||
<&disp_cc_mdss_dptx0_link_clk>,
|
||||
<&disp_cc_mdss_dptx0_link_intf_clk>,
|
||||
<&disp_cc_mdss_dptx0_pixel0_clk>,
|
||||
<&disp_cc_mdss_dptx0_pixel1_clk>;
|
||||
clock-names = "core_iface",
|
||||
"core_aux",
|
||||
"ctrl_link",
|
||||
"ctrl_link_iface",
|
||||
"stream_pixel",
|
||||
"stream_1_pixel";
|
||||
|
||||
assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>,
|
||||
<&disp_cc_mdss_dptx0_pixel0_clk_src>,
|
||||
<&disp_cc_mdss_dptx0_pixel1_clk_src>;
|
||||
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
|
||||
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
|
||||
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
|
||||
|
||||
operating-points-v2 = <&dp_opp_table>;
|
||||
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
|
||||
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
|
||||
phy-names = "dp";
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
dp_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-192000000 {
|
||||
opp-hz = /bits/ 64 <192000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs_d1>;
|
||||
};
|
||||
|
||||
opp-270000000 {
|
||||
opp-hz = /bits/ 64 <270000000>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
};
|
||||
|
||||
opp-540000000 {
|
||||
opp-hz = /bits/ 64 <540000000>;
|
||||
required-opps = <&rpmhpd_opp_svs_l1>;
|
||||
};
|
||||
|
||||
opp-810000000 {
|
||||
opp-hz = /bits/ 64 <810000000>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
mdss_dp0_in: endpoint {
|
||||
remote-endpoint = <&dpu_intf0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mdss_dp0_out: endpoint {
|
||||
data-lanes = <0 1 2 3>;
|
||||
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
|
||||
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -50,6 +50,22 @@ patternProperties:
|
|||
- qcom,sc8280xp-dp
|
||||
- qcom,sc8280xp-edp
|
||||
|
||||
"^dsi@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,sc8280xp-dsi-ctrl
|
||||
|
||||
"^phy@[0-9a-f]+$":
|
||||
type: object
|
||||
additionalProperties: true
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,sc8280xp-dsi-phy-5nm
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -129,6 +145,20 @@ examples:
|
|||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dpu_intf1_out: endpoint {
|
||||
remote-endpoint = <&mdss0_dsi0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dpu_intf2_out: endpoint {
|
||||
remote-endpoint = <&mdss0_dsi1_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
endpoint {
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ properties:
|
|||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- qcom,eliza-dpu
|
||||
- qcom,glymur-dpu
|
||||
- qcom,kaanapali-dpu
|
||||
- qcom,sa8775p-dpu
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
|
||||
$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-10nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 10nm PHY
|
||||
|
|
@ -10,7 +10,7 @@ maintainers:
|
|||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
- $ref: qcom,dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
|
||||
$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-14nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 14nm PHY
|
||||
|
|
@ -10,7 +10,7 @@ maintainers:
|
|||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
- $ref: qcom,dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
|
||||
$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-20nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 20nm PHY
|
||||
|
|
@ -10,7 +10,7 @@ maintainers:
|
|||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
- $ref: qcom,dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
|
||||
$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-28nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 28nm PHY
|
||||
|
|
@ -10,7 +10,7 @@ maintainers:
|
|||
- Krishna Manikandan <quic_mkrishn@quicinc.com>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
- $ref: qcom,dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
|
||||
$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-7nm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI 7nm PHY
|
||||
|
|
@ -10,7 +10,7 @@ maintainers:
|
|||
- Jonathan Marek <jonathan@marek.ca>
|
||||
|
||||
allOf:
|
||||
- $ref: dsi-phy-common.yaml#
|
||||
- $ref: qcom,dsi-phy-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -29,9 +29,14 @@ properties:
|
|||
- qcom,sm8550-dsi-phy-4nm
|
||||
- qcom,sm8650-dsi-phy-4nm
|
||||
- qcom,sm8750-dsi-phy-3nm
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,eliza-dsi-phy-4nm
|
||||
- const: qcom,sm8650-dsi-phy-4nm
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs8300-dsi-phy-5nm
|
||||
- qcom,sc8280xp-dsi-phy-5nm
|
||||
- const: qcom,sa8775p-dsi-phy-5nm
|
||||
|
||||
reg:
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
|
||||
$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display DSI PHY Common Properties
|
||||
|
|
@ -2195,6 +2195,7 @@ L: dri-devel@lists.freedesktop.org
|
|||
S: Supported
|
||||
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
|
||||
F: Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
|
||||
F: drivers/gpu/drm/ci/xfails/panthor*
|
||||
F: drivers/gpu/drm/panthor/
|
||||
F: include/uapi/drm/panthor_drm.h
|
||||
|
||||
|
|
|
|||
|
|
@ -83,6 +83,7 @@ CONFIG_SC_DISPCC_7180=y
|
|||
CONFIG_SC_GPUCC_7180=y
|
||||
CONFIG_SM_GPUCC_8350=y
|
||||
CONFIG_QCOM_SPMI_ADC5=y
|
||||
CONFIG_QCOM_SPMI_VADC=y
|
||||
CONFIG_DRM_PARADE_PS8640=y
|
||||
CONFIG_DRM_LONTIUM_LT9611UXC=y
|
||||
CONFIG_PHY_QCOM_USB_HS=y
|
||||
|
|
@ -208,3 +209,8 @@ CONFIG_ARM_TEGRA_DEVFREQ=y
|
|||
CONFIG_TEGRA_SOCTHERM=y
|
||||
CONFIG_DRM_TEGRA_DEBUG=y
|
||||
CONFIG_PWM_TEGRA=y
|
||||
|
||||
# For Rockchip rk3588
|
||||
CONFIG_DRM_PANTHOR=m
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
|
||||
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
|
||||
|
|
|
|||
|
|
@ -3,9 +3,6 @@
|
|||
|
||||
set -ex
|
||||
|
||||
# Clean up stale rebases that GitLab might not have removed when reusing a checkout dir
|
||||
rm -rf .git/rebase-apply
|
||||
|
||||
. .gitlab-ci/container/container_pre_build.sh
|
||||
|
||||
# libssl-dev was uninstalled because it was considered an ephemeral package
|
||||
|
|
@ -19,6 +16,7 @@ if [[ "$KERNEL_ARCH" = "arm64" ]]; then
|
|||
GCC_ARCH="aarch64-linux-gnu"
|
||||
DEBIAN_ARCH="arm64"
|
||||
DEVICE_TREES="arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dtb"
|
||||
DEVICE_TREES+=" arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtb"
|
||||
DEVICE_TREES+=" arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dtb"
|
||||
DEVICE_TREES+=" arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dtb"
|
||||
DEVICE_TREES+=" arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dtb"
|
||||
|
|
@ -61,25 +59,24 @@ export PATH=$NEWPATH:$PATH
|
|||
|
||||
git config --global user.email "fdo@example.com"
|
||||
git config --global user.name "freedesktop.org CI"
|
||||
git config --global pull.rebase true
|
||||
|
||||
# cleanup git state on the worker
|
||||
rm -rf .git/rebase-merge
|
||||
rm -rf .git/rebase-merge .git/rebase-apply
|
||||
|
||||
# Try to merge fixes from target repo
|
||||
if [ "$(git ls-remote --exit-code --heads ${UPSTREAM_REPO} ${TARGET_BRANCH}-external-fixes)" ]; then
|
||||
git pull ${UPSTREAM_REPO} ${TARGET_BRANCH}-external-fixes
|
||||
git pull --no-rebase ${UPSTREAM_REPO} ${TARGET_BRANCH}-external-fixes
|
||||
fi
|
||||
|
||||
# Try to merge fixes from local repo if this isn't a merge request
|
||||
# otherwise try merging the fixes from the merge target
|
||||
if [ -z "$CI_MERGE_REQUEST_PROJECT_PATH" ]; then
|
||||
if [ "$(git ls-remote --exit-code --heads origin ${TARGET_BRANCH}-external-fixes)" ]; then
|
||||
git pull origin ${TARGET_BRANCH}-external-fixes
|
||||
git pull --no-rebase origin ${TARGET_BRANCH}-external-fixes
|
||||
fi
|
||||
else
|
||||
if [ "$(git ls-remote --exit-code --heads ${CI_MERGE_REQUEST_PROJECT_URL} ${CI_MERGE_REQUEST_TARGET_BRANCH_NAME}-external-fixes)" ]; then
|
||||
git pull ${CI_MERGE_REQUEST_PROJECT_URL} ${CI_MERGE_REQUEST_TARGET_BRANCH_NAME}-external-fixes
|
||||
git pull --no-rebase ${CI_MERGE_REQUEST_PROJECT_URL} ${CI_MERGE_REQUEST_TARGET_BRANCH_NAME}-external-fixes
|
||||
fi
|
||||
fi
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
.build:
|
||||
extends:
|
||||
- .container+build-rules
|
||||
- .build-rules
|
||||
stage: build-only
|
||||
artifacts:
|
||||
paths:
|
||||
|
|
@ -133,6 +133,10 @@ debian-arm32-asan:
|
|||
rules:
|
||||
- when: never
|
||||
|
||||
debian-x86_64-msan:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
debian-arm64:
|
||||
rules:
|
||||
- when: never
|
||||
|
|
@ -153,7 +157,7 @@ debian-arm64-ubsan:
|
|||
rules:
|
||||
- when: never
|
||||
|
||||
debian-build-testing:
|
||||
debian-build-x86_64:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
|
|
@ -177,26 +181,14 @@ debian-release:
|
|||
rules:
|
||||
- when: never
|
||||
|
||||
debian-riscv64:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
debian-s390x:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
debian-testing:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
debian-testing-asan:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
debian-testing-msan:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
debian-testing-ubsan:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
debian-vulkan:
|
||||
rules:
|
||||
- when: never
|
||||
|
|
@ -205,6 +197,18 @@ debian-x86_32:
|
|||
rules:
|
||||
- when: never
|
||||
|
||||
debian-x86_64:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
debian-x86_64-asan:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
debian-x86_64-ubsan:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
fedora-release:
|
||||
rules:
|
||||
- when: never
|
||||
|
|
|
|||
|
|
@ -5,21 +5,29 @@
|
|||
|
||||
debian/x86_64_build-base:
|
||||
variables:
|
||||
EXTRA_LOCAL_PACKAGES: "libcairo-dev libdw-dev libjson-c-dev libkmod2 libkmod-dev libpciaccess-dev libproc2-dev libudev-dev libunwind-dev python3-docutils bc python3-ply libssl-dev bc"
|
||||
|
||||
debian/x86_64_test-gl:
|
||||
variables:
|
||||
EXTRA_LOCAL_PACKAGES: "jq libasound2 libcairo2 libdw1 libglib2.0-0 libjson-c5 libkmod-dev libkmod2 libgles2 libproc2-dev"
|
||||
EXTRA_LOCAL_PACKAGES: "libcairo-dev libdw-dev libjson-c-dev libkmod-dev libpciaccess-dev libproc2-dev libudev-dev libunwind-dev python3-docutils bc python3-ply libssl-dev bc"
|
||||
|
||||
debian/arm64_build:
|
||||
variables:
|
||||
EXTRA_LOCAL_PACKAGES: "libcairo-dev libdw-dev libjson-c-dev libproc2-dev libkmod2 libkmod-dev libpciaccess-dev libudev-dev libunwind-dev python3-docutils libssl-dev crossbuild-essential-armhf libkmod-dev:armhf libproc2-dev:armhf libunwind-dev:armhf libdw-dev:armhf libpixman-1-dev:armhf libcairo-dev:armhf libudev-dev:armhf libjson-c-dev:armhf"
|
||||
EXTRA_LOCAL_PACKAGES: "libcairo-dev libdw-dev libjson-c-dev libproc2-dev libkmod-dev libpciaccess-dev libudev-dev libunwind-dev python3-docutils libssl-dev crossbuild-essential-armhf libkmod-dev:armhf libproc2-dev:armhf libunwind-dev:armhf libdw-dev:armhf libpixman-1-dev:armhf libcairo-dev:armhf libudev-dev:armhf libjson-c-dev:armhf"
|
||||
|
||||
.kernel+rootfs:
|
||||
debian/x86_64_test-gl:
|
||||
variables:
|
||||
EXTRA_LOCAL_PACKAGES: "jq libasound2 libcairo2 libdw1 libglib2.0-0 libjson-c5"
|
||||
EXTRA_LOCAL_PACKAGES: "jq libasound2t64 libcairo2 libdw1t64 libglib2.0-0t64 libjson-c5 libkmod2 libgles2 libdrm-nouveau2 libdrm-amdgpu1"
|
||||
|
||||
debian/arm64_test-gl:
|
||||
variables:
|
||||
EXTRA_LOCAL_PACKAGES: "jq libasound2t64 libcairo2 libdw1t64 libglib2.0-0t64 libjson-c5 libkmod2 libgles2 libdrm-nouveau2 libdrm-amdgpu1"
|
||||
|
||||
debian/arm32_test-gl:
|
||||
variables:
|
||||
EXTRA_LOCAL_PACKAGES: "jq libasound2t64 libcairo2 libdw1t64 libglib2.0-0t64 libjson-c5 libkmod2 libgles2 libdrm-nouveau2 libdrm-amdgpu1 libunwind8"
|
||||
|
||||
# Disable container jobs that we won't use
|
||||
alpine/x86_64_build:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
debian/arm64_test-vk:
|
||||
rules:
|
||||
- when: never
|
||||
|
|
@ -28,6 +36,10 @@ debian/baremetal_arm32_test-gl:
|
|||
rules:
|
||||
- when: never
|
||||
|
||||
debian/baremetal_arm64_test-gl:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
debian/baremetal_arm64_test-vk:
|
||||
rules:
|
||||
- when: never
|
||||
|
|
@ -36,6 +48,10 @@ debian/ppc64el_build:
|
|||
rules:
|
||||
- when: never
|
||||
|
||||
debian/riscv64_build:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
debian/s390x_build:
|
||||
rules:
|
||||
- when: never
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
variables:
|
||||
DRM_CI_PROJECT_PATH: &drm-ci-project-path mesa/mesa
|
||||
DRM_CI_COMMIT_SHA: &drm-ci-commit-sha 02337aec715c25dae7ff2479d986f831c77fe536
|
||||
DRM_CI_COMMIT_SHA: &drm-ci-commit-sha 25881c701a56233dd8fc7f92db6884a73949d63d
|
||||
|
||||
UPSTREAM_REPO: https://gitlab.freedesktop.org/drm/kernel.git
|
||||
TARGET_BRANCH: drm-next
|
||||
|
|
@ -11,7 +11,7 @@ variables:
|
|||
DEQP_RUNNER_GIT_TAG: v0.20.0
|
||||
|
||||
FDO_UPSTREAM_REPO: helen.fornazier/linux # The repo where the git-archive daily runs
|
||||
MESA_TEMPLATES_COMMIT: &ci-templates-commit c6aeb16f86e32525fa630fb99c66c4f3e62fc3cb
|
||||
MESA_TEMPLATES_COMMIT: &ci-templates-commit aec7a6ce7bb38902c70641526f6611e27141784a
|
||||
DRM_CI_PROJECT_URL: https://gitlab.freedesktop.org/${DRM_CI_PROJECT_PATH}
|
||||
CI_PRE_CLONE_SCRIPT: |-
|
||||
set -o xtrace
|
||||
|
|
@ -30,6 +30,8 @@ variables:
|
|||
S3_GITCACHE_BUCKET: git-cache
|
||||
# Bucket for the pipeline artifacts pushed to S3
|
||||
S3_ARTIFACTS_BUCKET: artifacts
|
||||
# Base path used for various artifacts
|
||||
S3_BASE_PATH: "${S3_HOST}/${S3_KERNEL_BUCKET}"
|
||||
# per-pipeline artifact storage on MinIO
|
||||
PIPELINE_ARTIFACTS_BASE: ${S3_HOST}/${S3_ARTIFACTS_BUCKET}/${CI_PROJECT_PATH}/${CI_PIPELINE_ID}
|
||||
# per-job artifact storage on MinIO
|
||||
|
|
@ -44,6 +46,8 @@ variables:
|
|||
ARTIFACTS_BASE_URL: https://${CI_PROJECT_ROOT_NAMESPACE}.${CI_PAGES_DOMAIN}/-/${CI_PROJECT_NAME}/-/jobs/${CI_JOB_ID}/artifacts
|
||||
# Python scripts for structured logger
|
||||
PYTHONPATH: "$PYTHONPATH:$CI_PROJECT_DIR/install"
|
||||
# Mesa-specific variables that shouldn't be forwarded to DUTs and crosvm
|
||||
CI_EXCLUDE_ENV_VAR_REGEX: 'SCRIPTS_DIR|RESULTS_DIR'
|
||||
|
||||
|
||||
default:
|
||||
|
|
@ -84,10 +88,11 @@ include:
|
|||
- project: *drm-ci-project-path
|
||||
ref: *drm-ci-commit-sha
|
||||
file:
|
||||
- '/.gitlab-ci/bare-metal/gitlab-ci.yml'
|
||||
- '/.gitlab-ci/build/gitlab-ci.yml'
|
||||
- '/.gitlab-ci/container/gitlab-ci.yml'
|
||||
- '/.gitlab-ci/farm-rules.yml'
|
||||
- '/.gitlab-ci/lava/lava-gitlab-ci.yml'
|
||||
- '/.gitlab-ci/lava/gitlab-ci.yml'
|
||||
- '/.gitlab-ci/test-source-dep.yml'
|
||||
- '/.gitlab-ci/test/gitlab-ci.yml'
|
||||
- '/src/amd/ci/gitlab-ci-inc.yml'
|
||||
|
|
@ -131,6 +136,7 @@ stages:
|
|||
- meson
|
||||
- msm
|
||||
- panfrost
|
||||
- panthor
|
||||
- powervr
|
||||
- rockchip
|
||||
- software-driver
|
||||
|
|
@ -147,10 +153,10 @@ stages:
|
|||
- if: &is-merge-attempt $GITLAB_USER_LOGIN == "marge-bot" && $CI_PIPELINE_SOURCE == "merge_request_event"
|
||||
# post-merge pipeline
|
||||
- if: &is-post-merge $GITLAB_USER_LOGIN == "marge-bot" && $CI_PIPELINE_SOURCE == "push"
|
||||
# Pre-merge pipeline
|
||||
- if: &is-pre-merge $CI_PIPELINE_SOURCE == "merge_request_event"
|
||||
# Pre-merge pipeline (because merge pipelines are already caught above)
|
||||
- if: &is-merge-request $CI_PIPELINE_SOURCE == "merge_request_event"
|
||||
# Push to a branch on a fork
|
||||
- if: &is-fork-push $CI_PIPELINE_SOURCE == "push"
|
||||
- if: &is-push-to-fork $CI_PIPELINE_SOURCE == "push"
|
||||
# nightly pipeline
|
||||
- if: &is-scheduled-pipeline $CI_PIPELINE_SOURCE == "schedule"
|
||||
# pipeline for direct pushes that bypassed the CI
|
||||
|
|
@ -160,17 +166,59 @@ stages:
|
|||
# Rules applied to every job in the pipeline
|
||||
.common-rules:
|
||||
rules:
|
||||
- if: *is-fork-push
|
||||
- if: *is-push-to-fork
|
||||
when: manual
|
||||
|
||||
|
||||
.never-post-merge-rules:
|
||||
rules:
|
||||
- if: *is-post-merge
|
||||
when: never
|
||||
|
||||
|
||||
.container+build-rules:
|
||||
# Note: make sure the branches in this list are the same as in
|
||||
# `.build-only-delayed-rules` below.
|
||||
.container-rules:
|
||||
rules:
|
||||
- !reference [.common-rules, rules]
|
||||
# Run when re-enabling a disabled farm, but not when disabling it
|
||||
- !reference [.disable-farm-mr-rules, rules]
|
||||
# Never run immediately after merging, as we just ran everything
|
||||
- !reference [.never-post-merge-rules, rules]
|
||||
# Only rebuild containers in merge pipelines if any tags have been
|
||||
# changed, else we'll just use the already-built containers
|
||||
- if: *is-merge-attempt
|
||||
changes: &image_tags_path
|
||||
- drivers/gpu/drm/ci/image-tags.yml
|
||||
when: on_success
|
||||
# Skip everything for pre-merge and merge pipelines which don't change
|
||||
# anything in the build; we only do this for marge-bot and not user
|
||||
# pipelines in a MR, because we might still need to run it to copy the
|
||||
# container into the user's namespace.
|
||||
- if: *is-merge-attempt
|
||||
when: never
|
||||
# Any MR pipeline which changes image-tags.yml needs to be able to
|
||||
# rebuild the containers
|
||||
- if: *is-merge-request
|
||||
changes: *image_tags_path
|
||||
when: manual
|
||||
# ... however for MRs running inside the user namespace, we may need to
|
||||
# run these jobs to copy the container images from upstream
|
||||
- if: *is-merge-request
|
||||
when: manual
|
||||
# Build everything after someone bypassed the CI
|
||||
- if: *is-direct-push
|
||||
when: manual
|
||||
# Scheduled pipelines reuse already-built containers
|
||||
- if: *is-scheduled-pipeline
|
||||
when: never
|
||||
# Allow building everything in fork pipelines, but build nothing unless
|
||||
# manually triggered
|
||||
- when: manual
|
||||
|
||||
|
||||
# Note: make sure the branches in this list are the same as in
|
||||
# `.build-only-delayed-rules` below.
|
||||
.build-rules:
|
||||
rules:
|
||||
- !reference [.common-rules, rules]
|
||||
# Run when re-enabling a disabled farm, but not when disabling it
|
||||
|
|
@ -181,7 +229,7 @@ stages:
|
|||
- if: *is-merge-attempt
|
||||
when: on_success
|
||||
# Same as above, but for pre-merge pipelines
|
||||
- if: *is-pre-merge
|
||||
- if: *is-merge-request
|
||||
when: manual
|
||||
# Build everything after someone bypassed the CI
|
||||
- if: *is-direct-push
|
||||
|
|
@ -197,7 +245,7 @@ stages:
|
|||
# Repeat of the above but with `when: on_success` replaced with
|
||||
# `when: delayed` + `start_in:`, for build-only jobs.
|
||||
# Note: make sure the branches in this list are the same as in
|
||||
# `.container+build-rules` above.
|
||||
# `.build-rules` above.
|
||||
.build-only-delayed-rules:
|
||||
rules:
|
||||
- !reference [.common-rules, rules]
|
||||
|
|
@ -210,7 +258,7 @@ stages:
|
|||
when: delayed
|
||||
start_in: &build-delay 5 minutes
|
||||
# Same as above, but for pre-merge pipelines
|
||||
- if: *is-pre-merge
|
||||
- if: *is-merge-request
|
||||
when: manual
|
||||
# Build everything after someone bypassed the CI
|
||||
- if: *is-direct-push
|
||||
|
|
@ -237,11 +285,6 @@ stages:
|
|||
- _build/meson-logs/strace
|
||||
|
||||
|
||||
python-artifacts:
|
||||
variables:
|
||||
GIT_DEPTH: 10
|
||||
|
||||
|
||||
# Git archive
|
||||
make-git-archive:
|
||||
extends:
|
||||
|
|
@ -273,7 +316,7 @@ sanity:
|
|||
tags:
|
||||
- $FDO_RUNNER_JOB_PRIORITY_TAG_X86_64
|
||||
rules:
|
||||
- if: *is-pre-merge
|
||||
- if: *is-merge-request
|
||||
when: on_success
|
||||
- when: never
|
||||
variables:
|
||||
|
|
@ -284,7 +327,6 @@ sanity:
|
|||
- |
|
||||
set -eu
|
||||
image_tags=(
|
||||
ALPINE_X86_64_LAVA_SSH_TAG
|
||||
CONTAINER_TAG
|
||||
DEBIAN_BASE_TAG
|
||||
DEBIAN_BUILD_TAG
|
||||
|
|
@ -347,3 +389,19 @@ linkcheck-docs:
|
|||
test-docs:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
.ci-tron-x86_64-test-vk:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
.ci-tron-x86_64-test-gl-manual:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
.ci-tron-arm64-test-gl:
|
||||
rules:
|
||||
- when: never
|
||||
|
||||
.ci-tron-x86_64-test-gl:
|
||||
rules:
|
||||
- when: never
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
#!/bin/sh
|
||||
#!/usr/bin/env bash
|
||||
# SPDX-License-Identifier: MIT
|
||||
|
||||
. "${SCRIPTS_DIR}/setup-test-env.sh"
|
||||
|
||||
set -ex
|
||||
|
||||
export IGT_FORCE_DRIVER=${DRIVER_NAME}
|
||||
|
|
@ -21,7 +23,7 @@ set -e
|
|||
|
||||
mkdir -p /lib/modules
|
||||
case "$DRIVER_NAME" in
|
||||
amdgpu|vkms)
|
||||
amdgpu|vkms|panthor)
|
||||
# Cannot use HWCI_KERNEL_MODULES as at that point we don't have the module in /lib
|
||||
mv /install/modules/lib/modules/* /lib/modules/. || true
|
||||
modprobe --first-time $DRIVER_NAME
|
||||
|
|
|
|||
|
|
@ -1,18 +1,22 @@
|
|||
variables:
|
||||
CONTAINER_TAG: "20250502-mesa-uprev"
|
||||
DEBIAN_BASE_TAG: "${CONTAINER_TAG}"
|
||||
CONTAINER_TAG: "20260108-mesa-igt"
|
||||
|
||||
DEBIAN_BUILD_BASE_TAG: "${CONTAINER_TAG}"
|
||||
DEBIAN_BUILD_TAG: "${CONTAINER_TAG}"
|
||||
DEBIAN_TEST_BASE_TAG: "${CONTAINER_TAG}"
|
||||
|
||||
DEBIAN_TEST_GL_TAG: "${CONTAINER_TAG}"
|
||||
# default kernel for rootfs before injecting the current kernel tree
|
||||
KERNEL_TAG: "v6.14-mesa-0bdd"
|
||||
KERNEL_TAG: "v6.16-mesa-9d85"
|
||||
KERNEL_REPO: "gfx-ci/linux"
|
||||
PKG_REPO_REV: "95bf62c"
|
||||
|
||||
DEBIAN_PYUTILS_TAG: "${CONTAINER_TAG}"
|
||||
PKG_REPO_REV: "0d2527f6"
|
||||
FIRMWARE_TAG: "8fc31b97"
|
||||
FIRMWARE_REPO: "gfx-ci/firmware"
|
||||
|
||||
ALPINE_X86_64_BUILD_TAG: "${CONTAINER_TAG}"
|
||||
ALPINE_X86_64_LAVA_SSH_TAG: "${CONTAINER_TAG}"
|
||||
|
||||
CONDITIONAL_BUILD_ANGLE_TAG: 384145a4023315dae658259bee07c43a
|
||||
CONDITIONAL_BUILD_PIGLIT_TAG: a19e424b8a3f020dbf1b9dd29f220a4f
|
||||
CONDITIONAL_BUILD_ANGLE_TAG: efd57e99d51361944f87b9466356b0ce
|
||||
CONDITIONAL_BUILD_CROSVM_TAG: 4079babd375b09761d59eacb25a0598a
|
||||
CONDITIONAL_BUILD_PIGLIT_TAG: 21ab2c66f54777163dd038dc4cfcfde6
|
||||
|
||||
CROSVM_TAG: ${CONDITIONAL_BUILD_CROSVM_TAG}
|
||||
|
|
|
|||
|
|
@ -3,27 +3,18 @@
|
|||
# shellcheck disable=SC2086 # we want word splitting
|
||||
# shellcheck disable=SC1091 # paths only become valid at runtime
|
||||
|
||||
# If we run in the fork (not from mesa or Marge-bot), reuse mainline kernel and rootfs, if exist.
|
||||
_check_artifact_path() {
|
||||
_url="https://${1}/${2}"
|
||||
if curl -s -o /dev/null -I -L -f --retry 4 --retry-delay 15 "${_url}"; then
|
||||
echo -n "${_url}"
|
||||
fi
|
||||
}
|
||||
# shellcheck disable=SC1090
|
||||
source "${FDO_CI_BASH_HELPERS}"
|
||||
|
||||
get_path_to_artifact() {
|
||||
_mainline_artifact="$(_check_artifact_path ${BASE_SYSTEM_MAINLINE_HOST_PATH} ${1})"
|
||||
if [ -n "${_mainline_artifact}" ]; then
|
||||
echo -n "${_mainline_artifact}"
|
||||
return
|
||||
fi
|
||||
_fork_artifact="$(_check_artifact_path ${BASE_SYSTEM_FORK_HOST_PATH} ${1})"
|
||||
if [ -n "${_fork_artifact}" ]; then
|
||||
echo -n "${_fork_artifact}"
|
||||
return
|
||||
fi
|
||||
fdo_log_section_start_collapsed prepare_rootfs "Preparing root filesystem"
|
||||
|
||||
set -ex
|
||||
|
||||
# If we run in the fork (not from mesa or Marge-bot), reuse mainline kernel and rootfs, if exist.
|
||||
ROOTFS_URL="$(fdo_find_s3_path "$LAVA_ROOTFS_PATH")" ||
|
||||
{
|
||||
set +x
|
||||
error "Sorry, I couldn't find a viable built path for ${1} in either mainline or a fork." >&2
|
||||
fdo_log_section_error "Sorry, I couldn't find a viable built path for ${LAVA_ROOTFS_PATH} in either mainline or a fork." >&2
|
||||
echo "" >&2
|
||||
echo "If you're working on CI, this probably means that you're missing a dependency:" >&2
|
||||
echo "this job ran ahead of the job which was supposed to upload that artifact." >&2
|
||||
|
|
@ -35,38 +26,51 @@ get_path_to_artifact() {
|
|||
exit 1
|
||||
}
|
||||
|
||||
. "${SCRIPTS_DIR}/setup-test-env.sh"
|
||||
|
||||
section_start prepare_rootfs "Preparing root filesystem"
|
||||
|
||||
set -ex
|
||||
|
||||
ROOTFS_URL="$(get_path_to_artifact lava-rootfs.tar.zst)"
|
||||
[ $? != 1 ] || exit 1
|
||||
|
||||
rm -rf results
|
||||
mkdir -p results/job-rootfs-overlay/
|
||||
mkdir results
|
||||
|
||||
artifacts/ci-common/export-gitlab-job-env-for-dut.sh \
|
||||
> results/job-rootfs-overlay/set-job-env-vars.sh
|
||||
cp artifacts/ci-common/init-*.sh results/job-rootfs-overlay/
|
||||
cp "$SCRIPTS_DIR"/setup-test-env.sh results/job-rootfs-overlay/
|
||||
fdo_filter_env_vars > dut-env-vars.sh
|
||||
# Set SCRIPTS_DIR to point to the Mesa install we download for the DUT
|
||||
echo "export SCRIPTS_DIR='$CI_PROJECT_DIR/install'" >> dut-env-vars.sh
|
||||
|
||||
tar zcf job-rootfs-overlay.tar.gz -C results/job-rootfs-overlay/ .
|
||||
ci-fairy s3cp --token-file "${S3_JWT_FILE}" job-rootfs-overlay.tar.gz "https://${JOB_ROOTFS_OVERLAY_PATH}"
|
||||
fdo_log_section_end prepare_rootfs
|
||||
|
||||
# Prepare env vars for upload.
|
||||
section_switch variables "Environment variables passed through to device:"
|
||||
cat results/job-rootfs-overlay/set-job-env-vars.sh
|
||||
fdo_log_section_start_collapsed variables "Environment variables passed through to device:"
|
||||
cat dut-env-vars.sh
|
||||
fdo_log_section_end variables
|
||||
|
||||
section_switch lava_submit "Submitting job for scheduling"
|
||||
fdo_log_section_start_collapsed lava_submit "Submitting job for scheduling"
|
||||
|
||||
touch results/lava.log
|
||||
tail -f results/lava.log &
|
||||
# Ensure that we are printing the commands that are being executed,
|
||||
# making it easier to debug the job in case it fails.
|
||||
set -x
|
||||
PYTHONPATH=artifacts/ artifacts/lava/lava_job_submitter.py \
|
||||
|
||||
# List of optional overlays
|
||||
LAVA_EXTRA_OVERLAYS=()
|
||||
if [ -n "${LAVA_FIRMWARE:-}" ]; then
|
||||
for fw in $LAVA_FIRMWARE; do
|
||||
LAVA_EXTRA_OVERLAYS+=(
|
||||
- append-overlay
|
||||
--name=linux-firmware
|
||||
--url="https://${S3_BASE_PATH}/${FIRMWARE_REPO}/${fw}-${FIRMWARE_TAG}.tar"
|
||||
--path="/"
|
||||
--format=tar
|
||||
)
|
||||
done
|
||||
fi
|
||||
LAVA_EXTRA_OVERLAYS+=(
|
||||
- append-overlay \
|
||||
--name=kernel-build \
|
||||
--url="${FDO_HTTP_CACHE_URI:-}https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/kernel-files.tar.zst" \
|
||||
--compression=zstd \
|
||||
--path="${CI_PROJECT_DIR}" \
|
||||
--format=tar \
|
||||
)
|
||||
|
||||
lava-job-submitter \
|
||||
--farm "${FARM}" \
|
||||
--device-type "${DEVICE_TYPE}" \
|
||||
--boot-method "${BOOT_METHOD}" \
|
||||
|
|
@ -75,9 +79,8 @@ PYTHONPATH=artifacts/ artifacts/lava/lava_job_submitter.py \
|
|||
--pipeline-info "$CI_JOB_NAME: $CI_PIPELINE_URL on $CI_COMMIT_REF_NAME ${CI_NODE_INDEX}/${CI_NODE_TOTAL}" \
|
||||
--rootfs-url "${ROOTFS_URL}" \
|
||||
--kernel-url-prefix "https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}" \
|
||||
--kernel-external "${EXTERNAL_KERNEL_TAG}" \
|
||||
--first-stage-init artifacts/ci-common/init-stage1.sh \
|
||||
--dtb-filename "${DTB}" \
|
||||
--env-file dut-env-vars.sh \
|
||||
--jwt-file "${S3_JWT_FILE}" \
|
||||
--kernel-image-name "${KERNEL_IMAGE_NAME}" \
|
||||
--kernel-image-type "${KERNEL_IMAGE_TYPE}" \
|
||||
|
|
@ -86,20 +89,10 @@ PYTHONPATH=artifacts/ artifacts/lava/lava_job_submitter.py \
|
|||
--mesa-job-name "$CI_JOB_NAME" \
|
||||
--structured-log-file "results/lava_job_detail.json" \
|
||||
--ssh-client-image "${LAVA_SSH_CLIENT_IMAGE}" \
|
||||
--project-dir "${CI_PROJECT_DIR}" \
|
||||
--project-name "${CI_PROJECT_NAME}" \
|
||||
--starting-section "${CURRENT_SECTION}" \
|
||||
--starting-section lava_submit \
|
||||
--job-submitted-at "${CI_JOB_STARTED_AT}" \
|
||||
- append-overlay \
|
||||
--name=kernel-build \
|
||||
--url="${FDO_HTTP_CACHE_URI:-}https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/kernel-files.tar.zst" \
|
||||
--compression=zstd \
|
||||
--path="${CI_PROJECT_DIR}" \
|
||||
--format=tar \
|
||||
- append-overlay \
|
||||
--name=job-overlay \
|
||||
--url="https://${JOB_ROOTFS_OVERLAY_PATH}" \
|
||||
--compression=gz \
|
||||
--path="/" \
|
||||
--format=tar \
|
||||
"${LAVA_EXTRA_OVERLAYS[@]}" \
|
||||
- submit \
|
||||
>> results/lava.log
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
check-patch:
|
||||
stage: static-checks
|
||||
extends:
|
||||
- .build
|
||||
- .use-debian/x86_64_build
|
||||
|
|
|
|||
|
|
@ -7,13 +7,16 @@
|
|||
|
||||
.lava-test:
|
||||
extends:
|
||||
- .container+build-rules
|
||||
- .build-rules
|
||||
- .allow_failure_lockdep
|
||||
timeout: "1h30m"
|
||||
rules:
|
||||
- !reference [.scheduled_pipeline-rules, rules]
|
||||
- !reference [.collabora-farm-rules, rules]
|
||||
- when: on_success
|
||||
before_script:
|
||||
# lava-submit.sh is a part of the archive, unlike Mesa CI
|
||||
- eval "$S3_JWT_FILE_SCRIPT"
|
||||
script:
|
||||
# Note: Build dir (and thus install) may be dirty due to GIT_STRATEGY
|
||||
- rm -rf install
|
||||
|
|
@ -32,9 +35,7 @@
|
|||
dependencies:
|
||||
- testing:arm32
|
||||
needs:
|
||||
- alpine/x86_64_lava_ssh_client
|
||||
- debian/arm32_test-gl
|
||||
- python-artifacts
|
||||
- testing:arm32
|
||||
- igt:arm32
|
||||
|
||||
|
|
@ -48,9 +49,7 @@
|
|||
dependencies:
|
||||
- testing:arm64
|
||||
needs:
|
||||
- alpine/x86_64_lava_ssh_client
|
||||
- debian/arm64_test-gl
|
||||
- python-artifacts
|
||||
- testing:arm64
|
||||
- igt:arm64
|
||||
|
||||
|
|
@ -64,37 +63,10 @@
|
|||
dependencies:
|
||||
- testing:x86_64
|
||||
needs:
|
||||
- alpine/x86_64_lava_ssh_client
|
||||
- debian/x86_64_test-gl
|
||||
- python-artifacts
|
||||
- testing:x86_64
|
||||
- igt:x86_64
|
||||
|
||||
.baremetal-igt-arm64:
|
||||
extends:
|
||||
- .baremetal-test-arm64-gl
|
||||
- .use-debian/baremetal_arm64_test-gl
|
||||
- .allow_failure_lockdep
|
||||
timeout: "1h30m"
|
||||
rules:
|
||||
- !reference [.scheduled_pipeline-rules, rules]
|
||||
- !reference [.google-freedreno-farm-rules, rules]
|
||||
- when: on_success
|
||||
variables:
|
||||
FDO_CI_CONCURRENT: 10
|
||||
HWCI_TEST_SCRIPT: "/install/igt_runner.sh"
|
||||
S3_ARTIFACT_NAME: "arm64/kernel-files"
|
||||
BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/Image.gz
|
||||
BM_CMDLINE: "ip=dhcp console=ttyMSM0,115200n8 $BM_KERNEL_EXTRA_ARGS root=/dev/nfs rw nfsrootdebug nfsroot=,tcp,nfsvers=4.2 init=/init $BM_KERNELARGS"
|
||||
FARM: google
|
||||
needs:
|
||||
- debian/baremetal_arm64_test-gl
|
||||
- job: testing:arm64
|
||||
artifacts: false
|
||||
- igt:arm64
|
||||
tags:
|
||||
- $RUNNER_TAG
|
||||
|
||||
.software-driver:
|
||||
stage: software-driver
|
||||
extends:
|
||||
|
|
@ -110,6 +82,7 @@
|
|||
- !reference [default, before_script]
|
||||
- rm -rf install
|
||||
- tar -xf artifacts/install.tar
|
||||
- mkdir -p /kernel
|
||||
script:
|
||||
- ln -sf $CI_PROJECT_DIR/install /install
|
||||
- mv install/bzImage /kernel/bzImage
|
||||
|
|
@ -127,6 +100,7 @@
|
|||
DRIVER_NAME: msm
|
||||
BOOT_METHOD: depthcharge
|
||||
KERNEL_IMAGE_TYPE: ""
|
||||
LAVA_FIRMWARE: qcom-lava
|
||||
|
||||
msm:sc7180-trogdor-lazor-limozeen:
|
||||
extends:
|
||||
|
|
@ -150,40 +124,43 @@ msm:sc7180-trogdor-kingoftown:
|
|||
|
||||
msm:apq8016:
|
||||
extends:
|
||||
- .baremetal-igt-arm64
|
||||
- .lava-igt:arm64
|
||||
stage: msm
|
||||
parallel: 3
|
||||
variables:
|
||||
DEVICE_TYPE: apq8016-sbc-usb-host
|
||||
BOOT_METHOD: fastboot
|
||||
DEVICE_TYPE: dragonboard-410c
|
||||
DRIVER_NAME: msm
|
||||
BM_DTB: https://${PIPELINE_ARTIFACTS_BASE}/arm64/${DEVICE_TYPE}.dtb
|
||||
DTB: apq8016-sbc-usb-host
|
||||
FARM: collabora
|
||||
GPU_VERSION: apq8016
|
||||
# disabling unused clocks congests with the MDSS runtime PM trying to
|
||||
# disable those clocks and causes boot to fail.
|
||||
# Reproducer: DRM_MSM=y, DRM_I2C_ADV7511=m
|
||||
BM_KERNEL_EXTRA_ARGS: clk_ignore_unused
|
||||
RUNNER_TAG: google-freedreno-db410c
|
||||
script:
|
||||
- ./install/bare-metal/fastboot.sh || exit $?
|
||||
KERNEL_IMAGE_NAME: "Image.gz"
|
||||
KERNEL_IMAGE_TYPE: ""
|
||||
RUNNER_TAG: mesa-ci-x86-64-lava-dragonboard-410c
|
||||
LAVA_FIRMWARE: qcom-lava
|
||||
|
||||
msm:apq8096:
|
||||
extends:
|
||||
- .baremetal-igt-arm64
|
||||
- .lava-igt:arm64
|
||||
stage: msm
|
||||
parallel: 3
|
||||
variables:
|
||||
DEVICE_TYPE: apq8096-db820c
|
||||
BOOT_METHOD: fastboot
|
||||
DEVICE_TYPE: dragonboard-820c
|
||||
DRIVER_NAME: msm
|
||||
BM_KERNEL_EXTRA_ARGS: maxcpus=2
|
||||
BM_DTB: https://${PIPELINE_ARTIFACTS_BASE}/arm64/${DEVICE_TYPE}.dtb
|
||||
DTB: apq8096-db820c
|
||||
FARM: collabora
|
||||
GPU_VERSION: apq8096
|
||||
RUNNER_TAG: google-freedreno-db820c
|
||||
script:
|
||||
- ./install/bare-metal/fastboot.sh || exit $?
|
||||
KERNEL_IMAGE_NAME: "Image.gz"
|
||||
KERNEL_IMAGE_TYPE: ""
|
||||
RUNNER_TAG: mesa-ci-x86-64-lava-dragonboard-820c
|
||||
LAVA_FIRMWARE: qcom-lava
|
||||
|
||||
msm:sm8350-hdk:
|
||||
extends:
|
||||
- .lava-igt:arm64
|
||||
stage: msm
|
||||
parallel: 4
|
||||
parallel: 2
|
||||
variables:
|
||||
BOOT_METHOD: fastboot
|
||||
DEVICE_TYPE: sm8350-hdk
|
||||
|
|
@ -194,11 +171,14 @@ msm:sm8350-hdk:
|
|||
KERNEL_IMAGE_NAME: "Image.gz"
|
||||
KERNEL_IMAGE_TYPE: ""
|
||||
RUNNER_TAG: mesa-ci-x86-64-lava-sm8350-hdk
|
||||
LAVA_FIRMWARE: qcom-lava
|
||||
LAVA_FASTBOOT_CMD: "set_active a"
|
||||
|
||||
.rockchip-device:
|
||||
variables:
|
||||
DTB: ${DEVICE_TYPE}
|
||||
BOOT_METHOD: depthcharge
|
||||
LAVA_FIRMWARE: arm
|
||||
|
||||
.rockchip-display:
|
||||
stage: rockchip
|
||||
|
|
@ -226,6 +206,19 @@ msm:sm8350-hdk:
|
|||
KERNEL_IMAGE_TYPE: ""
|
||||
RUNNER_TAG: mesa-ci-x86-64-lava-rk3399-gru-kevin
|
||||
|
||||
.rk3588:
|
||||
extends:
|
||||
- .lava-igt:arm64
|
||||
- .rockchip-device
|
||||
parallel: 2
|
||||
variables:
|
||||
DEVICE_TYPE: rk3588-rock-5b
|
||||
GPU_VERSION: rk3588
|
||||
BOOT_METHOD: u-boot
|
||||
KERNEL_IMAGE_NAME: Image
|
||||
KERNEL_IMAGE_TYPE: "image"
|
||||
RUNNER_TAG: mesa-ci-x86-64-lava-rk3588-rock-5b
|
||||
|
||||
rockchip:rk3288:
|
||||
extends:
|
||||
- .rk3288
|
||||
|
|
@ -246,6 +239,16 @@ panfrost:rk3399:
|
|||
- .rk3399
|
||||
- .panfrost-gpu
|
||||
|
||||
rockchip:rk3588:
|
||||
extends:
|
||||
- .rk3588
|
||||
- .rockchip-display
|
||||
|
||||
panthor:rk3588:
|
||||
extends:
|
||||
- .rk3588
|
||||
- .panthor-gpu
|
||||
|
||||
.i915:
|
||||
extends:
|
||||
- .lava-igt:x86_64
|
||||
|
|
@ -255,6 +258,7 @@ panfrost:rk3399:
|
|||
DTB: ""
|
||||
BOOT_METHOD: depthcharge
|
||||
KERNEL_IMAGE_TYPE: ""
|
||||
LAVA_FIRMWARE: i915
|
||||
|
||||
i915:apl:
|
||||
extends:
|
||||
|
|
@ -277,7 +281,7 @@ i915:glk:
|
|||
i915:amly:
|
||||
extends:
|
||||
- .i915
|
||||
parallel: 2
|
||||
parallel: 3
|
||||
variables:
|
||||
DEVICE_TYPE: asus-C433TA-AJ0005-rammus
|
||||
GPU_VERSION: amly
|
||||
|
|
@ -304,11 +308,11 @@ i915:whl:
|
|||
i915:cml:
|
||||
extends:
|
||||
- .i915
|
||||
parallel: 2
|
||||
parallel: 5
|
||||
variables:
|
||||
DEVICE_TYPE: asus-C436FA-Flip-hatch
|
||||
DEVICE_TYPE: acer-chromebox-cxi4-puff
|
||||
GPU_VERSION: cml
|
||||
RUNNER_TAG: mesa-ci-x86-64-lava-asus-C436FA-Flip-hatch
|
||||
RUNNER_TAG: mesa-ci-x86-64-lava-acer-chromebox-cxi4-puff
|
||||
|
||||
i915:tgl:
|
||||
extends:
|
||||
|
|
@ -337,6 +341,7 @@ i915:jsl:
|
|||
DTB: ""
|
||||
BOOT_METHOD: depthcharge
|
||||
KERNEL_IMAGE_TYPE: ""
|
||||
LAVA_FIRMWARE: amdgpu-lava
|
||||
|
||||
amdgpu:stoney:
|
||||
extends:
|
||||
|
|
@ -355,6 +360,7 @@ amdgpu:stoney:
|
|||
DTB: ${DEVICE_TYPE}
|
||||
BOOT_METHOD: depthcharge
|
||||
KERNEL_IMAGE_TYPE: ""
|
||||
LAVA_FIRMWARE: arm
|
||||
|
||||
.mediatek-display:
|
||||
stage: mediatek
|
||||
|
|
@ -371,6 +377,11 @@ amdgpu:stoney:
|
|||
variables:
|
||||
DRIVER_NAME: panfrost
|
||||
|
||||
.panthor-gpu:
|
||||
stage: panthor
|
||||
variables:
|
||||
DRIVER_NAME: panthor
|
||||
|
||||
.mt8173:
|
||||
extends:
|
||||
- .mediatek-device
|
||||
|
|
|
|||
|
|
@ -3,9 +3,10 @@ amdgpu/amd_abm@abm_gradual,Fail
|
|||
amdgpu/amd_abm@backlight_monotonic_abm,Fail
|
||||
amdgpu/amd_abm@backlight_monotonic_basic,Fail
|
||||
amdgpu/amd_abm@dpms_cycle,Fail
|
||||
amdgpu/amd_assr@assr-links,Fail
|
||||
amdgpu/amd_assr@assr-links-dpms,Fail
|
||||
amdgpu/amd_mall@static-screen,Crash
|
||||
amdgpu/amd_assr@assr-links,Fail
|
||||
amdgpu/amd_basic@cs-gfx-with-IP-GFX,Fail
|
||||
amdgpu/amd_basic@cs-multi-fence-with-IP-GFX,Fail
|
||||
amdgpu/amd_mode_switch@mode-switch-first-last-pipe-2,Crash
|
||||
amdgpu/amd_plane@mpo-pan-nv12,Fail
|
||||
amdgpu/amd_plane@mpo-pan-p010,Fail
|
||||
|
|
@ -13,11 +14,13 @@ amdgpu/amd_plane@mpo-pan-rgb,Crash
|
|||
amdgpu/amd_plane@mpo-scale-nv12,Fail
|
||||
amdgpu/amd_plane@mpo-scale-p010,Fail
|
||||
amdgpu/amd_plane@mpo-scale-rgb,Crash
|
||||
amdgpu/amd_plane@mpo-swizzle-toggle,Fail
|
||||
amdgpu/amd_plane@mpo-swizzle-toggle,Crash
|
||||
amdgpu/amd_uvd_dec@amdgpu_uvd_decode,Fail
|
||||
core_setmaster@master-drop-set-user,Fail
|
||||
kms_addfb_basic@bad-pitch-65536,Fail
|
||||
kms_addfb_basic@bo-too-small,Fail
|
||||
kms_addfb_basic@too-high,Fail
|
||||
kms_async_flips@basic-modeset-with-all-modifiers-formats,Crash
|
||||
kms_atomic_transition@plane-all-modeset-transition-internal-panels,Fail
|
||||
kms_atomic_transition@plane-all-transition,Fail
|
||||
kms_atomic_transition@plane-all-transition-nonblocking,Fail
|
||||
|
|
@ -33,8 +36,10 @@ kms_cursor_crc@cursor-sliding-64x64,Fail
|
|||
kms_cursor_edge_walk@64x64-left-edge,Fail
|
||||
kms_flip@flip-vs-modeset-vs-hang,Fail
|
||||
kms_flip@flip-vs-panning-vs-hang,Fail
|
||||
kms_invalid_mode@int-max-clock,Fail
|
||||
kms_invalid_mode@overflow-vrefresh,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
kms_plane@pixel-format,Fail
|
||||
kms_plane_cursor@primary,Fail
|
||||
kms_plane@pixel-format,Fail
|
||||
kms_rotation_crc@primary-rotation-180,Fail
|
||||
perf@i915-ref-count,Fail
|
||||
|
|
|
|||
|
|
@ -32,3 +32,10 @@ kms_async_flips@async-flip-with-page-flip-events-atomic
|
|||
# IGT Version: 1.29-g33adea9eb
|
||||
# Linux Version: 6.13.0-rc2
|
||||
kms_async_flips@crc-atomic
|
||||
|
||||
# Board Name: hp-11A-G6-EE-grunt
|
||||
# Bug Report: https://gitlab.freedesktop.org/drm/amd/-/issues/4406
|
||||
# Failure Rate: 20
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_async_flips@alternate-sync-async-flip
|
||||
|
|
|
|||
|
|
@ -1,43 +1,18 @@
|
|||
core_setmaster_vs_auth,Fail
|
||||
i915_module_load@load,Fail
|
||||
i915_module_load@reload,Fail
|
||||
i915_module_load@reload-no-display,Fail
|
||||
i915_module_load@resize-bar,Fail
|
||||
i915_pm_rpm@gem-execbuf-stress,Timeout
|
||||
i915_pm_rpm@module-reload,Fail
|
||||
kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc,Timeout
|
||||
kms_fb_coherency@memset-crc,Crash
|
||||
kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail
|
||||
kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu,Timeout
|
||||
kms_lease@lease-uevent,Fail
|
||||
kms_plane_alpha_blend@alpha-basic,Fail
|
||||
kms_plane_alpha_blend@alpha-opaque-fb,Fail
|
||||
kms_plane_alpha_blend@alpha-transparent-fb,Fail
|
||||
kms_plane_alpha_blend@constant-alpha-max,Fail
|
||||
kms_plane_scaling@planes-upscale-factor-0-25,Timeout
|
||||
kms_pm_backlight@brightness-with-dpms,Crash
|
||||
kms_pm_backlight@fade,Crash
|
||||
kms_prop_blob@invalid-set-prop-any,Fail
|
||||
kms_properties@connector-properties-legacy,Timeout
|
||||
kms_pm_rpm@modeset-stress-extra-wait,Timeout
|
||||
kms_universal_plane@disable-primary-vs-flip,Timeout
|
||||
perf@i915-ref-count,Fail
|
||||
perf_pmu@module-unload,Fail
|
||||
|
|
|
|||
|
|
@ -1,29 +1,9 @@
|
|||
core_setmaster@master-drop-set-user,Fail
|
||||
i915_module_load@load,Fail
|
||||
i915_module_load@reload,Fail
|
||||
i915_module_load@reload-no-display,Fail
|
||||
i915_module_load@resize-bar,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail
|
||||
kms_flip@flip-vs-wf_vblank-interruptible,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
kms_plane_alpha_blend@alpha-basic,Fail
|
||||
kms_plane_alpha_blend@alpha-opaque-fb,Fail
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
core_setmaster_vs_auth,Fail
|
||||
api_intel_bb@intel-bb-blit-none,Timeout
|
||||
core_setmaster@master-drop-set-user,Fail
|
||||
i915_module_load@load,Fail
|
||||
i915_module_load@reload,Fail
|
||||
i915_module_load@reload-no-display,Fail
|
||||
|
|
@ -8,18 +9,15 @@ i915_pipe_stress@stress-xrgb8888-ytiled,Fail
|
|||
i915_pm_rpm@gem-execbuf-stress,Timeout
|
||||
i915_pm_rpm@module-reload,Fail
|
||||
i915_pm_rpm@system-suspend-execbuf,Timeout
|
||||
kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc,Timeout
|
||||
kms_cursor_crc@cursor-suspend,Timeout
|
||||
kms_fb_coherency@memset-crc,Crash
|
||||
kms_flip@busy-flip,Timeout
|
||||
kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail
|
||||
|
|
@ -31,39 +29,18 @@ kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail
|
|||
kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
kms_pipe_stress@stress-xrgb8888-untiled,Fail
|
||||
kms_pipe_stress@stress-xrgb8888-ytiled,Fail
|
||||
kms_plane_alpha_blend@alpha-basic,Fail
|
||||
kms_plane_alpha_blend@alpha-opaque-fb,Fail
|
||||
kms_plane_alpha_blend@alpha-transparent-fb,Fail
|
||||
kms_plane_alpha_blend@constant-alpha-max,Fail
|
||||
kms_plane_scaling@planes-upscale-factor-0-25,Timeout
|
||||
kms_pm_backlight@brightness-with-dpms,Crash
|
||||
kms_pm_backlight@fade,Crash
|
||||
kms_prop_blob@invalid-set-prop-any,Fail
|
||||
kms_properties@connector-properties-legacy,Timeout
|
||||
kms_pm_rpm@basic-rte,Fail
|
||||
kms_psr2_sf@cursor-plane-update-sf,Fail
|
||||
kms_psr2_sf@overlay-plane-update-continuous-sf,Fail
|
||||
kms_psr2_sf@overlay-plane-update-sf-dmg-area,Fail
|
||||
kms_psr2_sf@overlay-primary-update-sf-dmg-area,Fail
|
||||
kms_psr2_sf@plane-move-sf-dmg-area,Fail
|
||||
kms_psr2_sf@primary-plane-update-sf-dmg-area,Fail
|
||||
kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb,Fail
|
||||
kms_psr2_sf@psr2-cursor-plane-update-sf,Fail
|
||||
kms_psr2_sf@psr2-overlay-plane-update-continuous-sf,Fail
|
||||
kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area,Fail
|
||||
kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area,Fail
|
||||
kms_psr2_sf@psr2-plane-move-sf-dmg-area,Fail
|
||||
kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area,Fail
|
||||
kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb,Fail
|
||||
kms_psr2_su@page_flip-NV12,Fail
|
||||
kms_psr2_su@page_flip-P010,Fail
|
||||
kms_setmode@basic,Fail
|
||||
kms_universal_plane@disable-primary-vs-flip,Timeout
|
||||
kms_psr2_sf@primary-plane-update-sf-dmg-area,Fail
|
||||
perf@i915-ref-count,Fail
|
||||
perf_pmu@module-unload,Fail
|
||||
perf_pmu@rc6,Crash
|
||||
|
|
|
|||
|
|
@ -32,3 +32,10 @@ kms_async_flips@crc
|
|||
# IGT Version: 1.29-g33adea9eb
|
||||
# Linux Version: 6.13.0-rc2
|
||||
gen9_exec_parse@unaligned-access
|
||||
|
||||
# Board Name: asus-C436FA-Flip-hatch
|
||||
# Bug Report: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14625
|
||||
# Failure Rate: 100
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
perf_pmu@most-busy-check-all
|
||||
|
|
|
|||
|
|
@ -4,41 +4,31 @@ i915_module_load@load,Fail
|
|||
i915_module_load@reload,Fail
|
||||
i915_module_load@reload-no-display,Fail
|
||||
i915_module_load@resize-bar,Fail
|
||||
kms_dirtyfb@default-dirtyfb-ioctl,Fail
|
||||
kms_dirtyfb@drrs-dirtyfb-ioctl,Fail
|
||||
kms_dirtyfb@fbc-dirtyfb-ioctl,Fail
|
||||
kms_flip@blocking-wf_vblank,Fail
|
||||
kms_flip@wf_vblank-ts-check,Fail
|
||||
kms_flip@wf_vblank-ts-check-interruptible,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail
|
||||
kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu,Timeout
|
||||
kms_flip@wf_vblank-ts-check,Fail
|
||||
kms_flip@wf_vblank-ts-check-interruptible,Fail
|
||||
kms_frontbuffer_tracking@fbcdrrs-tiling-linear,Fail
|
||||
kms_frontbuffer_tracking@fbc-tiling-linear,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
kms_plane_alpha_blend@alpha-opaque-fb,Fail
|
||||
kms_plane_scaling@planes-upscale-factor-0-25,Timeout
|
||||
kms_pm_backlight@brightness-with-dpms,Crash
|
||||
kms_pm_backlight@fade,Crash
|
||||
kms_prop_blob@invalid-set-prop-any,Fail
|
||||
kms_properties@connector-properties-legacy,Timeout
|
||||
kms_rotation_crc@multiplane-rotation,Fail
|
||||
kms_rotation_crc@multiplane-rotation-cropping-top,Fail
|
||||
kms_universal_plane@disable-primary-vs-flip,Timeout
|
||||
perf@non-zero-reason,Timeout
|
||||
sysfs_heartbeat_interval@long,Timeout
|
||||
|
|
|
|||
|
|
@ -1,45 +1,24 @@
|
|||
core_setmaster@master-drop-set-root,Fail
|
||||
drm_fdinfo@busy-check-all,Fail
|
||||
i915_module_load@load,Fail
|
||||
i915_module_load@reload,Fail
|
||||
i915_module_load@reload-no-display,Fail
|
||||
i915_module_load@resize-bar,Fail
|
||||
i915_pm_rpm@gem-execbuf-stress,Timeout
|
||||
i915_pm_rpm@module-reload,Fail
|
||||
kms_flip@dpms-off-confusion,Fail
|
||||
kms_flip@nonexisting-fb,Fail
|
||||
kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,UnexpectedImprovement(Skip)
|
||||
kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
kms_pm_rpm@modeset-stress-extra-wait,Timeout
|
||||
kms_rotation_crc@bad-pixel-format,Fail
|
||||
kms_rotation_crc@multiplane-rotation,Fail
|
||||
kms_rotation_crc@multiplane-rotation-cropping-bottom,Fail
|
||||
kms_rotation_crc@multiplane-rotation-cropping-top,Fail
|
||||
perf@i915-ref-count,Fail
|
||||
perf_pmu@module-unload,Fail
|
||||
perf_pmu@most-busy-idle-check-all,Fail
|
||||
perf_pmu@rc6,Crash
|
||||
prime_busy@before-wait,Fail
|
||||
sysfs_heartbeat_interval@long,Timeout
|
||||
sysfs_heartbeat_interval@off,Timeout
|
||||
sysfs_preempt_timeout@off,Timeout
|
||||
|
|
|
|||
|
|
@ -1,11 +1,12 @@
|
|||
core_setmaster@master-drop-set-user,Fail
|
||||
i915_module_load@load,Fail
|
||||
i915_module_load@reload,Fail
|
||||
i915_module_load@reload-no-display,Fail
|
||||
i915_module_load@resize-bar,Fail
|
||||
i915_pm_rpm@gem-execbuf-stress,Timeout
|
||||
kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail
|
||||
|
|
@ -17,6 +18,8 @@ perf@i915-ref-count,Fail
|
|||
perf_pmu@busy-accuracy-50,Fail
|
||||
perf_pmu@module-unload,Fail
|
||||
perf_pmu@rc6,Crash
|
||||
prime_busy@after-wait,Fail
|
||||
prime_busy@before,Fail
|
||||
sysfs_heartbeat_interval@long,Timeout
|
||||
sysfs_heartbeat_interval@off,Timeout
|
||||
sysfs_preempt_timeout@off,Timeout
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
api_intel_allocator@reopen,Timeout
|
||||
api_intel_bb@destroy-bb,Timeout
|
||||
core_hotunplug@hotrebind-lateclose,Timeout
|
||||
core_setmaster@master-drop-set-user,Fail
|
||||
drm_read@short-buffer-block,Timeout
|
||||
dumb_buffer@map-valid,Timeout
|
||||
i915_module_load@load,Fail
|
||||
i915_module_load@reload,Fail
|
||||
i915_module_load@reload-no-display,Fail
|
||||
i915_module_load@resize-bar,Fail
|
||||
i915_pm_rpm@gem-execbuf-stress,Timeout
|
||||
i915_pm_rps@engine-order,Timeout
|
||||
i915_pm_rps@waitboost,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
kms_rotation_crc@multiplane-rotation,Fail
|
||||
perf@i915-ref-count,Fail
|
||||
|
|
@ -17,7 +17,6 @@ perf_pmu@enable-race,Timeout
|
|||
perf_pmu@module-unload,Fail
|
||||
perf_pmu@rc6,Crash
|
||||
perf_pmu@semaphore-wait-idle,Timeout
|
||||
prime_busy@before,Fail
|
||||
prime_mmap@test_refcounting,Timeout
|
||||
sriov_basic@enable-vfs-bind-unbind-each-numvfs-all,Timeout
|
||||
syncobj_basic@illegal-fd-to-handle,Timeout
|
||||
|
|
|
|||
6
drivers/gpu/drm/ci/xfails/i915-tgl-flakes.txt
Normal file
6
drivers/gpu/drm/ci/xfails/i915-tgl-flakes.txt
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# Board Name: acer-cp514-2h-1130g7-volteer
|
||||
# Bug Report: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14624
|
||||
# Failure Rate: 100
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
perf@gen12-unprivileged-single-ctx-counters
|
||||
|
|
@ -6,17 +6,17 @@ i915_module_load@resize-bar,Fail
|
|||
i915_pm_rpm@gem-execbuf-stress,Timeout
|
||||
i915_pm_rpm@module-reload,Fail
|
||||
i915_pm_rpm@system-suspend-execbuf,Timeout
|
||||
kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc,Timeout
|
||||
kms_cursor_crc@cursor-suspend,Timeout
|
||||
kms_dirtyfb@default-dirtyfb-ioctl,Fail
|
||||
kms_dirtyfb@fbc-dirtyfb-ioctl,Fail
|
||||
kms_fb_coherency@memset-crc,Crash
|
||||
kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail
|
||||
|
|
@ -26,10 +26,9 @@ kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail
|
|||
kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail
|
||||
kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu,Timeout
|
||||
kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail
|
||||
kms_frontbuffer_tracking@fbc-tiling-linear,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
kms_plane_alpha_blend@alpha-basic,Fail
|
||||
|
|
@ -37,8 +36,6 @@ kms_plane_alpha_blend@alpha-opaque-fb,Fail
|
|||
kms_plane_alpha_blend@alpha-transparent-fb,Fail
|
||||
kms_plane_alpha_blend@constant-alpha-max,Fail
|
||||
kms_plane_scaling@planes-upscale-factor-0-25,Timeout
|
||||
kms_pm_backlight@brightness-with-dpms,Crash
|
||||
kms_pm_backlight@fade,Crash
|
||||
kms_prop_blob@invalid-set-prop-any,Fail
|
||||
kms_properties@connector-properties-legacy,Timeout
|
||||
kms_universal_plane@disable-primary-vs-flip,Timeout
|
||||
|
|
|
|||
|
|
@ -1,7 +1,8 @@
|
|||
core_setmaster@master-drop-set-root,Fail
|
||||
core_setmaster@master-drop-set-shared-fd,Fail
|
||||
core_setmaster@master-drop-set-user,Fail
|
||||
kms_3d,Fail
|
||||
kms_bw@connected-linear-tiling-1-displays-1920x1080p,Fail
|
||||
kms_bw@connected-linear-tiling-1-displays-2560x1440p,Fail
|
||||
kms_bw@connected-linear-tiling-1-displays-3840x2160p,Fail
|
||||
kms_bw@connected-linear-tiling-2-displays-1920x1080p,Fail
|
||||
kms_bw@connected-linear-tiling-2-displays-2160x1440p,Fail
|
||||
kms_bw@connected-linear-tiling-2-displays-2560x1440p,Fail
|
||||
|
|
@ -14,9 +15,7 @@ kms_bw@linear-tiling-2-displays-1920x1080p,Fail
|
|||
kms_bw@linear-tiling-2-displays-2160x1440p,Fail
|
||||
kms_bw@linear-tiling-2-displays-2560x1440p,Fail
|
||||
kms_bw@linear-tiling-2-displays-3840x2160p,Fail
|
||||
kms_color@invalid-gamma-lut-sizes,Fail
|
||||
kms_cursor_legacy@cursor-vs-flip-atomic,Fail
|
||||
kms_cursor_legacy@cursor-vs-flip-legacy,Fail
|
||||
kms_cursor_legacy@flip-vs-cursor-atomic,Fail
|
||||
kms_cursor_legacy@flip-vs-cursor-legacy,Fail
|
||||
kms_cursor_legacy@flip-vs-cursor-toggle,Fail
|
||||
|
|
@ -24,9 +23,9 @@ kms_cursor_legacy@flip-vs-cursor-varying-size,Fail
|
|||
kms_flip@basic-plain-flip,Fail
|
||||
kms_flip@dpms-off-confusion,Fail
|
||||
kms_flip@dpms-off-confusion-interruptible,Fail
|
||||
kms_flip@flip-vs-absolute-wf_vblank,Fail
|
||||
kms_flip@flip-vs-absolute-wf_vblank-interruptible,Fail
|
||||
kms_flip@flip-vs-blocking-wf-vblank,Fail
|
||||
kms_flip@flip-vs-dpms-on-nop,Fail
|
||||
kms_flip@flip-vs-dpms-on-nop-interruptible,Fail
|
||||
kms_flip@flip-vs-expired-vblank,Fail
|
||||
kms_flip@flip-vs-expired-vblank-interruptible,Fail
|
||||
kms_flip@flip-vs-modeset-vs-hang,Fail
|
||||
|
|
@ -40,5 +39,4 @@ kms_flip@plain-flip-fb-recreate-interruptible,Fail
|
|||
kms_flip@plain-flip-interruptible,Fail
|
||||
kms_flip@plain-flip-ts-check,Fail
|
||||
kms_flip@plain-flip-ts-check-interruptible,Fail
|
||||
kms_invalid_mode@overflow-vrefresh,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
|
|
|
|||
|
|
@ -53,3 +53,38 @@ kms_bw@connected-linear-tiling-1-displays-2160x1440p
|
|||
# IGT Version: 1.30-g04bedb923
|
||||
# Linux Version: 6.14.0-rc4
|
||||
kms_flip@flip-vs-wf_vblank-interruptible
|
||||
|
||||
# Board Name: mt8173-elm-hana
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/7559dd68-c9dd-410f-880f-201679e2dd54@collabora.com/T/#u
|
||||
# Failure Rate: 20
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_flip@blocking-wf_vblank
|
||||
|
||||
# Board Name: mt8173-elm-hana
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/953ab66e-9dda-4003-9b98-9e0d81e18a1f@collabora.com/T/#u
|
||||
# Failure Rate: 40
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_flip@busy-flip
|
||||
|
||||
# Board Name: mt8173-elm-hana
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/6ab7f59c-042e-4c7a-baaa-86c7d47ab308@collabora.com/
|
||||
# Failure Rate: 40
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_flip@flip-vs-rmfb
|
||||
|
||||
# Board Name: mt8173-elm-hana
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/30b3f8b0-3409-4329-bb60-b6287e1a439d@collabora.com/
|
||||
# Failure Rate: 60
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_atomic_transition@plane-all-modeset-transition-internal-panels
|
||||
|
||||
# Board Name: mt8173-elm-hana
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/4c9e1501-52cd-4659-a894-8a2ac58c3996@collabora.com/
|
||||
# Failure Rate: 40
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_flip@absolute-wf_vblank
|
||||
|
|
|
|||
|
|
@ -1,5 +1,9 @@
|
|||
core_setmaster@master-drop-set-user,Fail
|
||||
kms_3d,Fail
|
||||
kms_cursor_legacy@forked-move,Fail
|
||||
kms_cursor_legacy@single-bo,Fail
|
||||
kms_force_connector_basic@force-edid,Fail
|
||||
kms_hdmi_inject@inject-4k,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
msm/msm_mapping@memptrs,Fail
|
||||
msm/msm_mapping@ring,Fail
|
||||
|
|
|
|||
|
|
@ -1,2 +1,4 @@
|
|||
core_setmaster@master-drop-set-user,Fail
|
||||
kms_3d,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
msm/msm_mapping@memptrs,Fail
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
core_setmaster@master-drop-set-user,Fail
|
||||
kms_color@ctm-0-25,Fail
|
||||
kms_color@ctm-0-50,Fail
|
||||
kms_color@ctm-0-75,Fail
|
||||
|
|
@ -14,8 +15,8 @@ kms_flip@flip-vs-modeset-vs-hang,Fail
|
|||
kms_flip@flip-vs-panning-vs-hang,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail
|
||||
kms_plane@pixel-format,Fail
|
||||
kms_plane@pixel-format-source-clamping,Fail
|
||||
kms_plane_alpha_blend@alpha-7efc,Fail
|
||||
kms_plane_alpha_blend@coverage-7efc,Fail
|
||||
kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail
|
||||
kms_plane@pixel-format,Fail
|
||||
kms_plane@pixel-format-source-clamping,Fail
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
core_setmaster@master-drop-set-user,Fail
|
||||
kms_color@ctm-0-25,Fail
|
||||
kms_color@ctm-0-50,Fail
|
||||
kms_color@ctm-0-75,Fail
|
||||
|
|
@ -14,8 +15,8 @@ kms_flip@flip-vs-modeset-vs-hang,Fail
|
|||
kms_flip@flip-vs-panning-vs-hang,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail
|
||||
kms_plane@pixel-format,Fail
|
||||
kms_plane@pixel-format-source-clamping,Fail
|
||||
kms_plane_alpha_blend@alpha-7efc,Fail
|
||||
kms_plane_alpha_blend@coverage-7efc,Fail
|
||||
kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail
|
||||
kms_plane@pixel-format,Fail
|
||||
kms_plane@pixel-format-source-clamping,Fail
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
core_setmaster@master-drop-set-user,Fail
|
||||
kms_3d,Fail
|
||||
kms_cursor_legacy@forked-bo,Fail
|
||||
kms_cursor_legacy@forked-move,Fail
|
||||
|
|
|
|||
|
|
@ -1,2 +1,3 @@
|
|||
core_setmaster@master-drop-set-user,Fail
|
||||
panfrost/panfrost_prime@gem-prime-import,Fail
|
||||
panfrost/panfrost_submit@pan-submit-error-bad-requirements,Fail
|
||||
|
|
|
|||
|
|
@ -1,2 +1,3 @@
|
|||
core_setmaster@master-drop-set-user,Crash
|
||||
panfrost/panfrost_prime@gem-prime-import,Crash
|
||||
panfrost/panfrost_submit@pan-submit-error-bad-requirements,Crash
|
||||
|
|
|
|||
|
|
@ -1,2 +1,3 @@
|
|||
core_setmaster@master-drop-set-user,Fail
|
||||
panfrost/panfrost_prime@gem-prime-import,Fail
|
||||
panfrost/panfrost_submit@pan-submit-error-bad-requirements,Fail
|
||||
|
|
|
|||
5
drivers/gpu/drm/ci/xfails/panthor-rk3588-fails.txt
Normal file
5
drivers/gpu/drm/ci/xfails/panthor-rk3588-fails.txt
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
core_hotunplug@hotreplug,Fail
|
||||
core_hotunplug@hotreplug-lateclose,Fail
|
||||
core_hotunplug@hotunplug-rescan,Fail
|
||||
core_hotunplug@unplug-rescan,Fail
|
||||
core_setmaster@master-drop-set-user,Fail
|
||||
20
drivers/gpu/drm/ci/xfails/panthor-rk3588-skips.txt
Normal file
20
drivers/gpu/drm/ci/xfails/panthor-rk3588-skips.txt
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
# Skip driver specific tests
|
||||
^amdgpu.*
|
||||
^msm.*
|
||||
nouveau_.*
|
||||
^v3d.*
|
||||
^vc4.*
|
||||
^vmwgfx*
|
||||
|
||||
# Skip intel specific tests
|
||||
gem_.*
|
||||
i915_.*
|
||||
tools_test.*
|
||||
kms_dp_link_training.*
|
||||
|
||||
# Panfrost is not a KMS driver, so skip the KMS tests
|
||||
kms_.*
|
||||
|
||||
# Skip display functionality tests for GPU-only drivers
|
||||
dumb_buffer.*
|
||||
fbdev.*
|
||||
|
|
@ -2,8 +2,17 @@ core_setmaster@master-drop-set-root,Crash
|
|||
core_setmaster@master-drop-set-shared-fd,Crash
|
||||
core_setmaster@master-drop-set-user,Crash
|
||||
core_setmaster_vs_auth,Crash
|
||||
dumb_buffer@create-clear,Crash
|
||||
fbdev@pan,Crash
|
||||
kms_cursor_legacy@basic-flip-before-cursor-legacy,Fail
|
||||
kms_prop_blob@invalid-set-prop,Crash
|
||||
kms_cursor_crc@cursor-dpms,Crash
|
||||
kms_cursor_crc@cursor-sliding-32x32,Crash
|
||||
kms_cursor_legacy@basic-flip-before-cursor-atomic,Crash
|
||||
kms_cursor_legacy@cursor-vs-flip-atomic,Crash
|
||||
kms_flip@basic-flip-vs-wf_vblank,Crash
|
||||
kms_flip@flip-vs-panning-vs-hang,Crash
|
||||
kms_flip@plain-flip-fb-recreate-interruptible,Crash
|
||||
kms_pipe_crc_basic@read-crc-frame-sequence,Crash
|
||||
kms_plane_cursor@overlay,Crash
|
||||
kms_plane_cursor@viewport,Crash
|
||||
kms_prop_blob@invalid-set-prop-any,Crash
|
||||
kms_prop_blob@invalid-set-prop,Crash
|
||||
kms_properties@get_properties-sanity-non-atomic,Fail
|
||||
|
|
|
|||
|
|
@ -32,3 +32,24 @@ kms_flip@plain-flip-ts-check
|
|||
# IGT Version: 1.28-ga73311079
|
||||
# Linux Version: 6.11.0-rc2
|
||||
kms_cursor_crc@cursor-alpha-opaque
|
||||
|
||||
# Board Name: rk3288-veyron-jaq
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/acfd5838-d861-4dd9-97c3-99fffc9bfa04@collabora.com/T/#u
|
||||
# Failure Rate: 40
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_flip@flip-vs-absolute-wf_vblank
|
||||
|
||||
# Board Name: rk3288-veyron-jaq
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/81e13fcc-d916-4eb8-91cd-f74f64f53f72@collabora.com/T/#u
|
||||
# Failure Rate: 40
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_flip@flip-vs-dpms-on-nop-interruptible
|
||||
|
||||
# Board Name: rk3288-veyron-jaq
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/10c5abab-c8fe-4eff-8eed-009038436b49@collabora.com/T/#u
|
||||
# Failure Rate: 20
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_flip@plain-flip-fb-recreate
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
dumb_buffer@create-clear,Crash
|
||||
core_setmaster@master-drop-set-user,Fail
|
||||
kms_atomic_transition@modeset-transition,Fail
|
||||
kms_atomic_transition@modeset-transition-fencing,Fail
|
||||
kms_atomic_transition@plane-toggle-modeset-transition,Fail
|
||||
kms_color@gamma,Fail
|
||||
kms_color@legacy-gamma,Fail
|
||||
kms_cursor_crc@async-cursor-crc-framebuffer-change,Fail
|
||||
kms_cursor_crc@async-cursor-crc-position-change,Fail
|
||||
kms_cursor_crc@cursor-alpha-opaque,Fail
|
||||
kms_cursor_crc@cursor-alpha-transparent,Fail
|
||||
kms_cursor_crc@cursor-dpms,Fail
|
||||
|
|
@ -41,8 +41,11 @@ kms_cursor_legacy@flip-vs-cursor-crc-atomic,Fail
|
|||
kms_cursor_legacy@flip-vs-cursor-crc-legacy,Fail
|
||||
kms_cursor_legacy@flip-vs-cursor-legacy,Fail
|
||||
kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic,Fail
|
||||
kms_flip@basic-flip-vs-dpms,Fail
|
||||
kms_flip@basic-flip-vs-wf_vblank,Fail
|
||||
kms_flip@blocking-wf_vblank,Fail
|
||||
kms_flip@flip-vs-dpms-on-nop,Fail
|
||||
kms_flip@flip-vs-dpms-on-nop-interruptible,Fail
|
||||
kms_flip@flip-vs-modeset-vs-hang,Fail
|
||||
kms_flip@flip-vs-panning,Fail
|
||||
kms_flip@flip-vs-panning-interruptible,Fail
|
||||
|
|
@ -51,7 +54,6 @@ kms_flip@modeset-vs-vblank-race,Fail
|
|||
kms_flip@plain-flip-fb-recreate,Fail
|
||||
kms_flip@plain-flip-fb-recreate-interruptible,Fail
|
||||
kms_flip@plain-flip-ts-check,Fail
|
||||
kms_flip@plain-flip-ts-check-interruptible,Fail
|
||||
kms_flip@wf_vblank-ts-check-interruptible,Fail
|
||||
kms_invalid_mode@int-max-clock,Fail
|
||||
kms_invalid_mode@overflow-vrefresh,Fail
|
||||
|
|
@ -64,11 +66,11 @@ kms_pipe_crc_basic@nonblocking-crc,Fail
|
|||
kms_pipe_crc_basic@nonblocking-crc-frame-sequence,Fail
|
||||
kms_pipe_crc_basic@read-crc,Fail
|
||||
kms_pipe_crc_basic@read-crc-frame-sequence,Fail
|
||||
kms_plane_cursor@primary,Fail
|
||||
kms_plane@pixel-format,Fail
|
||||
kms_plane@pixel-format-source-clamping,Fail
|
||||
kms_plane@plane-panning-bottom-right,Fail
|
||||
kms_plane@plane-panning-top-left,Fail
|
||||
kms_plane@plane-position-covered,Fail
|
||||
kms_plane@plane-position-hole,Fail
|
||||
kms_plane_cursor@primary,Fail
|
||||
kms_universal_plane@universal-plane-functional,Fail
|
||||
|
|
|
|||
|
|
@ -144,3 +144,38 @@ kms_bw@connected-linear-tiling-1-displays-2160x1440p
|
|||
# IGT Version: 1.30-g04bedb923
|
||||
# Linux Version: 6.14.0-rc4
|
||||
kms_bw@linear-tiling-1-displays-3840x2160p
|
||||
|
||||
# Board Name: rk3399-gru-kevin
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/7b6e2e3b-2ea2-4cd7-92a5-68d23a63e426@collabora.com/T/#u
|
||||
# Failure Rate: 60
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_color@gamma
|
||||
|
||||
# Board Name: rk3399-gru-kevin
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/e29c2892-08f2-423f-af72-e4d8b207fd1c@collabora.com/T/#u
|
||||
# Failure Rate: 60
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_bw@connected-linear-tiling-1-displays-3840x2160p
|
||||
|
||||
# Board Name: rk3399-gru-kevin
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/ad9ce463-c803-4502-ae89-381a6b6eb19f@collabora.com/T/#u
|
||||
# Failure Rate: 40
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_color@legacy-gamma
|
||||
|
||||
# Board Name: rk3399-gru-kevin
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/59724e10-12ca-4481-b0e4-72d7b6e4dae0@collabora.com/T/#u
|
||||
# Failure Rate: 40
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_flip@plain-flip-ts-check-interruptible
|
||||
|
||||
# Board Name: rk3399-gru-kevin
|
||||
# Bug Report: https://lore.kernel.org/dri-devel/d790db5f-a1ba-47f9-9af0-d3287ef3274c@collabora.com/T/#u
|
||||
# Failure Rate: 20
|
||||
# IGT Version: 2.1-g26ddb59c1
|
||||
# Linux Version: 6.16.0-rc2
|
||||
kms_bw@linear-tiling-2-displays-3840x2160p
|
||||
|
|
|
|||
9
drivers/gpu/drm/ci/xfails/rockchip-rk3588-fails.txt
Normal file
9
drivers/gpu/drm/ci/xfails/rockchip-rk3588-fails.txt
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
core_setmaster@master-drop-set-user,Fail
|
||||
kms_3d,Fail
|
||||
kms_cursor_legacy@forked-bo,Fail
|
||||
kms_cursor_legacy@forked-move,Fail
|
||||
kms_cursor_legacy@single-bo,Fail
|
||||
kms_cursor_legacy@single-move,Fail
|
||||
kms_cursor_legacy@torture-bo,Fail
|
||||
kms_cursor_legacy@torture-move,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
14
drivers/gpu/drm/ci/xfails/rockchip-rk3588-skips.txt
Normal file
14
drivers/gpu/drm/ci/xfails/rockchip-rk3588-skips.txt
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Skip driver specific tests
|
||||
^amdgpu.*
|
||||
^msm.*
|
||||
nouveau_.*
|
||||
^panfrost.*
|
||||
^v3d.*
|
||||
^vc4.*
|
||||
^vmwgfx*
|
||||
|
||||
# Skip intel specific tests
|
||||
gem_.*
|
||||
i915_.*
|
||||
tools_test.*
|
||||
kms_dp_link_training.*
|
||||
|
|
@ -2,11 +2,6 @@ kms_addfb_basic@bad-pitch-65536,Fail
|
|||
kms_addfb_basic@bo-too-small,Fail
|
||||
kms_addfb_basic@size-max,Fail
|
||||
kms_addfb_basic@too-high,Fail
|
||||
kms_atomic_transition@plane-primary-toggle-with-vblank-wait,Fail
|
||||
kms_bw@connected-linear-tiling-1-displays-1920x1080p,Fail
|
||||
kms_bw@connected-linear-tiling-1-displays-2160x1440p,Fail
|
||||
kms_bw@connected-linear-tiling-1-displays-2560x1440p,Fail
|
||||
kms_bw@connected-linear-tiling-1-displays-3840x2160p,Fail
|
||||
kms_bw@connected-linear-tiling-10-displays-1920x1080p,Fail
|
||||
kms_bw@connected-linear-tiling-10-displays-2160x1440p,Fail
|
||||
kms_bw@connected-linear-tiling-10-displays-2560x1440p,Fail
|
||||
|
|
@ -35,6 +30,10 @@ kms_bw@connected-linear-tiling-16-displays-1920x1080p,Fail
|
|||
kms_bw@connected-linear-tiling-16-displays-2160x1440p,Fail
|
||||
kms_bw@connected-linear-tiling-16-displays-2560x1440p,Fail
|
||||
kms_bw@connected-linear-tiling-16-displays-3840x2160p,Fail
|
||||
kms_bw@connected-linear-tiling-1-displays-1920x1080p,Fail
|
||||
kms_bw@connected-linear-tiling-1-displays-2160x1440p,Fail
|
||||
kms_bw@connected-linear-tiling-1-displays-2560x1440p,Fail
|
||||
kms_bw@connected-linear-tiling-1-displays-3840x2160p,Fail
|
||||
kms_bw@connected-linear-tiling-2-displays-1920x1080p,Fail
|
||||
kms_bw@connected-linear-tiling-2-displays-2160x1440p,Fail
|
||||
kms_bw@connected-linear-tiling-2-displays-2560x1440p,Fail
|
||||
|
|
@ -67,10 +66,6 @@ kms_bw@connected-linear-tiling-9-displays-1920x1080p,Fail
|
|||
kms_bw@connected-linear-tiling-9-displays-2160x1440p,Fail
|
||||
kms_bw@connected-linear-tiling-9-displays-2560x1440p,Fail
|
||||
kms_bw@connected-linear-tiling-9-displays-3840x2160p,Fail
|
||||
kms_bw@linear-tiling-1-displays-1920x1080p,Fail
|
||||
kms_bw@linear-tiling-1-displays-2160x1440p,Fail
|
||||
kms_bw@linear-tiling-1-displays-2560x1440p,Fail
|
||||
kms_bw@linear-tiling-1-displays-3840x2160p,Fail
|
||||
kms_bw@linear-tiling-10-displays-1920x1080p,Fail
|
||||
kms_bw@linear-tiling-10-displays-2160x1440p,Fail
|
||||
kms_bw@linear-tiling-10-displays-2560x1440p,Fail
|
||||
|
|
@ -99,6 +94,10 @@ kms_bw@linear-tiling-16-displays-1920x1080p,Fail
|
|||
kms_bw@linear-tiling-16-displays-2160x1440p,Fail
|
||||
kms_bw@linear-tiling-16-displays-2560x1440p,Fail
|
||||
kms_bw@linear-tiling-16-displays-3840x2160p,Fail
|
||||
kms_bw@linear-tiling-1-displays-1920x1080p,Fail
|
||||
kms_bw@linear-tiling-1-displays-2160x1440p,Fail
|
||||
kms_bw@linear-tiling-1-displays-2560x1440p,Fail
|
||||
kms_bw@linear-tiling-1-displays-3840x2160p,Fail
|
||||
kms_bw@linear-tiling-2-displays-1920x1080p,Fail
|
||||
kms_bw@linear-tiling-2-displays-2160x1440p,Fail
|
||||
kms_bw@linear-tiling-2-displays-2560x1440p,Fail
|
||||
|
|
@ -131,60 +130,11 @@ kms_bw@linear-tiling-9-displays-1920x1080p,Fail
|
|||
kms_bw@linear-tiling-9-displays-2160x1440p,Fail
|
||||
kms_bw@linear-tiling-9-displays-2560x1440p,Fail
|
||||
kms_bw@linear-tiling-9-displays-3840x2160p,Fail
|
||||
kms_flip@absolute-wf_vblank,Fail
|
||||
kms_flip@absolute-wf_vblank-interruptible,Fail
|
||||
kms_flip@basic-flip-vs-wf_vblank,Fail
|
||||
kms_flip@blocking-absolute-wf_vblank,Fail
|
||||
kms_flip@blocking-absolute-wf_vblank-interruptible,Fail
|
||||
kms_flip@blocking-wf_vblank,Fail
|
||||
kms_flip@busy-flip,Fail
|
||||
kms_flip@dpms-vs-vblank-race,Fail
|
||||
kms_flip@dpms-vs-vblank-race-interruptible,Fail
|
||||
kms_flip@flip-vs-absolute-wf_vblank,Fail
|
||||
kms_flip@flip-vs-absolute-wf_vblank-interruptible,Fail
|
||||
kms_flip@flip-vs-blocking-wf-vblank,Fail
|
||||
kms_flip@flip-vs-expired-vblank,Fail
|
||||
kms_flip@flip-vs-expired-vblank-interruptible,Fail
|
||||
kms_flip@flip-vs-modeset-vs-hang,Fail
|
||||
kms_flip@flip-vs-panning-vs-hang,Fail
|
||||
kms_flip@flip-vs-wf_vblank-interruptible,Fail
|
||||
kms_flip@modeset-vs-vblank-race,Fail
|
||||
kms_flip@modeset-vs-vblank-race-interruptible,Fail
|
||||
kms_flip@plain-flip-fb-recreate,Fail
|
||||
kms_flip@plain-flip-fb-recreate-interruptible,Fail
|
||||
kms_flip@plain-flip-ts-check,Fail
|
||||
kms_flip@plain-flip-ts-check-interruptible,Fail
|
||||
kms_flip@wf_vblank-ts-check,Fail
|
||||
kms_flip@wf_vblank-ts-check-interruptible,Fail
|
||||
kms_invalid_mode@int-max-clock,Fail
|
||||
kms_invalid_mode@overflow-vrefresh,Fail
|
||||
kms_lease@cursor-implicit-plane,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
kms_lease@page-flip-implicit-plane,Fail
|
||||
kms_lease@setcrtc-implicit-plane,Fail
|
||||
kms_lease@simple-lease,Fail
|
||||
kms_sequence@get-busy,Fail
|
||||
kms_sequence@get-forked,Fail
|
||||
kms_sequence@get-forked-busy,Fail
|
||||
kms_sequence@get-idle,Fail
|
||||
kms_sequence@queue-busy,Fail
|
||||
kms_sequence@queue-idle,Fail
|
||||
kms_setmode@basic,Fail
|
||||
kms_vblank@accuracy-idle,Fail
|
||||
kms_vblank@crtc-id,Fail
|
||||
kms_vblank@invalid,Fail
|
||||
kms_vblank@query-busy,Fail
|
||||
kms_vblank@query-forked,Fail
|
||||
kms_vblank@query-forked-busy,Fail
|
||||
kms_vblank@query-idle,Fail
|
||||
kms_vblank@ts-continuation-dpms-rpm,Fail
|
||||
kms_vblank@ts-continuation-dpms-suspend,Fail
|
||||
kms_vblank@ts-continuation-idle,Fail
|
||||
kms_vblank@ts-continuation-modeset,Fail
|
||||
kms_vblank@ts-continuation-modeset-rpm,Fail
|
||||
kms_vblank@ts-continuation-suspend,Fail
|
||||
kms_vblank@wait-busy,Fail
|
||||
kms_vblank@wait-forked,Fail
|
||||
kms_vblank@wait-forked-busy,Fail
|
||||
kms_vblank@wait-idle,Fail
|
||||
perf@i915-ref-count,Fail
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@ kms_flip@flip-vs-panning-vs-hang,Fail
|
|||
kms_flip@flip-vs-suspend,Fail
|
||||
kms_flip@flip-vs-suspend-interruptible,Fail
|
||||
kms_lease@lease-uevent,Fail
|
||||
kms_plane@pixel-format-source-clamping,Timeout
|
||||
kms_plane@pixel-format,Timeout
|
||||
kms_writeback@writeback-check-output,Fail
|
||||
kms_writeback@writeback-check-output-XRGB2101010,Fail
|
||||
kms_writeback@writeback-fb-id,Fail
|
||||
|
|
|
|||
|
|
@ -119,8 +119,7 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
|
|||
dpi_data_format = DPI_COLOR_18BIT_CFG_2;
|
||||
venc_data_width = VENC_IN_COLOR_18B;
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB666_PACKED:
|
||||
case MIPI_DSI_FMT_RGB565:
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -232,8 +231,7 @@ static int meson_dw_mipi_dsi_host_attach(void *priv_data,
|
|||
break;
|
||||
case MIPI_DSI_FMT_RGB666:
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB666_PACKED:
|
||||
case MIPI_DSI_FMT_RGB565:
|
||||
default:
|
||||
dev_err(mipi_dsi->dev, "invalid pixel format %d\n", device->format);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ adreno-y := \
|
|||
adreno/a6xx_hfi.o \
|
||||
adreno/a6xx_preempt.o \
|
||||
adreno/a8xx_gpu.o \
|
||||
adreno/a8xx_preempt.o \
|
||||
|
||||
adreno-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
|
||||
|
||||
|
|
|
|||
|
|
@ -604,11 +604,9 @@ static int a4xx_pm_suspend(struct msm_gpu *gpu) {
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
|
||||
static u64 a4xx_get_timestamp(struct msm_gpu *gpu)
|
||||
{
|
||||
*value = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO);
|
||||
|
||||
return 0;
|
||||
return gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO);
|
||||
}
|
||||
|
||||
static u64 a4xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)
|
||||
|
|
|
|||
|
|
@ -1435,11 +1435,9 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
|
||||
static u64 a5xx_get_timestamp(struct msm_gpu *gpu)
|
||||
{
|
||||
*value = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO);
|
||||
|
||||
return 0;
|
||||
return gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO);
|
||||
}
|
||||
|
||||
struct a5xx_crashdumper {
|
||||
|
|
@ -1732,6 +1730,7 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
|
|||
struct adreno_gpu *adreno_gpu;
|
||||
struct msm_gpu *gpu;
|
||||
unsigned int nr_rings;
|
||||
u32 speedbin;
|
||||
int ret;
|
||||
|
||||
a5xx_gpu = kzalloc_obj(*a5xx_gpu);
|
||||
|
|
@ -1758,6 +1757,11 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
|
|||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
/* Set the speedbin value that is passed to userspace */
|
||||
if (adreno_read_speedbin(&pdev->dev, &speedbin) || !speedbin)
|
||||
speedbin = 0xffff;
|
||||
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
|
||||
|
||||
msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
|
||||
a5xx_fault_handler);
|
||||
|
||||
|
|
|
|||
|
|
@ -1761,6 +1761,44 @@ static const u32 x285_protect_regs[] = {
|
|||
|
||||
DECLARE_ADRENO_PROTECT(x285_protect, 15);
|
||||
|
||||
static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = {
|
||||
{ REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) },
|
||||
{ REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)},
|
||||
{ REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
|
||||
{ REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
|
||||
{ REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BR) },
|
||||
{ REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) },
|
||||
{ REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) },
|
||||
{ REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) |
|
||||
BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) |
|
||||
BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) },
|
||||
{ REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) |
|
||||
BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) |
|
||||
BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) },
|
||||
{ REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC)},
|
||||
{ REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) },
|
||||
{ REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
|
||||
{ REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
|
||||
{ REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) },
|
||||
};
|
||||
DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist);
|
||||
|
||||
static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
|
||||
{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
|
||||
{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
|
|
@ -1891,6 +1929,185 @@ static const struct adreno_reglist a840_gbif[] = {
|
|||
{ },
|
||||
};
|
||||
|
||||
static const uint32_t a840_pwrup_reglist_regs[] = {
|
||||
REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP,
|
||||
REG_A7XX_SP_READ_SEL,
|
||||
REG_A6XX_UCHE_MODE_CNTL,
|
||||
REG_A8XX_UCHE_VARB_IDLE_TIMEOUT,
|
||||
REG_A8XX_UCHE_GBIF_GX_CONFIG,
|
||||
REG_A8XX_UCHE_CCHE_MODE_CNTL,
|
||||
REG_A8XX_UCHE_CCHE_CACHE_WAYS,
|
||||
REG_A8XX_UCHE_CACHE_WAYS,
|
||||
REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN,
|
||||
REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1,
|
||||
REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN,
|
||||
REG_A8XX_UCHE_CCHE_LPAC_GMEM_RANGE_MIN + 1,
|
||||
REG_A8XX_UCHE_CCHE_TRAP_BASE,
|
||||
REG_A8XX_UCHE_CCHE_TRAP_BASE + 1,
|
||||
REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE,
|
||||
REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE + 1,
|
||||
REG_A8XX_UCHE_HW_DBG_CNTL,
|
||||
REG_A8XX_UCHE_WRITE_THRU_BASE,
|
||||
REG_A8XX_UCHE_WRITE_THRU_BASE + 1,
|
||||
REG_A8XX_UCHE_TRAP_BASE,
|
||||
REG_A8XX_UCHE_TRAP_BASE + 1,
|
||||
REG_A8XX_UCHE_CLIENT_PF,
|
||||
REG_A8XX_RB_CMP_NC_MODE_CNTL,
|
||||
REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN,
|
||||
REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1,
|
||||
REG_A6XX_TPL1_NC_MODE_CNTL,
|
||||
REG_A6XX_TPL1_DBG_ECO_CNTL,
|
||||
REG_A6XX_TPL1_DBG_ECO_CNTL1,
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(0),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18),
|
||||
REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19),
|
||||
};
|
||||
DECLARE_ADRENO_REGLIST_LIST(a840_pwrup_reglist);
|
||||
|
||||
static const u32 a840_ifpc_reglist_regs[] = {
|
||||
REG_A8XX_RBBM_NC_MODE_CNTL,
|
||||
REG_A8XX_RBBM_SLICE_NC_MODE_CNTL,
|
||||
REG_A6XX_SP_NC_MODE_CNTL,
|
||||
REG_A6XX_SP_CHICKEN_BITS,
|
||||
REG_A8XX_SP_SS_CHICKEN_BITS_0,
|
||||
REG_A7XX_SP_CHICKEN_BITS_1,
|
||||
REG_A7XX_SP_CHICKEN_BITS_2,
|
||||
REG_A7XX_SP_CHICKEN_BITS_3,
|
||||
REG_A8XX_SP_CHICKEN_BITS_4,
|
||||
REG_A6XX_SP_PERFCTR_SHADER_MASK,
|
||||
REG_A8XX_RBBM_SLICE_PERFCTR_CNTL,
|
||||
REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL,
|
||||
REG_A7XX_SP_HLSQ_DBG_ECO_CNTL,
|
||||
REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1,
|
||||
REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2,
|
||||
REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3,
|
||||
REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN,
|
||||
REG_A8XX_SP_HLSQ_LPAC_GMEM_RANGE_MIN + 1,
|
||||
REG_A8XX_CP_INTERRUPT_STATUS_MASK_GLOBAL,
|
||||
REG_A8XX_RBBM_PERFCTR_CNTL,
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(0),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(1),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(2),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(3),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(4),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(5),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(6),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(7),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(8),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(9),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(10),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(11),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(12),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(13),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(14),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(15),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(16),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(17),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(18),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(19),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(20),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(21),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(22),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(23),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(24),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(25),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(26),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(27),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(28),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(29),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(30),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(31),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(32),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(33),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(34),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(35),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(36),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(37),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(38),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(39),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(40),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(41),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(42),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(43),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(44),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(45),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(46),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(47),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(48),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(49),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(50),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(51),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(52),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(53),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(54),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(55),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(56),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(57),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(58),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(59),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(60),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(61),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(62),
|
||||
REG_A8XX_CP_PROTECT_GLOBAL(63),
|
||||
};
|
||||
DECLARE_ADRENO_REGLIST_LIST(a840_ifpc_reglist);
|
||||
|
||||
static const struct adreno_reglist_pipe a840_dyn_pwrup_reglist_regs[] = {
|
||||
{ REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) },
|
||||
{ REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0, BIT(PIPE_BR)},
|
||||
{ REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
|
||||
{ REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) },
|
||||
{ REG_A6XX_RB_RBP_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) },
|
||||
{ REG_A6XX_RB_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) },
|
||||
{ REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) },
|
||||
{ REG_A8XX_CP_HW_FAULT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) |
|
||||
BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) |
|
||||
BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) },
|
||||
{ REG_A8XX_CP_INTERRUPT_STATUS_MASK_PIPE, 0, BIT(PIPE_BR) |
|
||||
BIT(PIPE_BV) | BIT(PIPE_LPAC) | BIT(PIPE_AQE0) |
|
||||
BIT(PIPE_AQE1) | BIT(PIPE_DDE_BR) | BIT(PIPE_DDE_BV) },
|
||||
{ REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC)},
|
||||
{ REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) | BIT(PIPE_LPAC) },
|
||||
{ REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
|
||||
{ REG_A8XX_RB_LPAC_GMEM_PROTECT, 0, BIT(PIPE_BR) },
|
||||
{ REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) },
|
||||
};
|
||||
DECLARE_ADRENO_REGLIST_PIPE_LIST(a840_dyn_pwrup_reglist);
|
||||
|
||||
static const struct adreno_info a8xx_gpus[] = {
|
||||
{
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x44070001),
|
||||
|
|
@ -1902,11 +2119,16 @@ static const struct adreno_info a8xx_gpus[] = {
|
|||
.gmem = 21 * SZ_1M,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
|
||||
ADRENO_QUIRK_HAS_HW_APRIV,
|
||||
ADRENO_QUIRK_HAS_HW_APRIV |
|
||||
ADRENO_QUIRK_PREEMPTION |
|
||||
ADRENO_QUIRK_SOFTFUSE,
|
||||
.funcs = &a8xx_gpu_funcs,
|
||||
.a6xx = &(const struct a6xx_info) {
|
||||
.protect = &x285_protect,
|
||||
.nonctxt_reglist = x285_nonctxt_regs,
|
||||
.pwrup_reglist = &a840_pwrup_reglist,
|
||||
.dyn_pwrup_reglist = &x285_dyn_pwrup_reglist,
|
||||
.ifpc_reglist = &a840_ifpc_reglist,
|
||||
.gbif_cx = a840_gbif,
|
||||
.max_slices = 4,
|
||||
.gmu_chipid = 0x8010100,
|
||||
|
|
@ -1922,6 +2144,12 @@ static const struct adreno_info a8xx_gpus[] = {
|
|||
{ /* sentinel */ },
|
||||
},
|
||||
},
|
||||
.speedbins = ADRENO_SPEEDBINS(
|
||||
{ 0, 0 },
|
||||
{ 388, 1 },
|
||||
{ 357, 2 },
|
||||
{ 284, 3 },
|
||||
),
|
||||
}, {
|
||||
.chip_ids = ADRENO_CHIP_IDS(0x44050a01),
|
||||
.family = ADRENO_8XX_GEN2,
|
||||
|
|
@ -1933,11 +2161,16 @@ static const struct adreno_info a8xx_gpus[] = {
|
|||
.gmem = 18 * SZ_1M,
|
||||
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
|
||||
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
|
||||
ADRENO_QUIRK_HAS_HW_APRIV,
|
||||
ADRENO_QUIRK_HAS_HW_APRIV |
|
||||
ADRENO_QUIRK_PREEMPTION |
|
||||
ADRENO_QUIRK_IFPC,
|
||||
.funcs = &a8xx_gpu_funcs,
|
||||
.a6xx = &(const struct a6xx_info) {
|
||||
.protect = &a840_protect,
|
||||
.nonctxt_reglist = a840_nonctxt_regs,
|
||||
.pwrup_reglist = &a840_pwrup_reglist,
|
||||
.dyn_pwrup_reglist = &a840_dyn_pwrup_reglist,
|
||||
.ifpc_reglist = &a840_ifpc_reglist,
|
||||
.gbif_cx = a840_gbif,
|
||||
.max_slices = 3,
|
||||
.gmu_chipid = 0x8020100,
|
||||
|
|
@ -1954,6 +2187,12 @@ static const struct adreno_info a8xx_gpus[] = {
|
|||
},
|
||||
},
|
||||
.preempt_record_size = 19708 * SZ_1K,
|
||||
.speedbins = ADRENO_SPEEDBINS(
|
||||
{ 0, 0 },
|
||||
{ 273, 1 },
|
||||
{ 252, 2 },
|
||||
{ 221, 3 },
|
||||
),
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@
|
|||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/firmware/qcom/qcom_scm.h>
|
||||
#include <linux/interconnect.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
|
@ -91,10 +92,10 @@ bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu)
|
|||
}
|
||||
|
||||
/* Check to see if the GX rail is still powered */
|
||||
bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
|
||||
bool a6xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu)
|
||||
{
|
||||
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
|
||||
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
|
||||
u32 val;
|
||||
|
||||
/* This can be called from gpu state code so make sure GMU is valid */
|
||||
|
|
@ -117,6 +118,40 @@ bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
|
|||
A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
|
||||
}
|
||||
|
||||
bool a7xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu)
|
||||
{
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
|
||||
u32 val;
|
||||
|
||||
/* This can be called from gpu state code so make sure GMU is valid */
|
||||
if (!gmu->initialized)
|
||||
return false;
|
||||
|
||||
val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
|
||||
|
||||
return !(val &
|
||||
(A7XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
|
||||
A7XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
|
||||
}
|
||||
|
||||
bool a8xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu)
|
||||
{
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
|
||||
u32 val;
|
||||
|
||||
/* This can be called from gpu state code so make sure GMU is valid */
|
||||
if (!gmu->initialized)
|
||||
return false;
|
||||
|
||||
val = gmu_read(gmu, REG_A8XX_GMU_PWR_CLK_STATUS);
|
||||
|
||||
return !(val &
|
||||
(A8XX_GMU_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
|
||||
A8XX_GMU_PWR_CLK_STATUS_GX_HM_CLK_OFF));
|
||||
}
|
||||
|
||||
void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
|
||||
bool suspended)
|
||||
{
|
||||
|
|
@ -240,7 +275,7 @@ static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
|
|||
|
||||
if (val == local) {
|
||||
if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
|
||||
!a6xx_gmu_gx_is_on(gmu))
|
||||
!adreno_gpu->funcs->gx_is_on(adreno_gpu))
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -1157,6 +1192,65 @@ static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
|
|||
dev_pm_opp_put(gpu_opp);
|
||||
}
|
||||
|
||||
static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
|
||||
struct msm_gpu *gpu = &adreno_gpu->base;
|
||||
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
|
||||
u32 fuse_val;
|
||||
int ret;
|
||||
|
||||
if (test_bit(GMU_STATUS_SECURE_INIT, &gmu->status))
|
||||
return 0;
|
||||
|
||||
if (adreno_is_a750(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) {
|
||||
/*
|
||||
* Assume that if qcom scm isn't available, that whatever
|
||||
* replacement allows writing the fuse register ourselves.
|
||||
* Users of alternative firmware need to make sure this
|
||||
* register is writeable or indicate that it's not somehow.
|
||||
* Print a warning because if you mess this up you're about to
|
||||
* crash horribly.
|
||||
*/
|
||||
if (!qcom_scm_is_available()) {
|
||||
dev_warn_once(gpu->dev->dev,
|
||||
"SCM is not available, poking fuse register\n");
|
||||
a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
|
||||
A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
|
||||
A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
|
||||
A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
|
||||
adreno_gpu->has_ray_tracing = true;
|
||||
goto done;
|
||||
}
|
||||
|
||||
ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ |
|
||||
QCOM_SCM_GPU_TSENSE_EN_REQ);
|
||||
if (ret) {
|
||||
dev_warn_once(gpu->dev->dev,
|
||||
"SCM call failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* On A7XX_GEN3 and newer, raytracing may be disabled by the
|
||||
* firmware, find out whether that's the case. The scm call
|
||||
* above sets the fuse register.
|
||||
*/
|
||||
fuse_val = a6xx_llc_read(a6xx_gpu,
|
||||
REG_A7XX_CX_MISC_SW_FUSE_VALUE);
|
||||
adreno_gpu->has_ray_tracing =
|
||||
!!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING);
|
||||
} else if (adreno_is_a740(adreno_gpu)) {
|
||||
/* Raytracing is always enabled on a740 */
|
||||
adreno_gpu->has_ray_tracing = true;
|
||||
}
|
||||
|
||||
done:
|
||||
set_bit(GMU_STATUS_SECURE_INIT, &gmu->status);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
|
||||
|
|
@ -1185,11 +1279,12 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
|
|||
clk_set_rate(gmu->hub_clk, adreno_is_a740_family(adreno_gpu) ?
|
||||
200000000 : 150000000);
|
||||
ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
|
||||
if (ret) {
|
||||
pm_runtime_put(gmu->gxpd);
|
||||
pm_runtime_put(gmu->dev);
|
||||
return ret;
|
||||
}
|
||||
if (ret)
|
||||
goto rpm_put;
|
||||
|
||||
ret = a6xx_gmu_secure_init(a6xx_gpu);
|
||||
if (ret)
|
||||
goto disable_clk;
|
||||
|
||||
/* Read the slice info on A8x GPUs */
|
||||
a8xx_gpu_get_slice_info(gpu);
|
||||
|
|
@ -1219,11 +1314,11 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
|
|||
|
||||
ret = a6xx_gmu_fw_start(gmu, status);
|
||||
if (ret)
|
||||
goto out;
|
||||
goto disable_irq;
|
||||
|
||||
ret = a6xx_hfi_start(gmu, status);
|
||||
if (ret)
|
||||
goto out;
|
||||
goto disable_irq;
|
||||
|
||||
/*
|
||||
* Turn on the GMU firmware fault interrupt after we know the boot
|
||||
|
|
@ -1236,19 +1331,16 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
|
|||
/* Set the GPU to the current freq */
|
||||
a6xx_gmu_set_initial_freq(gpu, gmu);
|
||||
|
||||
if (refcount_read(&gpu->sysprof_active) > 1) {
|
||||
ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET);
|
||||
if (!ret)
|
||||
set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status);
|
||||
}
|
||||
out:
|
||||
/* On failure, shut down the GMU to leave it in a good state */
|
||||
if (ret) {
|
||||
disable_irq(gmu->gmu_irq);
|
||||
a6xx_rpmh_stop(gmu);
|
||||
pm_runtime_put(gmu->gxpd);
|
||||
pm_runtime_put(gmu->dev);
|
||||
}
|
||||
return 0;
|
||||
|
||||
disable_irq:
|
||||
disable_irq(gmu->gmu_irq);
|
||||
a6xx_rpmh_stop(gmu);
|
||||
disable_clk:
|
||||
clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
|
||||
rpm_put:
|
||||
pm_runtime_put(gmu->gxpd);
|
||||
pm_runtime_put(gmu->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include <linux/notifier.h>
|
||||
#include <linux/soc/qcom/qcom_aoss.h>
|
||||
#include "msm_drv.h"
|
||||
#include "adreno_gpu.h"
|
||||
#include "a6xx_hfi.h"
|
||||
|
||||
struct a6xx_gmu_bo {
|
||||
|
|
@ -110,7 +111,7 @@ struct a6xx_gmu {
|
|||
|
||||
unsigned long freq;
|
||||
|
||||
struct a6xx_hfi_queue queues[2];
|
||||
struct a6xx_hfi_queue queues[HFI_MAX_QUEUES];
|
||||
|
||||
bool initialized;
|
||||
bool hung;
|
||||
|
|
@ -129,6 +130,8 @@ struct a6xx_gmu {
|
|||
#define GMU_STATUS_PDC_SLEEP 1
|
||||
/* To track Perfcounter OOB set status */
|
||||
#define GMU_STATUS_OOB_PERF_SET 2
|
||||
/* To track whether secure world init was done */
|
||||
#define GMU_STATUS_SECURE_INIT 3
|
||||
unsigned long status;
|
||||
};
|
||||
|
||||
|
|
@ -231,7 +234,9 @@ void a6xx_hfi_stop(struct a6xx_gmu *gmu);
|
|||
int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu);
|
||||
int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, u32 perf_index, u32 bw_index);
|
||||
|
||||
bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu);
|
||||
bool a6xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu);
|
||||
bool a7xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu);
|
||||
bool a8xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu);
|
||||
bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu);
|
||||
void a6xx_sptprac_disable(struct a6xx_gmu *gmu);
|
||||
int a6xx_sptprac_enable(struct a6xx_gmu *gmu);
|
||||
|
|
|
|||
|
|
@ -10,14 +10,15 @@
|
|||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/devfreq.h>
|
||||
#include <linux/firmware/qcom/qcom_scm.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/soc/qcom/llcc-qcom.h>
|
||||
|
||||
#define GPU_PAS_ID 13
|
||||
|
||||
static u64 read_gmu_ao_counter(struct a6xx_gpu *a6xx_gpu)
|
||||
static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
u64 count_hi, count_lo, temp;
|
||||
|
||||
do {
|
||||
|
|
@ -345,7 +346,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|||
* GPU registers so we need to add 0x1a800 to the register value on A630
|
||||
* to get the right value from PM4.
|
||||
*/
|
||||
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
|
||||
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_CONTEXT,
|
||||
rbmemptr_stats(ring, index, alwayson_start));
|
||||
|
||||
/* Invalidate CCU depth and color */
|
||||
|
|
@ -386,7 +387,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|||
|
||||
get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
|
||||
rbmemptr_stats(ring, index, cpcycles_end));
|
||||
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
|
||||
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_CONTEXT,
|
||||
rbmemptr_stats(ring, index, alwayson_end));
|
||||
|
||||
/* Write the fence to the scratch register */
|
||||
|
|
@ -404,12 +405,12 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|||
OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
|
||||
OUT_RING(ring, submit->seqno);
|
||||
|
||||
trace_msm_gpu_submit_flush(submit, read_gmu_ao_counter(a6xx_gpu));
|
||||
trace_msm_gpu_submit_flush(submit, adreno_gpu->funcs->get_timestamp(gpu));
|
||||
|
||||
a6xx_flush(gpu, ring);
|
||||
}
|
||||
|
||||
static void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring,
|
||||
void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring,
|
||||
struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue)
|
||||
{
|
||||
u64 preempt_postamble;
|
||||
|
|
@ -455,7 +456,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
struct msm_ringbuffer *ring = submit->ring;
|
||||
u32 rbbm_perfctr_cp0, cp_always_on_counter;
|
||||
u32 rbbm_perfctr_cp0, cp_always_on_context;
|
||||
unsigned int i, ibs = 0;
|
||||
|
||||
adreno_check_and_reenable_stall(adreno_gpu);
|
||||
|
|
@ -478,14 +479,14 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|||
|
||||
if (adreno_is_a8xx(adreno_gpu)) {
|
||||
rbbm_perfctr_cp0 = REG_A8XX_RBBM_PERFCTR_CP(0);
|
||||
cp_always_on_counter = REG_A8XX_CP_ALWAYS_ON_COUNTER;
|
||||
cp_always_on_context = REG_A8XX_CP_ALWAYS_ON_CONTEXT;
|
||||
} else {
|
||||
rbbm_perfctr_cp0 = REG_A7XX_RBBM_PERFCTR_CP(0);
|
||||
cp_always_on_counter = REG_A6XX_CP_ALWAYS_ON_COUNTER;
|
||||
cp_always_on_context = REG_A6XX_CP_ALWAYS_ON_CONTEXT;
|
||||
}
|
||||
|
||||
get_stats_counter(ring, rbbm_perfctr_cp0, rbmemptr_stats(ring, index, cpcycles_start));
|
||||
get_stats_counter(ring, cp_always_on_counter, rbmemptr_stats(ring, index, alwayson_start));
|
||||
get_stats_counter(ring, cp_always_on_context, rbmemptr_stats(ring, index, alwayson_start));
|
||||
|
||||
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
|
||||
OUT_RING(ring, CP_SET_THREAD_BOTH);
|
||||
|
|
@ -533,7 +534,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|||
}
|
||||
|
||||
get_stats_counter(ring, rbbm_perfctr_cp0, rbmemptr_stats(ring, index, cpcycles_end));
|
||||
get_stats_counter(ring, cp_always_on_counter, rbmemptr_stats(ring, index, alwayson_end));
|
||||
get_stats_counter(ring, cp_always_on_context, rbmemptr_stats(ring, index, alwayson_end));
|
||||
|
||||
/* Write the fence to the scratch register */
|
||||
if (adreno_is_a8xx(adreno_gpu)) {
|
||||
|
|
@ -614,12 +615,15 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|||
}
|
||||
|
||||
|
||||
trace_msm_gpu_submit_flush(submit, read_gmu_ao_counter(a6xx_gpu));
|
||||
trace_msm_gpu_submit_flush(submit, adreno_gpu->funcs->get_timestamp(gpu));
|
||||
|
||||
a6xx_flush(gpu, ring);
|
||||
|
||||
/* Check to see if we need to start preemption */
|
||||
a6xx_preempt_trigger(gpu);
|
||||
if (adreno_is_a8xx(adreno_gpu))
|
||||
a8xx_preempt_trigger(gpu);
|
||||
else
|
||||
a6xx_preempt_trigger(gpu);
|
||||
}
|
||||
|
||||
static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
|
||||
|
|
@ -1603,6 +1607,12 @@ static int hw_init(struct msm_gpu *gpu)
|
|||
a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
|
||||
}
|
||||
|
||||
if (!ret && (refcount_read(&gpu->sysprof_active) > 1)) {
|
||||
ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET);
|
||||
if (!ret)
|
||||
set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1635,7 +1645,7 @@ static void a6xx_recover(struct msm_gpu *gpu)
|
|||
|
||||
adreno_dump_info(gpu);
|
||||
|
||||
if (a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) {
|
||||
if (adreno_gpu->funcs->gx_is_on(adreno_gpu)) {
|
||||
/* Sometimes crashstate capture is skipped, so SQE should be halted here again */
|
||||
gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3);
|
||||
|
||||
|
|
@ -2152,56 +2162,6 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
|
|||
a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
|
||||
struct msm_gpu *gpu = &adreno_gpu->base;
|
||||
u32 fuse_val;
|
||||
int ret;
|
||||
|
||||
if (adreno_is_a750(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) {
|
||||
/*
|
||||
* Assume that if qcom scm isn't available, that whatever
|
||||
* replacement allows writing the fuse register ourselves.
|
||||
* Users of alternative firmware need to make sure this
|
||||
* register is writeable or indicate that it's not somehow.
|
||||
* Print a warning because if you mess this up you're about to
|
||||
* crash horribly.
|
||||
*/
|
||||
if (!qcom_scm_is_available()) {
|
||||
dev_warn_once(gpu->dev->dev,
|
||||
"SCM is not available, poking fuse register\n");
|
||||
a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
|
||||
A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
|
||||
A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
|
||||
A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
|
||||
adreno_gpu->has_ray_tracing = true;
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ |
|
||||
QCOM_SCM_GPU_TSENSE_EN_REQ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* On A7XX_GEN3 and newer, raytracing may be disabled by the
|
||||
* firmware, find out whether that's the case. The scm call
|
||||
* above sets the fuse register.
|
||||
*/
|
||||
fuse_val = a6xx_llc_read(a6xx_gpu,
|
||||
REG_A7XX_CX_MISC_SW_FUSE_VALUE);
|
||||
adreno_gpu->has_ray_tracing =
|
||||
!!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING);
|
||||
} else if (adreno_is_a740(adreno_gpu)) {
|
||||
/* Raytracing is always enabled on a740 */
|
||||
adreno_gpu->has_ray_tracing = true;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#define GBIF_CLIENT_HALT_MASK BIT(0)
|
||||
#define GBIF_ARB_HALT_MASK BIT(1)
|
||||
#define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0)
|
||||
|
|
@ -2414,20 +2374,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
|
||||
static u64 a6xx_get_timestamp(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
|
||||
*value = read_gmu_ao_counter(a6xx_gpu);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
|
||||
{
|
||||
*value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER);
|
||||
return 0;
|
||||
return gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER);
|
||||
}
|
||||
|
||||
static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
|
||||
|
|
@ -2600,13 +2549,33 @@ static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse)
|
|||
return UINT_MAX;
|
||||
}
|
||||
|
||||
static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info)
|
||||
static int a6xx_read_speedbin(struct device *dev, struct a6xx_gpu *a6xx_gpu,
|
||||
const struct adreno_info *info, u32 *speedbin)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Use speedbin fuse if present. Otherwise, fallback to softfuse */
|
||||
ret = adreno_read_speedbin(dev, speedbin);
|
||||
if (ret != -ENOENT)
|
||||
return ret;
|
||||
|
||||
if (info->quirks & ADRENO_QUIRK_SOFTFUSE) {
|
||||
*speedbin = a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS);
|
||||
*speedbin = A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*speedbin);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
|
||||
const struct adreno_info *info)
|
||||
{
|
||||
u32 supp_hw;
|
||||
u32 speedbin;
|
||||
int ret;
|
||||
|
||||
ret = adreno_read_speedbin(dev, &speedbin);
|
||||
ret = a6xx_read_speedbin(dev, a6xx_gpu, info, &speedbin);
|
||||
/*
|
||||
* -ENOENT means that the platform doesn't support speedbin which is
|
||||
* fine
|
||||
|
|
@ -2635,16 +2604,29 @@ static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *i
|
|||
return 0;
|
||||
}
|
||||
|
||||
static bool a6xx_aqe_is_enabled(struct adreno_gpu *adreno_gpu)
|
||||
{
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
|
||||
/*
|
||||
* AQE uses preemption context record as scratch pad, so check if
|
||||
* preemption is enabled
|
||||
*/
|
||||
return (adreno_gpu->base.nr_rings > 1) && !!a6xx_gpu->aqe_bo;
|
||||
}
|
||||
|
||||
static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
|
||||
{
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
struct platform_device *pdev = priv->gpu_pdev;
|
||||
struct adreno_platform_config *config = pdev->dev.platform_data;
|
||||
const struct adreno_info *info = config->info;
|
||||
struct device_node *node;
|
||||
struct a6xx_gpu *a6xx_gpu;
|
||||
struct adreno_gpu *adreno_gpu;
|
||||
struct msm_gpu *gpu;
|
||||
extern int enable_preemption;
|
||||
u32 speedbin;
|
||||
bool is_a7xx;
|
||||
int ret, nr_rings = 1;
|
||||
|
||||
|
|
@ -2656,6 +2638,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
|
|||
gpu = &adreno_gpu->base;
|
||||
|
||||
mutex_init(&a6xx_gpu->gmu.lock);
|
||||
spin_lock_init(&a6xx_gpu->aperture_lock);
|
||||
|
||||
adreno_gpu->registers = NULL;
|
||||
|
||||
|
|
@ -2667,14 +2650,14 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
|
|||
adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper");
|
||||
|
||||
adreno_gpu->base.hw_apriv =
|
||||
!!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
|
||||
!!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
|
||||
|
||||
/* gpu->info only gets assigned in adreno_gpu_init(). A8x is included intentionally */
|
||||
is_a7xx = config->info->family >= ADRENO_7XX_GEN1;
|
||||
is_a7xx = info->family >= ADRENO_7XX_GEN1;
|
||||
|
||||
a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);
|
||||
|
||||
ret = a6xx_set_supported_hw(&pdev->dev, config->info);
|
||||
ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info);
|
||||
if (ret) {
|
||||
a6xx_llc_slices_destroy(a6xx_gpu);
|
||||
kfree(a6xx_gpu);
|
||||
|
|
@ -2682,15 +2665,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
|
|||
}
|
||||
|
||||
if ((enable_preemption == 1) || (enable_preemption == -1 &&
|
||||
(config->info->quirks & ADRENO_QUIRK_PREEMPTION)))
|
||||
(info->quirks & ADRENO_QUIRK_PREEMPTION)))
|
||||
nr_rings = 4;
|
||||
|
||||
ret = adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, nr_rings);
|
||||
ret = adreno_gpu_init(dev, pdev, adreno_gpu, info->funcs, nr_rings);
|
||||
if (ret) {
|
||||
a6xx_destroy(&(a6xx_gpu->base.base));
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
/* Set the speedbin value that is passed to userspace */
|
||||
if (a6xx_read_speedbin(&pdev->dev, a6xx_gpu, info, &speedbin) || !speedbin)
|
||||
speedbin = 0xffff;
|
||||
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
|
||||
|
||||
/*
|
||||
* For now only clamp to idle freq for devices where this is known not
|
||||
* to cause power supply issues:
|
||||
|
|
@ -2708,14 +2696,6 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
|
|||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) {
|
||||
ret = a7xx_cx_mem_init(a6xx_gpu);
|
||||
if (ret) {
|
||||
a6xx_destroy(&(a6xx_gpu->base.base));
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
}
|
||||
|
||||
adreno_gpu->uche_trap_base = 0x1fffffffff000ull;
|
||||
|
||||
msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
|
||||
|
|
@ -2765,6 +2745,7 @@ const struct adreno_gpu_funcs a6xx_gpu_funcs = {
|
|||
.get_timestamp = a6xx_gmu_get_timestamp,
|
||||
.bus_halt = a6xx_bus_clear_pending_transactions,
|
||||
.mmu_fault_handler = a6xx_fault_handler,
|
||||
.gx_is_on = a6xx_gmu_gx_is_on,
|
||||
};
|
||||
|
||||
const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = {
|
||||
|
|
@ -2797,6 +2778,7 @@ const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = {
|
|||
.get_timestamp = a6xx_get_timestamp,
|
||||
.bus_halt = a6xx_bus_clear_pending_transactions,
|
||||
.mmu_fault_handler = a6xx_fault_handler,
|
||||
.gx_is_on = a6xx_gmu_gx_is_on,
|
||||
};
|
||||
|
||||
const struct adreno_gpu_funcs a7xx_gpu_funcs = {
|
||||
|
|
@ -2831,6 +2813,8 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs = {
|
|||
.get_timestamp = a6xx_gmu_get_timestamp,
|
||||
.bus_halt = a6xx_bus_clear_pending_transactions,
|
||||
.mmu_fault_handler = a6xx_fault_handler,
|
||||
.gx_is_on = a7xx_gmu_gx_is_on,
|
||||
.aqe_is_enabled = a6xx_aqe_is_enabled,
|
||||
};
|
||||
|
||||
const struct adreno_gpu_funcs a8xx_gpu_funcs = {
|
||||
|
|
@ -2858,4 +2842,6 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = {
|
|||
.get_timestamp = a8xx_gmu_get_timestamp,
|
||||
.bus_halt = a8xx_bus_clear_pending_transactions,
|
||||
.mmu_fault_handler = a8xx_fault_handler,
|
||||
.gx_is_on = a8xx_gmu_gx_is_on,
|
||||
.aqe_is_enabled = a6xx_aqe_is_enabled,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -278,6 +278,8 @@ void a6xx_preempt_hw_init(struct msm_gpu *gpu);
|
|||
void a6xx_preempt_trigger(struct msm_gpu *gpu);
|
||||
void a6xx_preempt_irq(struct msm_gpu *gpu);
|
||||
void a6xx_preempt_fini(struct msm_gpu *gpu);
|
||||
void a6xx_emit_set_pseudo_reg(struct msm_ringbuffer *ring,
|
||||
struct a6xx_gpu *a6xx_gpu, struct msm_gpu_submitqueue *queue);
|
||||
int a6xx_preempt_submitqueue_setup(struct msm_gpu *gpu,
|
||||
struct msm_gpu_submitqueue *queue);
|
||||
void a6xx_preempt_submitqueue_close(struct msm_gpu *gpu,
|
||||
|
|
@ -320,13 +322,16 @@ int a6xx_zap_shader_init(struct msm_gpu *gpu);
|
|||
void a8xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off);
|
||||
int a8xx_fault_handler(void *arg, unsigned long iova, int flags, void *data);
|
||||
void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
|
||||
int a8xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value);
|
||||
u64 a8xx_gmu_get_timestamp(struct msm_gpu *gpu);
|
||||
u64 a8xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate);
|
||||
int a8xx_gpu_feature_probe(struct msm_gpu *gpu);
|
||||
void a8xx_gpu_get_slice_info(struct msm_gpu *gpu);
|
||||
int a8xx_hw_init(struct msm_gpu *gpu);
|
||||
irqreturn_t a8xx_irq(struct msm_gpu *gpu);
|
||||
void a8xx_llc_activate(struct a6xx_gpu *a6xx_gpu);
|
||||
void a8xx_preempt_hw_init(struct msm_gpu *gpu);
|
||||
void a8xx_preempt_trigger(struct msm_gpu *gpu);
|
||||
void a8xx_preempt_irq(struct msm_gpu *gpu);
|
||||
bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
|
||||
void a8xx_recover(struct msm_gpu *gpu);
|
||||
#endif /* __A6XX_GPU_H__ */
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ struct a6xx_gpu_state {
|
|||
struct msm_gpu_state_bo *gmu_hfi;
|
||||
struct msm_gpu_state_bo *gmu_debug;
|
||||
|
||||
s32 hfi_queue_history[2][HFI_HISTORY_SZ];
|
||||
s32 hfi_queue_history[HFI_MAX_QUEUES][HFI_HISTORY_SZ];
|
||||
|
||||
struct list_head objs;
|
||||
|
||||
|
|
@ -361,7 +361,7 @@ static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu,
|
|||
sizeof(*a6xx_state->debugbus));
|
||||
|
||||
if (a6xx_state->debugbus) {
|
||||
int i;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(a6xx_debugbus_blocks); i++)
|
||||
a6xx_get_debugbus_block(gpu,
|
||||
|
|
@ -369,8 +369,6 @@ static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu,
|
|||
&a6xx_debugbus_blocks[i],
|
||||
&a6xx_state->debugbus[i]);
|
||||
|
||||
a6xx_state->nr_debugbus = ARRAY_SIZE(a6xx_debugbus_blocks);
|
||||
|
||||
/*
|
||||
* GBIF has same debugbus as of other GPU blocks, fall back to
|
||||
* default path if GPU uses GBIF, also GBIF uses exactly same
|
||||
|
|
@ -381,17 +379,19 @@ static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu,
|
|||
&a6xx_gbif_debugbus_block,
|
||||
&a6xx_state->debugbus[i]);
|
||||
|
||||
a6xx_state->nr_debugbus += 1;
|
||||
i++;
|
||||
}
|
||||
|
||||
|
||||
if (adreno_is_a650_family(to_adreno_gpu(gpu))) {
|
||||
for (i = 0; i < ARRAY_SIZE(a650_debugbus_blocks); i++)
|
||||
for (j = 0; j < ARRAY_SIZE(a650_debugbus_blocks); i++, j++)
|
||||
a6xx_get_debugbus_block(gpu,
|
||||
a6xx_state,
|
||||
&a650_debugbus_blocks[i],
|
||||
&a650_debugbus_blocks[j],
|
||||
&a6xx_state->debugbus[i]);
|
||||
}
|
||||
|
||||
a6xx_state->nr_debugbus = i;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1013,7 +1013,7 @@ static void a6xx_get_crashdumper_hlsq_registers(struct msm_gpu *gpu,
|
|||
u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
|
||||
int i, regcount = 0;
|
||||
|
||||
in += CRASHDUMP_WRITE(in, REG_A6XX_HLSQ_DBG_READ_SEL, regs->val1);
|
||||
in += CRASHDUMP_WRITE(in, REG_A6XX_HLSQ_DBG_READ_SEL, (regs->val1 & 0xff) << 8);
|
||||
|
||||
for (i = 0; i < regs->count; i += 2) {
|
||||
u32 count = RANGE(regs->registers, i);
|
||||
|
|
@ -1251,7 +1251,7 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
|
|||
_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gpucc_reg,
|
||||
&a6xx_state->gmu_registers[2], false);
|
||||
|
||||
if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu))
|
||||
if (!adreno_gpu->funcs->gx_is_on(adreno_gpu))
|
||||
return;
|
||||
|
||||
/* Set the fence to ALLOW mode so we can access the registers */
|
||||
|
|
@ -1607,7 +1607,7 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
|
|||
}
|
||||
|
||||
/* If GX isn't on the rest of the data isn't going to be accessible */
|
||||
if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu))
|
||||
if (!adreno_gpu->funcs->gx_is_on(adreno_gpu))
|
||||
return &a6xx_state->base;
|
||||
|
||||
/* Halt SQE first */
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu,
|
|||
struct a6xx_hfi_queue_header *header = queue->header;
|
||||
u32 i, hdr, index = header->read_index;
|
||||
|
||||
if (header->read_index == header->write_index) {
|
||||
if (header->read_index == READ_ONCE(header->write_index)) {
|
||||
header->rx_request = 1;
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -62,7 +62,10 @@ static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu,
|
|||
if (!gmu->legacy)
|
||||
index = ALIGN(index, 4) % header->size;
|
||||
|
||||
header->read_index = index;
|
||||
/* Ensure all memory operations are complete before updating the read index */
|
||||
dma_mb();
|
||||
|
||||
WRITE_ONCE(header->read_index, index);
|
||||
return HFI_HEADER_SIZE(hdr);
|
||||
}
|
||||
|
||||
|
|
@ -74,7 +77,7 @@ static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu,
|
|||
|
||||
spin_lock(&queue->lock);
|
||||
|
||||
space = CIRC_SPACE(header->write_index, header->read_index,
|
||||
space = CIRC_SPACE(header->write_index, READ_ONCE(header->read_index),
|
||||
header->size);
|
||||
if (space < dwords) {
|
||||
header->dropped++;
|
||||
|
|
@ -95,7 +98,10 @@ static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu,
|
|||
queue->data[index] = 0xfafafafa;
|
||||
}
|
||||
|
||||
header->write_index = index;
|
||||
/* Ensure all memory operations are complete before updating the write index */
|
||||
dma_mb();
|
||||
|
||||
WRITE_ONCE(header->write_index, index);
|
||||
spin_unlock(&queue->lock);
|
||||
|
||||
gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01);
|
||||
|
|
@ -845,7 +851,6 @@ static int a6xx_hfi_feature_ctrl_msg(struct a6xx_gmu *gmu, u32 feature, u32 enab
|
|||
return a6xx_hfi_send_msg(gmu, HFI_H2F_FEATURE_CTRL, &msg, sizeof(msg), NULL, 0);
|
||||
}
|
||||
|
||||
#define HFI_FEATURE_IFPC 9
|
||||
#define IFPC_LONG_HYST 0x1680
|
||||
|
||||
static int a6xx_hfi_enable_ifpc(struct a6xx_gmu *gmu)
|
||||
|
|
@ -856,8 +861,6 @@ static int a6xx_hfi_enable_ifpc(struct a6xx_gmu *gmu)
|
|||
return a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_IFPC, 1, IFPC_LONG_HYST);
|
||||
}
|
||||
|
||||
#define HFI_FEATURE_ACD 12
|
||||
|
||||
static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu)
|
||||
{
|
||||
struct a6xx_hfi_acd_table *acd_table = &gmu->acd_table;
|
||||
|
|
@ -1056,8 +1059,8 @@ void a6xx_hfi_init(struct a6xx_gmu *gmu)
|
|||
struct a6xx_gmu_bo *hfi = &gmu->hfi;
|
||||
struct a6xx_hfi_queue_table_header *table = hfi->virt;
|
||||
struct a6xx_hfi_queue_header *headers = hfi->virt + sizeof(*table);
|
||||
int table_size, idx;
|
||||
u64 offset;
|
||||
int table_size;
|
||||
|
||||
/*
|
||||
* The table size is the size of the table header plus all of the queue
|
||||
|
|
@ -1076,12 +1079,22 @@ void a6xx_hfi_init(struct a6xx_gmu *gmu)
|
|||
table->active_queues = ARRAY_SIZE(gmu->queues);
|
||||
|
||||
/* Command queue */
|
||||
idx = 0;
|
||||
offset = SZ_4K;
|
||||
a6xx_hfi_queue_init(&gmu->queues[0], &headers[0], hfi->virt + offset,
|
||||
a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset,
|
||||
hfi->iova + offset, 0);
|
||||
|
||||
/* GMU response queue */
|
||||
idx++;
|
||||
offset += SZ_4K;
|
||||
a6xx_hfi_queue_init(&gmu->queues[1], &headers[1], hfi->virt + offset,
|
||||
a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset,
|
||||
hfi->iova + offset, gmu->legacy ? 4 : 1);
|
||||
|
||||
/* GMU Debug queue */
|
||||
idx++;
|
||||
offset += SZ_4K;
|
||||
a6xx_hfi_queue_init(&gmu->queues[idx], &headers[idx], hfi->virt + offset,
|
||||
hfi->iova + offset, gmu->legacy ? 5 : 2);
|
||||
|
||||
WARN_ON(idx >= HFI_MAX_QUEUES);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
#ifndef _A6XX_HFI_H_
|
||||
#define _A6XX_HFI_H_
|
||||
|
||||
#define HFI_MAX_QUEUES 3
|
||||
|
||||
struct a6xx_hfi_queue_table_header {
|
||||
u32 version;
|
||||
u32 size; /* Size of the queue table in dwords */
|
||||
|
|
@ -11,7 +13,7 @@ struct a6xx_hfi_queue_table_header {
|
|||
u32 qhdr_size; /* Size of the queue headers */
|
||||
u32 num_queues; /* Number of total queues */
|
||||
u32 active_queues; /* Number of active queues */
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct a6xx_hfi_queue_header {
|
||||
u32 status;
|
||||
|
|
@ -26,7 +28,7 @@ struct a6xx_hfi_queue_header {
|
|||
u32 tx_request;
|
||||
u32 read_index;
|
||||
u32 write_index;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct a6xx_hfi_queue {
|
||||
struct a6xx_hfi_queue_header *header;
|
||||
|
|
@ -72,7 +74,7 @@ struct a6xx_hfi_msg_response {
|
|||
u32 ret_header;
|
||||
u32 error;
|
||||
u32 payload[HFI_RESPONSE_PAYLOAD_SIZE];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define HFI_F2H_MSG_ERROR 100
|
||||
|
||||
|
|
@ -80,7 +82,7 @@ struct a6xx_hfi_msg_error {
|
|||
u32 header;
|
||||
u32 code;
|
||||
u32 payload[2];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define HFI_H2F_MSG_INIT 0
|
||||
|
||||
|
|
@ -90,27 +92,27 @@ struct a6xx_hfi_msg_gmu_init_cmd {
|
|||
u32 dbg_buffer_addr;
|
||||
u32 dbg_buffer_size;
|
||||
u32 boot_state;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define HFI_H2F_MSG_FW_VERSION 1
|
||||
|
||||
struct a6xx_hfi_msg_fw_version {
|
||||
u32 header;
|
||||
u32 supported_version;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define HFI_H2F_MSG_PERF_TABLE 4
|
||||
|
||||
struct perf_level {
|
||||
u32 vote;
|
||||
u32 freq;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct perf_gx_level {
|
||||
u32 vote;
|
||||
u32 acd;
|
||||
u32 freq;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct a6xx_hfi_msg_perf_table_v1 {
|
||||
u32 header;
|
||||
|
|
@ -119,7 +121,7 @@ struct a6xx_hfi_msg_perf_table_v1 {
|
|||
|
||||
struct perf_level gx_votes[16];
|
||||
struct perf_level cx_votes[4];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct a6xx_hfi_msg_perf_table {
|
||||
u32 header;
|
||||
|
|
@ -128,7 +130,7 @@ struct a6xx_hfi_msg_perf_table {
|
|||
|
||||
struct perf_gx_level gx_votes[16];
|
||||
struct perf_level cx_votes[4];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define HFI_H2F_MSG_BW_TABLE 3
|
||||
|
||||
|
|
@ -143,13 +145,13 @@ struct a6xx_hfi_msg_bw_table {
|
|||
u32 cnoc_cmds_data[2][6];
|
||||
u32 ddr_cmds_addrs[8];
|
||||
u32 ddr_cmds_data[16][8];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define HFI_H2F_MSG_TEST 5
|
||||
|
||||
struct a6xx_hfi_msg_test {
|
||||
u32 header;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define HFI_H2F_MSG_ACD 7
|
||||
#define MAX_ACD_STRIDE 2
|
||||
|
|
@ -161,29 +163,100 @@ struct a6xx_hfi_acd_table {
|
|||
u32 stride;
|
||||
u32 num_levels;
|
||||
u32 data[16 * MAX_ACD_STRIDE];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define CLX_DATA(irated, num_phases, clx_path, extd_intf) \
|
||||
((extd_intf << 29) | \
|
||||
(clx_path << 28) | \
|
||||
(num_phases << 22) | \
|
||||
(irated << 16))
|
||||
|
||||
struct a6xx_hfi_clx_domain_v2 {
|
||||
/**
|
||||
* @data: BITS[0:15] Migration time
|
||||
* BITS[16:21] Current rating
|
||||
* BITS[22:27] Phases for domain
|
||||
* BITS[28:28] Path notification
|
||||
* BITS[29:31] Extra features
|
||||
*/
|
||||
u32 data;
|
||||
/** @clxt: CLX time in microseconds */
|
||||
u32 clxt;
|
||||
/** @clxh: CLH time in microseconds */
|
||||
u32 clxh;
|
||||
/** @urg_mode: Urgent HW throttle mode of operation */
|
||||
u32 urg_mode;
|
||||
/** @lkg_en: Enable leakage current estimate */
|
||||
u32 lkg_en;
|
||||
/** curr_budget: Current Budget */
|
||||
u32 curr_budget;
|
||||
} __packed;
|
||||
|
||||
#define HFI_H2F_MSG_CLX_TBL 8
|
||||
|
||||
#define MAX_CLX_DOMAINS 2
|
||||
struct a6xx_hfi_clx_table_v2_cmd {
|
||||
u32 hdr;
|
||||
u32 version;
|
||||
struct a6xx_hfi_clx_domain_v2 domain[MAX_CLX_DOMAINS];
|
||||
} __packed;
|
||||
|
||||
#define HFI_H2F_MSG_START 10
|
||||
|
||||
struct a6xx_hfi_msg_start {
|
||||
u32 header;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define HFI_H2F_FEATURE_CTRL 11
|
||||
|
||||
struct a6xx_hfi_msg_feature_ctrl {
|
||||
u32 header;
|
||||
u32 feature;
|
||||
#define HFI_FEATURE_DCVS 0
|
||||
#define HFI_FEATURE_HWSCHED 1
|
||||
#define HFI_FEATURE_PREEMPTION 2
|
||||
#define HFI_FEATURE_CLOCKS_ON 3
|
||||
#define HFI_FEATURE_BUS_ON 4
|
||||
#define HFI_FEATURE_RAIL_ON 5
|
||||
#define HFI_FEATURE_HWCG 6
|
||||
#define HFI_FEATURE_LM 7
|
||||
#define HFI_FEATURE_THROTTLE 8
|
||||
#define HFI_FEATURE_IFPC 9
|
||||
#define HFI_FEATURE_NAP 10
|
||||
#define HFI_FEATURE_BCL 11
|
||||
#define HFI_FEATURE_ACD 12
|
||||
#define HFI_FEATURE_DIDT 13
|
||||
#define HFI_FEATURE_DEPRECATED 14
|
||||
#define HFI_FEATURE_CB 15
|
||||
#define HFI_FEATURE_KPROF 16
|
||||
#define HFI_FEATURE_BAIL_OUT_TIMER 17
|
||||
#define HFI_FEATURE_GMU_STATS 18
|
||||
#define HFI_FEATURE_DBQ 19
|
||||
#define HFI_FEATURE_MINBW 20
|
||||
#define HFI_FEATURE_CLX 21
|
||||
#define HFI_FEATURE_LSR 23
|
||||
#define HFI_FEATURE_LPAC 24
|
||||
#define HFI_FEATURE_HW_FENCE 25
|
||||
#define HFI_FEATURE_PERF_NORETAIN 26
|
||||
#define HFI_FEATURE_DMS 27
|
||||
#define HFI_FEATURE_THERMAL 28
|
||||
#define HFI_FEATURE_AQE 29
|
||||
#define HFI_FEATURE_TDCVS 30
|
||||
#define HFI_FEATURE_DCE 31
|
||||
#define HFI_FEATURE_IFF_PCLX 32
|
||||
#define HFI_FEATURE_SOFT_RESET 0x10000001
|
||||
#define HFI_FEATURE_DCVS_PROFILE 0x10000002
|
||||
#define HFI_FEATURE_FAST_CTX_DESTROY 0x10000003
|
||||
u32 enable;
|
||||
u32 data;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define HFI_H2F_MSG_CORE_FW_START 14
|
||||
|
||||
struct a6xx_hfi_msg_core_fw_start {
|
||||
u32 header;
|
||||
u32 handle;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define HFI_H2F_MSG_TABLE 15
|
||||
|
||||
|
|
@ -191,16 +264,25 @@ struct a6xx_hfi_table_entry {
|
|||
u32 count;
|
||||
u32 stride;
|
||||
u32 data[];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct a6xx_hfi_table {
|
||||
u32 header;
|
||||
u32 version;
|
||||
u32 type;
|
||||
#define HFI_TABLE_BW_VOTE 0
|
||||
#define HFI_TABLE_GPU_PERF 1
|
||||
#define HFI_TABLE_BW_VOTE 0
|
||||
#define HFI_TABLE_GPU_PERF 1
|
||||
#define HFI_TABLE_DIDT 2
|
||||
#define HFI_TABLE_ACD 3
|
||||
#define HFI_TABLE_CLX_V1 4 /* Unused */
|
||||
#define HFI_TABLE_CLX_V2 5
|
||||
#define HFI_TABLE_THERM 6
|
||||
#define HFI_TABLE_DCVS 7
|
||||
#define HFI_TABLE_SYS_TIME 8
|
||||
#define HFI_TABLE_GMU_DCVS 9
|
||||
#define HFI_TABLE_LIMITS_MIT 10
|
||||
struct a6xx_hfi_table_entry entry[];
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define HFI_H2F_MSG_GX_BW_PERF_VOTE 30
|
||||
|
||||
|
|
@ -209,7 +291,7 @@ struct a6xx_hfi_gx_bw_perf_vote_cmd {
|
|||
u32 ack_type;
|
||||
u32 freq;
|
||||
u32 bw;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
#define AB_VOTE_MASK GENMASK(31, 16)
|
||||
#define MAX_AB_VOTE (FIELD_MAX(AB_VOTE_MASK) - 1)
|
||||
|
|
@ -222,6 +304,35 @@ struct a6xx_hfi_prep_slumber_cmd {
|
|||
u32 header;
|
||||
u32 bw;
|
||||
u32 freq;
|
||||
};
|
||||
} __packed;
|
||||
|
||||
struct a6xx_hfi_limits_cfg {
|
||||
u32 enable;
|
||||
u32 msg_path;
|
||||
u32 lkg_en;
|
||||
/*
|
||||
* BIT[0]: 0 = (static) throttle to fixed sid level
|
||||
* 1 = (dynamic) throttle to sid level calculated by HW
|
||||
* BIT[1]: 0 = Mx
|
||||
* 1 = Bx
|
||||
*/
|
||||
u32 mode;
|
||||
u32 sid;
|
||||
/* Mitigation time in microseconds */
|
||||
u32 mit_time;
|
||||
/* Max current in mA during mitigation */
|
||||
u32 curr_limit;
|
||||
} __packed;
|
||||
|
||||
struct a6xx_hfi_limits_tbl {
|
||||
u8 feature_id;
|
||||
#define GMU_MIT_IFF 0
|
||||
#define GMU_MIT_PCLX 1
|
||||
u8 domain;
|
||||
#define GMU_GX_DOMAIN 0
|
||||
#define GMU_MX_DOMAIN 1
|
||||
u16 feature_rev;
|
||||
struct a6xx_hfi_limits_cfg cfg;
|
||||
} __packed;
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -6,85 +6,10 @@
|
|||
#include "msm_gem.h"
|
||||
#include "a6xx_gpu.h"
|
||||
#include "a6xx_gmu.xml.h"
|
||||
#include "a6xx_preempt.h"
|
||||
#include "msm_mmu.h"
|
||||
#include "msm_gpu_trace.h"
|
||||
|
||||
/*
|
||||
* Try to transition the preemption state from old to new. Return
|
||||
* true on success or false if the original state wasn't 'old'
|
||||
*/
|
||||
static inline bool try_preempt_state(struct a6xx_gpu *a6xx_gpu,
|
||||
enum a6xx_preempt_state old, enum a6xx_preempt_state new)
|
||||
{
|
||||
enum a6xx_preempt_state cur = atomic_cmpxchg(&a6xx_gpu->preempt_state,
|
||||
old, new);
|
||||
|
||||
return (cur == old);
|
||||
}
|
||||
|
||||
/*
|
||||
* Force the preemption state to the specified state. This is used in cases
|
||||
* where the current state is known and won't change
|
||||
*/
|
||||
static inline void set_preempt_state(struct a6xx_gpu *gpu,
|
||||
enum a6xx_preempt_state new)
|
||||
{
|
||||
/*
|
||||
* preempt_state may be read by other cores trying to trigger a
|
||||
* preemption or in the interrupt handler so barriers are needed
|
||||
* before...
|
||||
*/
|
||||
smp_mb__before_atomic();
|
||||
atomic_set(&gpu->preempt_state, new);
|
||||
/* ... and after*/
|
||||
smp_mb__after_atomic();
|
||||
}
|
||||
|
||||
/* Write the most recent wptr for the given ring into the hardware */
|
||||
static inline void update_wptr(struct a6xx_gpu *a6xx_gpu, struct msm_ringbuffer *ring)
|
||||
{
|
||||
unsigned long flags;
|
||||
uint32_t wptr;
|
||||
|
||||
spin_lock_irqsave(&ring->preempt_lock, flags);
|
||||
|
||||
if (ring->restore_wptr) {
|
||||
wptr = get_wptr(ring);
|
||||
|
||||
a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_RB_WPTR, wptr, BIT(0), false);
|
||||
|
||||
ring->restore_wptr = false;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&ring->preempt_lock, flags);
|
||||
}
|
||||
|
||||
/* Return the highest priority ringbuffer with something in it */
|
||||
static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < gpu->nr_rings; i++) {
|
||||
bool empty;
|
||||
struct msm_ringbuffer *ring = gpu->rb[i];
|
||||
|
||||
spin_lock_irqsave(&ring->preempt_lock, flags);
|
||||
empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring));
|
||||
if (!empty && ring == a6xx_gpu->cur_ring)
|
||||
empty = ring->memptrs->fence == a6xx_gpu->last_seqno[i];
|
||||
spin_unlock_irqrestore(&ring->preempt_lock, flags);
|
||||
|
||||
if (!empty)
|
||||
return ring;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void a6xx_preempt_timer(struct timer_list *t)
|
||||
{
|
||||
struct a6xx_gpu *a6xx_gpu = timer_container_of(a6xx_gpu, t,
|
||||
|
|
|
|||
82
drivers/gpu/drm/msm/adreno/a6xx_preempt.h
Normal file
82
drivers/gpu/drm/msm/adreno/a6xx_preempt.h
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
|
||||
/* Copyright (c) 2023 Collabora, Ltd. */
|
||||
/* Copyright (c) 2024 Valve Corporation */
|
||||
/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */
|
||||
|
||||
/*
|
||||
* Try to transition the preemption state from old to new. Return
|
||||
* true on success or false if the original state wasn't 'old'
|
||||
*/
|
||||
static inline bool try_preempt_state(struct a6xx_gpu *a6xx_gpu,
|
||||
enum a6xx_preempt_state old, enum a6xx_preempt_state new)
|
||||
{
|
||||
enum a6xx_preempt_state cur = atomic_cmpxchg(&a6xx_gpu->preempt_state,
|
||||
old, new);
|
||||
|
||||
return (cur == old);
|
||||
}
|
||||
|
||||
/*
|
||||
* Force the preemption state to the specified state. This is used in cases
|
||||
* where the current state is known and won't change
|
||||
*/
|
||||
static inline void set_preempt_state(struct a6xx_gpu *gpu,
|
||||
enum a6xx_preempt_state new)
|
||||
{
|
||||
/*
|
||||
* preempt_state may be read by other cores trying to trigger a
|
||||
* preemption or in the interrupt handler so barriers are needed
|
||||
* before...
|
||||
*/
|
||||
smp_mb__before_atomic();
|
||||
atomic_set(&gpu->preempt_state, new);
|
||||
/* ... and after */
|
||||
smp_mb__after_atomic();
|
||||
}
|
||||
|
||||
/* Write the most recent wptr for the given ring into the hardware */
|
||||
static inline void update_wptr(struct a6xx_gpu *a6xx_gpu, struct msm_ringbuffer *ring)
|
||||
{
|
||||
unsigned long flags;
|
||||
uint32_t wptr;
|
||||
|
||||
spin_lock_irqsave(&ring->preempt_lock, flags);
|
||||
|
||||
if (ring->restore_wptr) {
|
||||
wptr = get_wptr(ring);
|
||||
|
||||
a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_RB_WPTR, wptr, BIT(0), false);
|
||||
|
||||
ring->restore_wptr = false;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&ring->preempt_lock, flags);
|
||||
}
|
||||
|
||||
/* Return the highest priority ringbuffer with something in it */
|
||||
static inline struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
|
||||
unsigned long flags;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < gpu->nr_rings; i++) {
|
||||
bool empty;
|
||||
struct msm_ringbuffer *ring = gpu->rb[i];
|
||||
|
||||
spin_lock_irqsave(&ring->preempt_lock, flags);
|
||||
empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring));
|
||||
if (!empty && ring == a6xx_gpu->cur_ring)
|
||||
empty = ring->memptrs->fence == a6xx_gpu->last_seqno[i];
|
||||
spin_unlock_irqrestore(&ring->preempt_lock, flags);
|
||||
|
||||
if (!empty)
|
||||
return ring;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
|
@ -87,6 +87,7 @@ void a8xx_gpu_get_slice_info(struct msm_gpu *gpu)
|
|||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
const struct a6xx_info *info = adreno_gpu->info->a6xx;
|
||||
struct device *dev = &gpu->pdev->dev;
|
||||
u32 slice_mask;
|
||||
|
||||
if (adreno_gpu->info->family < ADRENO_8XX_GEN1)
|
||||
|
|
@ -110,6 +111,15 @@ void a8xx_gpu_get_slice_info(struct msm_gpu *gpu)
|
|||
|
||||
/* Chip ID depends on the number of slices available. So update it */
|
||||
adreno_gpu->chip_id |= FIELD_PREP(GENMASK(7, 4), hweight32(slice_mask));
|
||||
|
||||
/* Update the gpu-name to reflect the slice config: */
|
||||
const char *name = devm_kasprintf(dev, GFP_KERNEL,
|
||||
"%"ADRENO_CHIPID_FMT,
|
||||
ADRENO_CHIPID_ARGS(adreno_gpu->chip_id));
|
||||
if (name) {
|
||||
devm_kfree(dev, adreno_gpu->base.name);
|
||||
adreno_gpu->base.name = name;
|
||||
}
|
||||
}
|
||||
|
||||
static u32 a8xx_get_first_slice(struct a6xx_gpu *a6xx_gpu)
|
||||
|
|
@ -173,7 +183,7 @@ void a8xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
|
|||
/* Update HW if this is the current ring and we are not in preempt*/
|
||||
if (!a6xx_in_preempt(a6xx_gpu)) {
|
||||
if (a6xx_gpu->cur_ring == ring)
|
||||
gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
|
||||
a6xx_fenced_write(a6xx_gpu, REG_A6XX_CP_RB_WPTR, wptr, BIT(0), false);
|
||||
else
|
||||
ring->restore_wptr = true;
|
||||
} else {
|
||||
|
|
@ -386,8 +396,115 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect)
|
|||
a8xx_aperture_clear(gpu);
|
||||
}
|
||||
|
||||
static void a8xx_patch_pwrup_reglist(struct msm_gpu *gpu)
|
||||
{
|
||||
const struct adreno_reglist_pipe_list *dyn_pwrup_reglist;
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
const struct adreno_reglist_list *reglist;
|
||||
void *ptr = a6xx_gpu->pwrup_reglist_ptr;
|
||||
struct cpu_gpu_lock *lock = ptr;
|
||||
u32 *dest = (u32 *)&lock->regs[0];
|
||||
u32 dyn_pwrup_reglist_count = 0;
|
||||
int i;
|
||||
|
||||
lock->gpu_req = lock->cpu_req = lock->turn = 0;
|
||||
|
||||
reglist = adreno_gpu->info->a6xx->ifpc_reglist;
|
||||
if (reglist) {
|
||||
lock->ifpc_list_len = reglist->count;
|
||||
|
||||
/*
|
||||
* For each entry in each of the lists, write the offset and the current
|
||||
* register value into the GPU buffer
|
||||
*/
|
||||
for (i = 0; i < reglist->count; i++) {
|
||||
*dest++ = reglist->regs[i];
|
||||
*dest++ = gpu_read(gpu, reglist->regs[i]);
|
||||
}
|
||||
}
|
||||
|
||||
reglist = adreno_gpu->info->a6xx->pwrup_reglist;
|
||||
if (reglist) {
|
||||
lock->preemption_list_len = reglist->count;
|
||||
|
||||
for (i = 0; i < reglist->count; i++) {
|
||||
*dest++ = reglist->regs[i];
|
||||
*dest++ = gpu_read(gpu, reglist->regs[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* The overall register list is composed of
|
||||
* 1. Static IFPC-only registers
|
||||
* 2. Static IFPC + preemption registers
|
||||
* 3. Dynamic IFPC + preemption registers (ex: perfcounter selects)
|
||||
*
|
||||
* The first two lists are static. Size of these lists are stored as
|
||||
* number of pairs in ifpc_list_len and preemption_list_len
|
||||
* respectively. With concurrent binning, Some of the perfcounter
|
||||
* registers being virtualized, CP needs to know the pipe id to program
|
||||
* the aperture inorder to restore the same. Thus, third list is a
|
||||
* dynamic list with triplets as
|
||||
* (<aperture, shifted 12 bits> <address> <data>), and the length is
|
||||
* stored as number for triplets in dynamic_list_len.
|
||||
*/
|
||||
dyn_pwrup_reglist = adreno_gpu->info->a6xx->dyn_pwrup_reglist;
|
||||
if (!dyn_pwrup_reglist)
|
||||
goto done;
|
||||
|
||||
for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_DDE_BV; pipe_id++) {
|
||||
for (i = 0; i < dyn_pwrup_reglist->count; i++) {
|
||||
if (!(dyn_pwrup_reglist->regs[i].pipe & BIT(pipe_id)))
|
||||
continue;
|
||||
*dest++ = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe_id);
|
||||
*dest++ = dyn_pwrup_reglist->regs[i].offset;
|
||||
*dest++ = a8xx_read_pipe_slice(gpu,
|
||||
pipe_id,
|
||||
a8xx_get_first_slice(a6xx_gpu),
|
||||
dyn_pwrup_reglist->regs[i].offset);
|
||||
dyn_pwrup_reglist_count++;
|
||||
}
|
||||
}
|
||||
|
||||
lock->dynamic_list_len = dyn_pwrup_reglist_count;
|
||||
|
||||
done:
|
||||
a8xx_aperture_clear(gpu);
|
||||
}
|
||||
|
||||
static int a8xx_preempt_start(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
struct msm_ringbuffer *ring = gpu->rb[0];
|
||||
|
||||
if (gpu->nr_rings <= 1)
|
||||
return 0;
|
||||
|
||||
/* Turn CP protection off */
|
||||
OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
|
||||
OUT_RING(ring, 0);
|
||||
|
||||
a6xx_emit_set_pseudo_reg(ring, a6xx_gpu, NULL);
|
||||
|
||||
/* Yield the floor on command completion */
|
||||
OUT_PKT7(ring, CP_CONTEXT_SWITCH_YIELD, 4);
|
||||
OUT_RING(ring, 0x00);
|
||||
OUT_RING(ring, 0x00);
|
||||
OUT_RING(ring, 0x00);
|
||||
/* Generate interrupt on preemption completion */
|
||||
OUT_RING(ring, 0x00);
|
||||
|
||||
a6xx_flush(gpu, ring);
|
||||
|
||||
return a8xx_idle(gpu, ring) ? 0 : -EINVAL;
|
||||
}
|
||||
|
||||
static int a8xx_cp_init(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
struct msm_ringbuffer *ring = gpu->rb[0];
|
||||
u32 mask;
|
||||
|
||||
|
|
@ -395,7 +512,7 @@ static int a8xx_cp_init(struct msm_gpu *gpu)
|
|||
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
|
||||
OUT_RING(ring, BIT(27));
|
||||
|
||||
OUT_PKT7(ring, CP_ME_INIT, 4);
|
||||
OUT_PKT7(ring, CP_ME_INIT, 7);
|
||||
|
||||
/* Use multiple HW contexts */
|
||||
mask = BIT(0);
|
||||
|
|
@ -409,6 +526,9 @@ static int a8xx_cp_init(struct msm_gpu *gpu)
|
|||
/* Disable save/restore of performance counters across preemption */
|
||||
mask |= BIT(6);
|
||||
|
||||
/* Enable the register init list with the spinlock */
|
||||
mask |= BIT(8);
|
||||
|
||||
OUT_RING(ring, mask);
|
||||
|
||||
/* Enable multiple hardware contexts */
|
||||
|
|
@ -420,6 +540,14 @@ static int a8xx_cp_init(struct msm_gpu *gpu)
|
|||
/* Operation mode mask */
|
||||
OUT_RING(ring, 0x00000002);
|
||||
|
||||
/* Lo address */
|
||||
OUT_RING(ring, lower_32_bits(a6xx_gpu->pwrup_reglist_iova));
|
||||
/* Hi address */
|
||||
OUT_RING(ring, upper_32_bits(a6xx_gpu->pwrup_reglist_iova));
|
||||
|
||||
/* Enable dyn pwrup list with triplets (offset, value, pipe) */
|
||||
OUT_RING(ring, BIT(31));
|
||||
|
||||
a6xx_flush(gpu, ring);
|
||||
return a8xx_idle(gpu, ring) ? 0 : -EINVAL;
|
||||
}
|
||||
|
|
@ -648,6 +776,8 @@ static int hw_init(struct msm_gpu *gpu)
|
|||
gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, shadowptr(a6xx_gpu, gpu->rb[0]));
|
||||
gpu_write64(gpu, REG_A8XX_CP_RB_RPTR_ADDR_BV, rbmemptr(gpu->rb[0], bv_rptr));
|
||||
|
||||
a8xx_preempt_hw_init(gpu);
|
||||
|
||||
for (i = 0; i < gpu->nr_rings; i++)
|
||||
a6xx_gpu->shadow[i] = 0;
|
||||
|
||||
|
|
@ -702,15 +832,29 @@ static int hw_init(struct msm_gpu *gpu)
|
|||
WARN_ON(!gmem_protect);
|
||||
a8xx_aperture_clear(gpu);
|
||||
|
||||
if (!a6xx_gpu->pwrup_reglist_emitted) {
|
||||
a8xx_patch_pwrup_reglist(gpu);
|
||||
a6xx_gpu->pwrup_reglist_emitted = true;
|
||||
}
|
||||
|
||||
/* Enable hardware clockgating */
|
||||
a8xx_set_hwcg(gpu, true);
|
||||
out:
|
||||
/* Last step - yield the ringbuffer */
|
||||
a8xx_preempt_start(gpu);
|
||||
|
||||
/*
|
||||
* Tell the GMU that we are done touching the GPU and it can start power
|
||||
* management
|
||||
*/
|
||||
a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
|
||||
|
||||
if (!ret && (refcount_read(&gpu->sysprof_active) > 1)) {
|
||||
ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET);
|
||||
if (!ret)
|
||||
set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1108,11 +1252,11 @@ irqreturn_t a8xx_irq(struct msm_gpu *gpu)
|
|||
|
||||
if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) {
|
||||
msm_gpu_retire(gpu);
|
||||
a6xx_preempt_trigger(gpu);
|
||||
a8xx_preempt_trigger(gpu);
|
||||
}
|
||||
|
||||
if (status & A6XX_RBBM_INT_0_MASK_CP_SW)
|
||||
a6xx_preempt_irq(gpu);
|
||||
a8xx_preempt_irq(gpu);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
|
@ -1174,23 +1318,19 @@ void a8xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_
|
|||
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
|
||||
}
|
||||
|
||||
int a8xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
|
||||
u64 a8xx_gmu_get_timestamp(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
u64 count_hi, count_lo, temp;
|
||||
|
||||
mutex_lock(&a6xx_gpu->gmu.lock);
|
||||
do {
|
||||
count_hi = gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_H);
|
||||
count_lo = gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_L);
|
||||
temp = gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_H);
|
||||
} while (unlikely(count_hi != temp));
|
||||
|
||||
/* Force the GPU power on so we can read this register */
|
||||
a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
|
||||
|
||||
*value = gpu_read64(gpu, REG_A8XX_CP_ALWAYS_ON_COUNTER);
|
||||
|
||||
a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
|
||||
|
||||
mutex_unlock(&a6xx_gpu->gmu.lock);
|
||||
|
||||
return 0;
|
||||
return (count_hi << 32) | count_lo;
|
||||
}
|
||||
|
||||
u64 a8xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)
|
||||
|
|
|
|||
259
drivers/gpu/drm/msm/adreno/a8xx_preempt.c
Normal file
259
drivers/gpu/drm/msm/adreno/a8xx_preempt.c
Normal file
|
|
@ -0,0 +1,259 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */
|
||||
|
||||
#include "msm_gem.h"
|
||||
#include "a6xx_gpu.h"
|
||||
#include "a6xx_gmu.xml.h"
|
||||
#include "a6xx_preempt.h"
|
||||
#include "msm_mmu.h"
|
||||
#include "msm_gpu_trace.h"
|
||||
|
||||
static void preempt_prepare_postamble(struct a6xx_gpu *a6xx_gpu)
|
||||
{
|
||||
u32 *postamble = a6xx_gpu->preempt_postamble_ptr;
|
||||
u32 count = 0;
|
||||
|
||||
postamble[count++] = PKT7(CP_REG_RMW, 3);
|
||||
postamble[count++] = REG_A8XX_RBBM_PERFCTR_SRAM_INIT_CMD;
|
||||
postamble[count++] = 0;
|
||||
postamble[count++] = 1;
|
||||
|
||||
postamble[count++] = PKT7(CP_WAIT_REG_MEM, 6);
|
||||
postamble[count++] = CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ);
|
||||
postamble[count++] = CP_WAIT_REG_MEM_POLL_ADDR_LO(
|
||||
REG_A8XX_RBBM_PERFCTR_SRAM_INIT_STATUS);
|
||||
postamble[count++] = CP_WAIT_REG_MEM_POLL_ADDR_HI(0);
|
||||
postamble[count++] = CP_WAIT_REG_MEM_3_REF(0x1);
|
||||
postamble[count++] = CP_WAIT_REG_MEM_4_MASK(0x1);
|
||||
postamble[count++] = CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0);
|
||||
|
||||
a6xx_gpu->preempt_postamble_len = count;
|
||||
|
||||
a6xx_gpu->postamble_enabled = true;
|
||||
}
|
||||
|
||||
static void preempt_disable_postamble(struct a6xx_gpu *a6xx_gpu)
|
||||
{
|
||||
u32 *postamble = a6xx_gpu->preempt_postamble_ptr;
|
||||
|
||||
/*
|
||||
* Disable the postamble by replacing the first packet header with a NOP
|
||||
* that covers the whole buffer.
|
||||
*/
|
||||
*postamble = PKT7(CP_NOP, (a6xx_gpu->preempt_postamble_len - 1));
|
||||
|
||||
a6xx_gpu->postamble_enabled = false;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set preemption keepalive vote. Please note that this vote is different from the one used in
|
||||
* a8xx_irq()
|
||||
*/
|
||||
static void a8xx_preempt_keepalive_vote(struct msm_gpu *gpu, bool on)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
|
||||
gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_PWR_COL_PREEMPT_KEEPALIVE, on);
|
||||
}
|
||||
|
||||
void a8xx_preempt_irq(struct msm_gpu *gpu)
|
||||
{
|
||||
uint32_t status;
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
struct drm_device *dev = gpu->dev;
|
||||
|
||||
if (!try_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED, PREEMPT_PENDING))
|
||||
return;
|
||||
|
||||
/* Delete the preemption watchdog timer */
|
||||
timer_delete(&a6xx_gpu->preempt_timer);
|
||||
|
||||
/*
|
||||
* The hardware should be setting the stop bit of CP_CONTEXT_SWITCH_CNTL
|
||||
* to zero before firing the interrupt, but there is a non zero chance
|
||||
* of a hardware condition or a software race that could set it again
|
||||
* before we have a chance to finish. If that happens, log and go for
|
||||
* recovery
|
||||
*/
|
||||
status = gpu_read(gpu, REG_A8XX_CP_CONTEXT_SWITCH_CNTL);
|
||||
if (unlikely(status & A8XX_CP_CONTEXT_SWITCH_CNTL_STOP)) {
|
||||
DRM_DEV_ERROR(&gpu->pdev->dev,
|
||||
"!!!!!!!!!!!!!!!! preemption faulted !!!!!!!!!!!!!! irq\n");
|
||||
set_preempt_state(a6xx_gpu, PREEMPT_FAULTED);
|
||||
dev_err(dev->dev, "%s: Preemption failed to complete\n",
|
||||
gpu->name);
|
||||
kthread_queue_work(gpu->worker, &gpu->recover_work);
|
||||
return;
|
||||
}
|
||||
|
||||
a6xx_gpu->cur_ring = a6xx_gpu->next_ring;
|
||||
a6xx_gpu->next_ring = NULL;
|
||||
|
||||
set_preempt_state(a6xx_gpu, PREEMPT_FINISH);
|
||||
|
||||
update_wptr(a6xx_gpu, a6xx_gpu->cur_ring);
|
||||
|
||||
set_preempt_state(a6xx_gpu, PREEMPT_NONE);
|
||||
|
||||
a8xx_preempt_keepalive_vote(gpu, false);
|
||||
|
||||
trace_msm_gpu_preemption_irq(a6xx_gpu->cur_ring->id);
|
||||
|
||||
/*
|
||||
* Retrigger preemption to avoid a deadlock that might occur when preemption
|
||||
* is skipped due to it being already in flight when requested.
|
||||
*/
|
||||
a8xx_preempt_trigger(gpu);
|
||||
}
|
||||
|
||||
void a8xx_preempt_hw_init(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
int i;
|
||||
|
||||
/* No preemption if we only have one ring */
|
||||
if (gpu->nr_rings == 1)
|
||||
return;
|
||||
|
||||
for (i = 0; i < gpu->nr_rings; i++) {
|
||||
struct a6xx_preempt_record *record_ptr = a6xx_gpu->preempt[i];
|
||||
|
||||
record_ptr->wptr = 0;
|
||||
record_ptr->rptr = 0;
|
||||
record_ptr->rptr_addr = shadowptr(a6xx_gpu, gpu->rb[i]);
|
||||
record_ptr->info = 0;
|
||||
record_ptr->data = 0;
|
||||
record_ptr->rbase = gpu->rb[i]->iova;
|
||||
}
|
||||
|
||||
/* Write a 0 to signal that we aren't switching pagetables */
|
||||
gpu_write64(gpu, REG_A8XX_CP_CONTEXT_SWITCH_SMMU_INFO, 0);
|
||||
|
||||
/* Enable the GMEM save/restore feature for preemption */
|
||||
gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0x1);
|
||||
|
||||
/* Reset the preemption state */
|
||||
set_preempt_state(a6xx_gpu, PREEMPT_NONE);
|
||||
|
||||
spin_lock_init(&a6xx_gpu->eval_lock);
|
||||
|
||||
/* Always come up on rb 0 */
|
||||
a6xx_gpu->cur_ring = gpu->rb[0];
|
||||
}
|
||||
|
||||
void a8xx_preempt_trigger(struct msm_gpu *gpu)
|
||||
{
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
|
||||
unsigned long flags;
|
||||
struct msm_ringbuffer *ring;
|
||||
unsigned int cntl;
|
||||
bool sysprof;
|
||||
|
||||
if (gpu->nr_rings == 1)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Lock to make sure another thread attempting preemption doesn't skip it
|
||||
* while we are still evaluating the next ring. This makes sure the other
|
||||
* thread does start preemption if we abort it and avoids a soft lock.
|
||||
*/
|
||||
spin_lock_irqsave(&a6xx_gpu->eval_lock, flags);
|
||||
|
||||
/*
|
||||
* Try to start preemption by moving from NONE to START. If
|
||||
* unsuccessful, a preemption is already in flight
|
||||
*/
|
||||
if (!try_preempt_state(a6xx_gpu, PREEMPT_NONE, PREEMPT_START)) {
|
||||
spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags);
|
||||
return;
|
||||
}
|
||||
|
||||
cntl = A8XX_CP_CONTEXT_SWITCH_CNTL_LEVEL(a6xx_gpu->preempt_level);
|
||||
|
||||
if (a6xx_gpu->skip_save_restore)
|
||||
cntl |= A8XX_CP_CONTEXT_SWITCH_CNTL_SKIP_SAVE_RESTORE;
|
||||
|
||||
if (a6xx_gpu->uses_gmem)
|
||||
cntl |= A8XX_CP_CONTEXT_SWITCH_CNTL_USES_GMEM;
|
||||
|
||||
cntl |= A8XX_CP_CONTEXT_SWITCH_CNTL_STOP;
|
||||
|
||||
/* Get the next ring to preempt to */
|
||||
ring = get_next_ring(gpu);
|
||||
|
||||
/*
|
||||
* If no ring is populated or the highest priority ring is the current
|
||||
* one do nothing except to update the wptr to the latest and greatest
|
||||
*/
|
||||
if (!ring || (a6xx_gpu->cur_ring == ring)) {
|
||||
set_preempt_state(a6xx_gpu, PREEMPT_FINISH);
|
||||
update_wptr(a6xx_gpu, a6xx_gpu->cur_ring);
|
||||
set_preempt_state(a6xx_gpu, PREEMPT_NONE);
|
||||
spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags);
|
||||
return;
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&a6xx_gpu->eval_lock, flags);
|
||||
|
||||
spin_lock_irqsave(&ring->preempt_lock, flags);
|
||||
|
||||
struct a7xx_cp_smmu_info *smmu_info_ptr =
|
||||
a6xx_gpu->preempt_smmu[ring->id];
|
||||
struct a6xx_preempt_record *record_ptr = a6xx_gpu->preempt[ring->id];
|
||||
u64 ttbr0 = ring->memptrs->ttbr0;
|
||||
u32 context_idr = ring->memptrs->context_idr;
|
||||
|
||||
smmu_info_ptr->ttbr0 = ttbr0;
|
||||
smmu_info_ptr->context_idr = context_idr;
|
||||
record_ptr->wptr = get_wptr(ring);
|
||||
|
||||
/*
|
||||
* The GPU will write the wptr we set above when we preempt. Reset
|
||||
* restore_wptr to make sure that we don't write WPTR to the same
|
||||
* thing twice. It's still possible subsequent submissions will update
|
||||
* wptr again, in which case they will set the flag to true. This has
|
||||
* to be protected by the lock for setting the flag and updating wptr
|
||||
* to be atomic.
|
||||
*/
|
||||
ring->restore_wptr = false;
|
||||
|
||||
trace_msm_gpu_preemption_trigger(a6xx_gpu->cur_ring->id, ring->id);
|
||||
|
||||
spin_unlock_irqrestore(&ring->preempt_lock, flags);
|
||||
|
||||
/* Set the keepalive bit to keep the GPU ON until preemption is complete */
|
||||
a8xx_preempt_keepalive_vote(gpu, true);
|
||||
|
||||
a6xx_fenced_write(a6xx_gpu,
|
||||
REG_A8XX_CP_CONTEXT_SWITCH_SMMU_INFO, a6xx_gpu->preempt_smmu_iova[ring->id],
|
||||
BIT(1), true);
|
||||
|
||||
a6xx_fenced_write(a6xx_gpu,
|
||||
REG_A8XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR,
|
||||
a6xx_gpu->preempt_iova[ring->id], BIT(1), true);
|
||||
|
||||
a6xx_gpu->next_ring = ring;
|
||||
|
||||
/* Start a timer to catch a stuck preemption */
|
||||
mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000));
|
||||
|
||||
/* Enable or disable postamble as needed */
|
||||
sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1;
|
||||
|
||||
if (!sysprof && !a6xx_gpu->postamble_enabled)
|
||||
preempt_prepare_postamble(a6xx_gpu);
|
||||
|
||||
if (sysprof && a6xx_gpu->postamble_enabled)
|
||||
preempt_disable_postamble(a6xx_gpu);
|
||||
|
||||
/* Set the preemption state to triggered */
|
||||
set_preempt_state(a6xx_gpu, PREEMPT_TRIGGERED);
|
||||
|
||||
/* Trigger the preemption */
|
||||
a6xx_fenced_write(a6xx_gpu, REG_A8XX_CP_CONTEXT_SWITCH_CNTL, cntl, BIT(1), false);
|
||||
}
|
||||
|
||||
|
|
@ -45,8 +45,8 @@ static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
np = of_get_child_by_name(dev->of_node, "zap-shader");
|
||||
if (!of_device_is_available(np)) {
|
||||
np = of_get_available_child_by_name(dev->of_node, "zap-shader");
|
||||
if (!np) {
|
||||
zap_available = false;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
|
@ -391,13 +391,11 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
|
|||
return 0;
|
||||
case MSM_PARAM_TIMESTAMP:
|
||||
if (adreno_gpu->funcs->get_timestamp) {
|
||||
int ret;
|
||||
|
||||
pm_runtime_get_sync(&gpu->pdev->dev);
|
||||
ret = adreno_gpu->funcs->get_timestamp(gpu, value);
|
||||
*value = adreno_gpu->funcs->get_timestamp(gpu);
|
||||
pm_runtime_put_autosuspend(&gpu->pdev->dev);
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
return -EINVAL;
|
||||
case MSM_PARAM_PRIORITIES:
|
||||
|
|
@ -443,6 +441,10 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_context *ctx,
|
|||
case MSM_PARAM_HAS_PRR:
|
||||
*value = adreno_smmu_has_prr(gpu);
|
||||
return 0;
|
||||
case MSM_PARAM_AQE:
|
||||
*value = !!(adreno_gpu->funcs->aqe_is_enabled &&
|
||||
adreno_gpu->funcs->aqe_is_enabled(adreno_gpu));
|
||||
return 0;
|
||||
default:
|
||||
return UERR(EINVAL, drm, "%s: invalid param: %u", gpu->name, param);
|
||||
}
|
||||
|
|
@ -1184,7 +1186,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|||
struct msm_gpu_config adreno_gpu_config = { 0 };
|
||||
struct msm_gpu *gpu = &adreno_gpu->base;
|
||||
const char *gpu_name;
|
||||
u32 speedbin;
|
||||
int ret;
|
||||
|
||||
adreno_gpu->funcs = funcs;
|
||||
|
|
@ -1213,10 +1214,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|||
devm_pm_opp_set_clkname(dev, "core");
|
||||
}
|
||||
|
||||
if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
|
||||
speedbin = 0xffff;
|
||||
adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
|
||||
|
||||
gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
|
||||
ADRENO_CHIPID_ARGS(config->chip_id));
|
||||
if (!gpu_name)
|
||||
|
|
|
|||
|
|
@ -63,25 +63,24 @@ enum adreno_family {
|
|||
#define ADRENO_QUIRK_PREEMPTION BIT(5)
|
||||
#define ADRENO_QUIRK_4GB_VA BIT(6)
|
||||
#define ADRENO_QUIRK_IFPC BIT(7)
|
||||
#define ADRENO_QUIRK_SOFTFUSE BIT(8)
|
||||
|
||||
/* Helper for formating the chip_id in the way that userspace tools like
|
||||
* crashdec expect.
|
||||
*/
|
||||
#define ADRENO_CHIPID_FMT "u.%u.%u.%u"
|
||||
#define ADRENO_CHIPID_ARGS(_c) \
|
||||
(((_c) >> 24) & 0xff), \
|
||||
(((_c) >> 16) & 0xff), \
|
||||
(((_c) >> 8) & 0xff), \
|
||||
((_c) & 0xff)
|
||||
#define ADRENO_CHIPID_FMT "08x"
|
||||
#define ADRENO_CHIPID_ARGS(_c) (_c)
|
||||
|
||||
struct adreno_gpu;
|
||||
|
||||
struct adreno_gpu_funcs {
|
||||
struct msm_gpu_funcs base;
|
||||
struct msm_gpu *(*init)(struct drm_device *dev);
|
||||
int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
|
||||
u64 (*get_timestamp)(struct msm_gpu *gpu);
|
||||
void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off);
|
||||
int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data);
|
||||
bool (*gx_is_on)(struct adreno_gpu *adreno_gpu);
|
||||
bool (*aqe_is_enabled)(struct adreno_gpu *adreno_gpu);
|
||||
};
|
||||
|
||||
struct adreno_reglist {
|
||||
|
|
|
|||
|
|
@ -322,7 +322,6 @@ static const struct dpu_wb_cfg sm8650_wb[] = {
|
|||
.format_list = wb2_formats_rgb_yuv,
|
||||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -378,7 +377,7 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
|
|||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x37000, .len = 0x280,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
|
|
@ -445,8 +444,7 @@ const struct dpu_mdss_cfg dpu_sm8650_cfg = {
|
|||
.cwb = sm8650_cwb,
|
||||
.intf_count = ARRAY_SIZE(sm8650_intf),
|
||||
.intf = sm8650_intf,
|
||||
.vbif_count = ARRAY_SIZE(sm8650_vbif),
|
||||
.vbif = sm8650_vbif,
|
||||
.vbif = &sm8650_vbif,
|
||||
.perf = &sm8650_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -364,7 +364,6 @@ static const struct dpu_wb_cfg sm8750_wb[] = {
|
|||
.format_list = wb2_formats_rgb_yuv,
|
||||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -420,7 +419,7 @@ static const struct dpu_intf_cfg sm8750_intf[] = {
|
|||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x37000, .len = 0x4bc,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
|
|
@ -486,8 +485,7 @@ const struct dpu_mdss_cfg dpu_sm8750_cfg = {
|
|||
.cwb = sm8650_cwb,
|
||||
.intf_count = ARRAY_SIZE(sm8750_intf),
|
||||
.intf = sm8750_intf,
|
||||
.vbif_count = ARRAY_SIZE(sm8650_vbif),
|
||||
.vbif = sm8650_vbif,
|
||||
.vbif = &sm8650_vbif,
|
||||
.perf = &sm8750_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -371,7 +371,6 @@ static const struct dpu_wb_cfg glymur_wb[] = {
|
|||
.format_list = wb2_formats_rgb_yuv,
|
||||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -426,7 +425,7 @@ static const struct dpu_intf_cfg glymur_intf[] = {
|
|||
}, {
|
||||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x37000, .len = 0x400,
|
||||
.type = INTF_NONE,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
|
|
@ -458,7 +457,7 @@ static const struct dpu_intf_cfg glymur_intf[] = {
|
|||
}, {
|
||||
.name = "intf_7", .id = INTF_7,
|
||||
.base = 0x3b000, .len = 0x400,
|
||||
.type = INTF_NONE,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
|
||||
|
|
@ -466,7 +465,7 @@ static const struct dpu_intf_cfg glymur_intf[] = {
|
|||
}, {
|
||||
.name = "intf_8", .id = INTF_8,
|
||||
.base = 0x3c000, .len = 0x400,
|
||||
.type = INTF_NONE,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
|
||||
|
|
@ -533,8 +532,7 @@ const struct dpu_mdss_cfg dpu_glymur_cfg = {
|
|||
.cwb = sm8650_cwb,
|
||||
.intf_count = ARRAY_SIZE(glymur_intf),
|
||||
.intf = glymur_intf,
|
||||
.vbif_count = ARRAY_SIZE(sm8650_vbif),
|
||||
.vbif = sm8650_vbif,
|
||||
.vbif = &sm8650_vbif,
|
||||
.perf = &glymur_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
363
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h
Normal file
363
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h
Normal file
|
|
@ -0,0 +1,363 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _DPU_12_4_ELIZA_H
|
||||
#define _DPU_12_4_ELIZA_H
|
||||
|
||||
static const struct dpu_caps eliza_dpu_caps = {
|
||||
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
|
||||
.max_mixer_blendstages = 0xb,
|
||||
.has_src_split = true,
|
||||
.has_dim_layer = true,
|
||||
.has_idle_pc = true,
|
||||
.has_3d_merge = true,
|
||||
.max_linewidth = 8192,
|
||||
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
|
||||
};
|
||||
|
||||
static const struct dpu_mdp_cfg eliza_mdp = {
|
||||
.name = "top_0",
|
||||
.base = 0, .len = 0x494,
|
||||
.clk_ctrls = {
|
||||
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_ctl_cfg eliza_ctl[] = {
|
||||
{
|
||||
.name = "ctl_0", .id = CTL_0,
|
||||
.base = 0x15000, .len = 0x1000,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
|
||||
}, {
|
||||
.name = "ctl_1", .id = CTL_1,
|
||||
.base = 0x16000, .len = 0x1000,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
|
||||
}, {
|
||||
.name = "ctl_2", .id = CTL_2,
|
||||
.base = 0x17000, .len = 0x1000,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
|
||||
}, {
|
||||
.name = "ctl_3", .id = CTL_3,
|
||||
.base = 0x18000, .len = 0x1000,
|
||||
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_sspp_cfg eliza_sspp[] = {
|
||||
{
|
||||
.name = "sspp_0", .id = SSPP_VIG0,
|
||||
.base = 0x4000, .len = 0x344,
|
||||
.features = VIG_SDM845_MASK_SDMA,
|
||||
.sblk = &dpu_vig_sblk_qseed3_3_4,
|
||||
.xin_id = 0,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
}, {
|
||||
.name = "sspp_1", .id = SSPP_VIG1,
|
||||
.base = 0x6000, .len = 0x344,
|
||||
.features = VIG_SDM845_MASK_SDMA,
|
||||
.sblk = &dpu_vig_sblk_qseed3_3_4,
|
||||
.xin_id = 4,
|
||||
.type = SSPP_TYPE_VIG,
|
||||
}, {
|
||||
.name = "sspp_8", .id = SSPP_DMA0,
|
||||
.base = 0x24000, .len = 0x344,
|
||||
.features = DMA_SDM845_MASK_SDMA,
|
||||
.sblk = &dpu_dma_sblk,
|
||||
.xin_id = 1,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
}, {
|
||||
.name = "sspp_9", .id = SSPP_DMA1,
|
||||
.base = 0x26000, .len = 0x344,
|
||||
.features = DMA_SDM845_MASK_SDMA,
|
||||
.sblk = &dpu_dma_sblk,
|
||||
.xin_id = 5,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
}, {
|
||||
.name = "sspp_10", .id = SSPP_DMA2,
|
||||
.base = 0x28000, .len = 0x344,
|
||||
.features = DMA_SDM845_MASK_SDMA,
|
||||
.sblk = &dpu_dma_sblk,
|
||||
.xin_id = 9,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
}, {
|
||||
.name = "sspp_11", .id = SSPP_DMA3,
|
||||
.base = 0x2a000, .len = 0x344,
|
||||
.features = DMA_SDM845_MASK_SDMA,
|
||||
.sblk = &dpu_dma_sblk,
|
||||
.xin_id = 13,
|
||||
.type = SSPP_TYPE_DMA,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_lm_cfg eliza_lm[] = {
|
||||
{
|
||||
.name = "lm_0", .id = LM_0,
|
||||
.base = 0x44000, .len = 0x400,
|
||||
.features = MIXER_MSM8998_MASK,
|
||||
.sblk = &sm8750_lm_sblk,
|
||||
.lm_pair = LM_1,
|
||||
.pingpong = PINGPONG_0,
|
||||
.dspp = DSPP_0,
|
||||
}, {
|
||||
.name = "lm_1", .id = LM_1,
|
||||
.base = 0x45000, .len = 0x400,
|
||||
.features = MIXER_MSM8998_MASK,
|
||||
.sblk = &sm8750_lm_sblk,
|
||||
.lm_pair = LM_0,
|
||||
.pingpong = PINGPONG_1,
|
||||
.dspp = DSPP_1,
|
||||
}, {
|
||||
.name = "lm_2", .id = LM_2,
|
||||
.base = 0x46000, .len = 0x400,
|
||||
.features = MIXER_MSM8998_MASK,
|
||||
.sblk = &sm8750_lm_sblk,
|
||||
.lm_pair = LM_3,
|
||||
.pingpong = PINGPONG_2,
|
||||
.dspp = DSPP_2,
|
||||
}, {
|
||||
.name = "lm_3", .id = LM_3,
|
||||
.base = 0x47000, .len = 0x400,
|
||||
.features = MIXER_MSM8998_MASK,
|
||||
.sblk = &sm8750_lm_sblk,
|
||||
.lm_pair = LM_2,
|
||||
.pingpong = PINGPONG_3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_dspp_cfg eliza_dspp[] = {
|
||||
{
|
||||
.name = "dspp_0", .id = DSPP_0,
|
||||
.base = 0x54000, .len = 0x1800,
|
||||
.sblk = &sm8750_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_1", .id = DSPP_1,
|
||||
.base = 0x56000, .len = 0x1800,
|
||||
.sblk = &sm8750_dspp_sblk,
|
||||
}, {
|
||||
.name = "dspp_2", .id = DSPP_2,
|
||||
.base = 0x58000, .len = 0x1800,
|
||||
.sblk = &sm8750_dspp_sblk,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_pingpong_cfg eliza_pp[] = {
|
||||
{
|
||||
.name = "pingpong_0", .id = PINGPONG_0,
|
||||
.base = 0x69000, .len = 0,
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
|
||||
}, {
|
||||
.name = "pingpong_1", .id = PINGPONG_1,
|
||||
.base = 0x6a000, .len = 0,
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_0,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
|
||||
}, {
|
||||
.name = "pingpong_2", .id = PINGPONG_2,
|
||||
.base = 0x6b000, .len = 0,
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
|
||||
}, {
|
||||
.name = "pingpong_3", .id = PINGPONG_3,
|
||||
.base = 0x6c000, .len = 0,
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_1,
|
||||
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
|
||||
}, {
|
||||
.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
|
||||
.base = 0x66000, .len = 0,
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
}, {
|
||||
.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
|
||||
.base = 0x66400, .len = 0,
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_2,
|
||||
}, {
|
||||
.name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,
|
||||
.base = 0x7e000, .len = 0,
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_3,
|
||||
}, {
|
||||
.name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,
|
||||
.base = 0x7e400, .len = 0,
|
||||
.sblk = &sc7280_pp_sblk,
|
||||
.merge_3d = MERGE_3D_3,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_merge_3d_cfg eliza_merge_3d[] = {
|
||||
{
|
||||
.name = "merge_3d_0", .id = MERGE_3D_0,
|
||||
.base = 0x4e000, .len = 0x1c,
|
||||
}, {
|
||||
.name = "merge_3d_1", .id = MERGE_3D_1,
|
||||
.base = 0x4f000, .len = 0x1c,
|
||||
}, {
|
||||
.name = "merge_3d_2", .id = MERGE_3D_2,
|
||||
.base = 0x66700, .len = 0x1c,
|
||||
}, {
|
||||
.name = "merge_3d_3", .id = MERGE_3D_3,
|
||||
.base = 0x7e700, .len = 0x1c,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* NOTE: Each display compression engine (DCE) contains dual hard
|
||||
* slice DSC encoders so both share same base address but with
|
||||
* its own different sub block address.
|
||||
*/
|
||||
static const struct dpu_dsc_cfg eliza_dsc[] = {
|
||||
{
|
||||
.name = "dce_0_0", .id = DSC_0,
|
||||
.base = 0x80000, .len = 0x8,
|
||||
.features = BIT(DPU_DSC_NATIVE_42x_EN),
|
||||
.sblk = &sm8750_dsc_sblk_0,
|
||||
}, {
|
||||
.name = "dce_0_1", .id = DSC_1,
|
||||
.base = 0x80000, .len = 0x8,
|
||||
.features = BIT(DPU_DSC_NATIVE_42x_EN),
|
||||
.sblk = &sm8750_dsc_sblk_1,
|
||||
}, {
|
||||
.name = "dce_1_0", .id = DSC_2,
|
||||
.base = 0x81000, .len = 0x8,
|
||||
.features = BIT(DPU_DSC_NATIVE_42x_EN),
|
||||
.sblk = &sm8750_dsc_sblk_0,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_wb_cfg eliza_wb[] = {
|
||||
{
|
||||
.name = "wb_2", .id = WB_2,
|
||||
.base = 0x65000, .len = 0x2c8,
|
||||
.features = WB_SDM845_MASK,
|
||||
.format_list = wb2_formats_rgb_yuv,
|
||||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.xin_id = 6,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_cwb_cfg eliza_cwb[] = {
|
||||
{
|
||||
.name = "cwb_0", .id = CWB_0,
|
||||
.base = 0x66200, .len = 0x20,
|
||||
},
|
||||
{
|
||||
.name = "cwb_1", .id = CWB_1,
|
||||
.base = 0x66600, .len = 0x20,
|
||||
},
|
||||
{
|
||||
.name = "cwb_2", .id = CWB_2,
|
||||
.base = 0x7e200, .len = 0x20,
|
||||
},
|
||||
{
|
||||
.name = "cwb_3", .id = CWB_3,
|
||||
.base = 0x7e600, .len = 0x20,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct dpu_intf_cfg eliza_intf[] = {
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x34000, .len = 0x4bc,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x35000, .len = 0x4bc,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_0,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_2", .id = INTF_2,
|
||||
.base = 0x36000, .len = 0x4bc,
|
||||
.type = INTF_DSI,
|
||||
.controller_id = MSM_DSI_CONTROLLER_1,
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
|
||||
.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
|
||||
}, {
|
||||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x37000, .len = 0x4bc,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
}
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg eliza_perf_data = {
|
||||
.max_bw_low = 6800000,
|
||||
.max_bw_high = 14200000,
|
||||
.min_core_ib = 2500000,
|
||||
.min_llcc_ib = 0,
|
||||
.min_dram_ib = 1600000,
|
||||
.min_prefill_lines = 35,
|
||||
.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
|
||||
.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
|
||||
.qos_lut_tbl = {
|
||||
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
|
||||
.entries = sc7180_qos_linear
|
||||
},
|
||||
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
|
||||
.entries = sc7180_qos_macrotile
|
||||
},
|
||||
{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
|
||||
.entries = sc7180_qos_nrt
|
||||
},
|
||||
/* TODO: macrotile-qseed is different from macrotile */
|
||||
},
|
||||
.cdp_cfg = {
|
||||
{.rd_enable = 1, .wr_enable = 1},
|
||||
{.rd_enable = 1, .wr_enable = 0}
|
||||
},
|
||||
.clk_inefficiency_factor = 105,
|
||||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_version eliza_mdss_ver = {
|
||||
.core_major_ver = 12,
|
||||
.core_minor_ver = 4,
|
||||
};
|
||||
|
||||
const struct dpu_mdss_cfg dpu_eliza_cfg = {
|
||||
.mdss_ver = &eliza_mdss_ver,
|
||||
.caps = &eliza_dpu_caps,
|
||||
.mdp = &eliza_mdp,
|
||||
.cdm = &dpu_cdm_5_x,
|
||||
.ctl_count = ARRAY_SIZE(eliza_ctl),
|
||||
.ctl = eliza_ctl,
|
||||
.sspp_count = ARRAY_SIZE(eliza_sspp),
|
||||
.sspp = eliza_sspp,
|
||||
.mixer_count = ARRAY_SIZE(eliza_lm),
|
||||
.mixer = eliza_lm,
|
||||
.dspp_count = ARRAY_SIZE(eliza_dspp),
|
||||
.dspp = eliza_dspp,
|
||||
.pingpong_count = ARRAY_SIZE(eliza_pp),
|
||||
.pingpong = eliza_pp,
|
||||
.dsc_count = ARRAY_SIZE(eliza_dsc),
|
||||
.dsc = eliza_dsc,
|
||||
.merge_3d_count = ARRAY_SIZE(eliza_merge_3d),
|
||||
.merge_3d = eliza_merge_3d,
|
||||
.wb_count = ARRAY_SIZE(eliza_wb),
|
||||
.wb = eliza_wb,
|
||||
.cwb_count = ARRAY_SIZE(eliza_cwb),
|
||||
.cwb = eliza_cwb,
|
||||
.intf_count = ARRAY_SIZE(eliza_intf),
|
||||
.intf = eliza_intf,
|
||||
.vbif = &sm8650_vbif,
|
||||
.perf = &eliza_perf_data,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -362,7 +362,6 @@ static const struct dpu_wb_cfg kaanapali_wb[] = {
|
|||
.format_list = wb2_formats_rgb_yuv,
|
||||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -418,7 +417,7 @@ static const struct dpu_intf_cfg kaanapali_intf[] = {
|
|||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x190000, .len = 0x4bc,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
|
|
@ -484,8 +483,7 @@ const struct dpu_mdss_cfg dpu_kaanapali_cfg = {
|
|||
.cwb = sm8650_cwb,
|
||||
.intf_count = ARRAY_SIZE(kaanapali_intf),
|
||||
.intf = kaanapali_intf,
|
||||
.vbif_count = ARRAY_SIZE(sm8650_vbif),
|
||||
.vbif = sm8650_vbif,
|
||||
.vbif = &sm8650_vbif,
|
||||
.perf = &kaanapali_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -197,8 +197,7 @@ const struct dpu_mdss_cfg dpu_msm8937_cfg = {
|
|||
.pingpong = msm8937_pp,
|
||||
.intf_count = ARRAY_SIZE(msm8937_intf),
|
||||
.intf = msm8937_intf,
|
||||
.vbif_count = ARRAY_SIZE(msm8996_vbif),
|
||||
.vbif = msm8996_vbif,
|
||||
.vbif = &msm8996_vbif,
|
||||
.perf = &msm8937_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -176,8 +176,7 @@ const struct dpu_mdss_cfg dpu_msm8917_cfg = {
|
|||
.pingpong = msm8917_pp,
|
||||
.intf_count = ARRAY_SIZE(msm8917_intf),
|
||||
.intf = msm8917_intf,
|
||||
.vbif_count = ARRAY_SIZE(msm8996_vbif),
|
||||
.vbif = msm8996_vbif,
|
||||
.vbif = &msm8996_vbif,
|
||||
.perf = &msm8917_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -121,13 +121,6 @@ static const struct dpu_dspp_cfg msm8953_dspp[] = {
|
|||
|
||||
static const struct dpu_intf_cfg msm8953_intf[] = {
|
||||
{
|
||||
.name = "intf_0", .id = INTF_0,
|
||||
.base = 0x6a000, .len = 0x268,
|
||||
.type = INTF_NONE,
|
||||
.prog_fetch_lines_worst_case = 14,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
|
||||
}, {
|
||||
.name = "intf_1", .id = INTF_1,
|
||||
.base = 0x6a800, .len = 0x268,
|
||||
.type = INTF_DSI,
|
||||
|
|
@ -204,8 +197,7 @@ const struct dpu_mdss_cfg dpu_msm8953_cfg = {
|
|||
.pingpong = msm8953_pp,
|
||||
.intf_count = ARRAY_SIZE(msm8953_intf),
|
||||
.intf = msm8953_intf,
|
||||
.vbif_count = ARRAY_SIZE(msm8996_vbif),
|
||||
.vbif = msm8996_vbif,
|
||||
.vbif = &msm8996_vbif,
|
||||
.perf = &msm8953_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -320,8 +320,7 @@ const struct dpu_mdss_cfg dpu_msm8996_cfg = {
|
|||
.dsc = msm8996_dsc,
|
||||
.intf_count = ARRAY_SIZE(msm8996_intf),
|
||||
.intf = msm8996_intf,
|
||||
.vbif_count = ARRAY_SIZE(msm8996_vbif),
|
||||
.vbif = msm8996_vbif,
|
||||
.vbif = &msm8996_vbif,
|
||||
.perf = &msm8996_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -305,8 +305,7 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = {
|
|||
.dsc = msm8998_dsc,
|
||||
.intf_count = ARRAY_SIZE(msm8998_intf),
|
||||
.intf = msm8998_intf,
|
||||
.vbif_count = ARRAY_SIZE(msm8998_vbif),
|
||||
.vbif = msm8998_vbif,
|
||||
.vbif = &msm8998_vbif,
|
||||
.perf = &msm8998_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -269,8 +269,7 @@ const struct dpu_mdss_cfg dpu_sdm660_cfg = {
|
|||
.dsc = sdm660_dsc,
|
||||
.intf_count = ARRAY_SIZE(sdm660_intf),
|
||||
.intf = sdm660_intf,
|
||||
.vbif_count = ARRAY_SIZE(msm8998_vbif),
|
||||
.vbif = msm8998_vbif,
|
||||
.vbif = &msm8998_vbif,
|
||||
.perf = &sdm660_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -207,8 +207,7 @@ const struct dpu_mdss_cfg dpu_sdm630_cfg = {
|
|||
.pingpong = sdm630_pp,
|
||||
.intf_count = ARRAY_SIZE(sdm630_intf),
|
||||
.intf = sdm630_intf,
|
||||
.vbif_count = ARRAY_SIZE(msm8998_vbif),
|
||||
.vbif = msm8998_vbif,
|
||||
.vbif = &msm8998_vbif,
|
||||
.perf = &sdm630_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -258,7 +258,7 @@ static const struct dpu_intf_cfg sdm845_intf[] = {
|
|||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x6b800, .len = 0x280,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
|
|
@ -325,8 +325,7 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
|
|||
.dsc = sdm845_dsc,
|
||||
.intf_count = ARRAY_SIZE(sdm845_intf),
|
||||
.intf = sdm845_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &sdm845_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -144,8 +144,7 @@ const struct dpu_mdss_cfg dpu_sdm670_cfg = {
|
|||
.dsc = sdm670_dsc,
|
||||
.intf_count = ARRAY_SIZE(sdm845_intf),
|
||||
.intf = sdm845_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &sdm845_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -280,7 +280,6 @@ static const struct dpu_wb_cfg sm8150_wb[] = {
|
|||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.clk_ctrl = DPU_CLK_CTRL_WB2,
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -317,7 +316,7 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
|
|||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x6b800, .len = 0x280,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
|
|
@ -381,8 +380,7 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
|
|||
.wb = sm8150_wb,
|
||||
.intf_count = ARRAY_SIZE(sm8150_intf),
|
||||
.intf = sm8150_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &sm8150_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -286,7 +286,6 @@ static const struct dpu_wb_cfg sc8180x_wb[] = {
|
|||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.clk_ctrl = DPU_CLK_CTRL_WB2,
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -405,8 +404,7 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
|
|||
.wb = sc8180x_wb,
|
||||
.intf_count = ARRAY_SIZE(sc8180x_intf),
|
||||
.intf = sc8180x_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &sc8180x_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -230,7 +230,7 @@ static const struct dpu_intf_cfg sm7150_intf[] = {
|
|||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x6b800, .len = 0x280,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
|
|
@ -246,7 +246,6 @@ static const struct dpu_wb_cfg sm7150_wb[] = {
|
|||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.clk_ctrl = DPU_CLK_CTRL_WB2,
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -309,8 +308,7 @@ const struct dpu_mdss_cfg dpu_sm7150_cfg = {
|
|||
.intf = sm7150_intf,
|
||||
.wb_count = ARRAY_SIZE(sm7150_wb),
|
||||
.wb = sm7150_wb,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &sm7150_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -158,7 +158,6 @@ static const struct dpu_wb_cfg sm6150_wb[] = {
|
|||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.clk_ctrl = DPU_CLK_CTRL_WB2,
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 2160,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -186,7 +185,7 @@ static const struct dpu_intf_cfg sm6150_intf[] = {
|
|||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x6b800, .len = 0x280,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
|
|
@ -246,8 +245,7 @@ const struct dpu_mdss_cfg dpu_sm6150_cfg = {
|
|||
.wb = sm6150_wb,
|
||||
.intf_count = ARRAY_SIZE(sm6150_intf),
|
||||
.intf = sm6150_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &sm6150_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -137,7 +137,6 @@ static const struct dpu_wb_cfg sm6125_wb[] = {
|
|||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.clk_ctrl = DPU_CLK_CTRL_WB2,
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 2160,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -217,8 +216,7 @@ const struct dpu_mdss_cfg dpu_sm6125_cfg = {
|
|||
.wb = sm6125_wb,
|
||||
.intf_count = ARRAY_SIZE(sm6125_intf),
|
||||
.intf = sm6125_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &sm6125_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -301,7 +301,7 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
|
|||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x6b800, .len = 0x280,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
|
|
@ -317,7 +317,6 @@ static const struct dpu_wb_cfg sm8250_wb[] = {
|
|||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.clk_ctrl = DPU_CLK_CTRL_WB2,
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -378,8 +377,7 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = {
|
|||
.merge_3d = sm8250_merge_3d,
|
||||
.intf_count = ARRAY_SIZE(sm8250_intf),
|
||||
.intf = sm8250_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.wb_count = ARRAY_SIZE(sm8250_wb),
|
||||
.wb = sm8250_wb,
|
||||
.perf = &sm8250_perf_data,
|
||||
|
|
|
|||
|
|
@ -153,7 +153,6 @@ static const struct dpu_wb_cfg sc7180_wb[] = {
|
|||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.clk_ctrl = DPU_CLK_CTRL_WB2,
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -211,8 +210,7 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = {
|
|||
.intf = sc7180_intf,
|
||||
.wb_count = ARRAY_SIZE(sc7180_wb),
|
||||
.wb = sc7180_wb,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &sc7180_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -144,8 +144,7 @@ const struct dpu_mdss_cfg dpu_sm6115_cfg = {
|
|||
.pingpong = sm6115_pp,
|
||||
.intf_count = ARRAY_SIZE(sm6115_intf),
|
||||
.intf = sm6115_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &sm6115_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -147,7 +147,6 @@ static const struct dpu_wb_cfg sm6350_wb[] = {
|
|||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.clk_ctrl = DPU_CLK_CTRL_WB2,
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 1920,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -229,8 +228,7 @@ const struct dpu_mdss_cfg dpu_sm6350_cfg = {
|
|||
.wb = sm6350_wb,
|
||||
.intf_count = ARRAY_SIZE(sm6350_intf),
|
||||
.intf = sm6350_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &sm6350_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -137,8 +137,7 @@ const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
|
|||
.pingpong = qcm2290_pp,
|
||||
.intf_count = ARRAY_SIZE(qcm2290_intf),
|
||||
.intf = qcm2290_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &qcm2290_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -155,8 +155,7 @@ const struct dpu_mdss_cfg dpu_sm6375_cfg = {
|
|||
.pingpong = sm6375_pp,
|
||||
.intf_count = ARRAY_SIZE(sm6375_intf),
|
||||
.intf = sm6375_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &sm6375_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -290,7 +290,6 @@ static const struct dpu_wb_cfg sm8350_wb[] = {
|
|||
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
|
||||
.clk_ctrl = DPU_CLK_CTRL_WB2,
|
||||
.xin_id = 6,
|
||||
.vbif_idx = VBIF_RT,
|
||||
.maxlinewidth = 4096,
|
||||
.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
|
||||
},
|
||||
|
|
@ -327,7 +326,7 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
|
|||
.name = "intf_3", .id = INTF_3,
|
||||
.base = 0x37000, .len = 0x280,
|
||||
.type = INTF_DP,
|
||||
.controller_id = MSM_DP_CONTROLLER_1,
|
||||
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
|
||||
.prog_fetch_lines_worst_case = 24,
|
||||
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
|
||||
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
|
||||
|
|
@ -392,8 +391,7 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
|
|||
.wb = sm8350_wb,
|
||||
.intf_count = ARRAY_SIZE(sm8350_intf),
|
||||
.intf = sm8350_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.vbif = &sdm845_vbif,
|
||||
.perf = &sm8350_perf_data,
|
||||
};
|
||||
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user