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drm/xe/gsc: add HECI2 register offsets

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Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Vitaly Lubart 2023-08-28 13:07:07 +03:00 committed by Rodrigo Vivi
parent cd0adf7465
commit 5120243bfb
1 changed files with 4 additions and 0 deletions
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4
drivers/gpu/drm/xe/regs/xe_regs.h
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@ -33,6 +33,10 @@
#define XEHPC_BCS6_RING_BASE 0x3ea000
#define XEHPC_BCS7_RING_BASE 0x3ec000
#define XEHPC_BCS8_RING_BASE 0x3ee000
#define DG1_GSC_HECI2_BASE 0x00259000
#define DG2_GSC_HECI2_BASE 0x00374000
#define GSCCS_RING_BASE 0x11a000
#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
#define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8)