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i.MX arm64 device tree change for 6.14:

Browse Source 
- Add simple-framebuffer support for imx8mn-bsh-smm-s2/pro board
   (Dario Binacchi)
 - Add LVDS compatible string for imx8mm-phg board (Fabio Estevam)
 - Add P3T1085 temperature sensor support for imx93-9x9-qsb board (Frank Li)
 - Add support for i.MX8MP based aristainetos3 boards from ABB
   (Heiko Schocher)
 - Add PCA9452 system PMIC support for imx93-14x14-evk board (Joy Zou)
 - Support NXP LVDS to HDMI adapter cards for imx8mp-evk board with DT
   overlays (Liu Ying)
 - A couple of changes from Markus Niebel to enable Open Drain for MDIO
   on imx93-tqma9352 boards
 - A series from Peng Fan to enable wdog3 fsl,ext-reset-output support
   for NXP i.MX93 boards
 - A couple changes from Wei Fang to add NETC support for i.MX95
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Merge tag 'imx-dt64-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX arm64 device tree change for 6.14:

- Add simple-framebuffer support for imx8mn-bsh-smm-s2/pro board
  (Dario Binacchi)
- Add LVDS compatible string for imx8mm-phg board (Fabio Estevam)
- Add P3T1085 temperature sensor support for imx93-9x9-qsb board (Frank Li)
- Add support for i.MX8MP based aristainetos3 boards from ABB
  (Heiko Schocher)
- Add PCA9452 system PMIC support for imx93-14x14-evk board (Joy Zou)
- Support NXP LVDS to HDMI adapter cards for imx8mp-evk board with DT
  overlays (Liu Ying)
- A couple of changes from Markus Niebel to enable Open Drain for MDIO
  on imx93-tqma9352 boards
- A series from Peng Fan to enable wdog3 fsl,ext-reset-output support
  for NXP i.MX93 boards
- A couple changes from Wei Fang to add NETC support for i.MX95

* tag 'imx-dt64-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: freescale: imx93-9x9-qsb: enable fsl,ext-reset-output for wdog3
  arm64: dts: freescale: imx93-14x14-evk: enable fsl,ext-reset-output for wdog3
  arm64: dts: freescale: imx93-11x11-evk: enable fsl,ext-reset-output for wdog3
  arm64: dts: imx95-19x19-evk: add ENETC 0 support
  arm64: dts: imx95: add NETC related nodes
  arm64: dts: imx8mm-phg: Add LVDS compatible string
  arm64: dts: imx93: add pca9452 support
  arm64: dts: imx8mn-bsh-smm-s2/pro: add simple-framebuffer
  arm64: dts: imx93-tqma9352-mba93xxla: enable Open Drain for MDIO
  arm64: dts: imx93-tqma9352-mba93xxca: enable Open Drain for MDIO
  arm64: dts: imx93-9x9-qsb: add temp-sensor nxp,p3t1085
  arm64: dts: imx8mp-evk: Add NXP LVDS to HDMI adapter cards
  arm64: dts: imx8mp-skov-revb-mi1010ait-1cp1: Set "media_disp2_pix" clock rate to 70MHz
  arm64: dts: imx8mp: add aristainetos3 board support
  arm64: dts: imx8mq-zii-ultra: remove #address-cells of eeprom@a4
  arm64: dts: imx: Switch to simple-audio-card,hp-det-gpios

Link: https://lore.kernel.org/r/20250105095139.714590-4-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-01-16 14:41:30 +01:00
commit 50e859f99d
27 changed files with 2096 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
arch/arm64/boot/dts/freescale/Makefile
View File

@ -165,6 +165,11 @@ imx8mn-tqma8mqnl-mba8mx-usbotg-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8m
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-usbotg.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-adpismarc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios.dtb
imx8mp-aristainetos3-helios-lvds-dtbs += imx8mp-aristainetos3-helios.dtb imx8mp-aristainetos3-helios-lvds.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios-lvds.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
@ -211,8 +216,16 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb
imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtbo
imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-lvds-hdmi.dtbo
imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtbo
imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-lvds-hdmi.dtbo
imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo
imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx8mp-evk-pcie-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-lvds-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-lvds-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-mx8-dlvds-lcd1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie-ep.dtb

2
arch/arm64/boot/dts/freescale/imx8mm-phg.dts
View File

@ -82,7 +82,7 @@ reg_usdhc2_vmmc: regulator-vmmc {
};
panel {
compatible = "panel-lvds";
compatible = "auo,g084sn05", "panel-lvds";
width-mm = <170>;
height-mm = <28>;
data-mapping = "jeida-18";

28
arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi
View File

@ -4,6 +4,34 @@
*/
/ {
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
framebuffer-panel0 {
compatible = "simple-framebuffer";
clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, /* lcdif */
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>,
<&clk IMX8MN_VIDEO_PLL1>,
<&clk IMX8MN_CLK_DISP_AXI_ROOT>, /* pgc_dispmix */
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
<&clk IMX8MN_CLK_DISP_AXI>,
<&clk IMX8MN_CLK_DISP_APB>,
<&clk IMX8MN_SYS_PLL2_1000M>,
<&clk IMX8MN_SYS_PLL1_800M>,
<&clk IMX8MN_CLK_DSI_CORE>, /* mipi_disi */
<&clk IMX8MN_CLK_DSI_PHY_REF>;
power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>,
<&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
dvdd-supply = <&reg_3v3_dvdd>;
avdd-supply = <&reg_v3v3_avdd>;
status = "disabled";
};
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 700000 0>; /* 700000 ns = 1337Hz */

37
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-adpismarc.dts Normal file
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@ -0,0 +1,37 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2024 Heiko Schocher <hs@denx.de>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx8mp-aristainetos3a-som-v1.dtsi"
&{/} {
model = "Aristainetos3 ADLink PI SMARC carrier";
compatible = "abb,imx8mp-aristanetos3-adpismarc",
"abb,imx8mp-aristanetos3-som",
"fsl,imx8mp";
};
&flexcan1 {
status = "okay";
};
&i2c2 {
gpio8: pinctrl@3e {
compatible = "semtech,sx1509q";
reg = <0x3e>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
semtech,probe-reset;
gpio-controller;
interrupt-controller;
interrupt-parent = <&gpio6>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
};
};

113
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios-lvds.dtso Normal file
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@ -0,0 +1,113 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2024 Heiko Schocher <hs@denx.de>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pwm/pwm.h>
/dts-v1/;
/plugin/;
&{/} {
model = "Aristainetos3 helios carrier with LVDS";
compatible = "abb,imx8mp-aristanetos3-helios",
"abb,imx8mp-aristanetos3-som",
"fsl,imx8mp";
panel_lvds: panel-lvds {
compatible = "lg,lb070wv8";
power-supply = <&reg_vcc_disp>;
backlight = <&lvds_backlight>;
port {
in_lvds0: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
reg_vcc_disp: regulator-disp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd0_vcc_en>;
compatible = "regulator-fixed";
regulator-name = "disp_power_en_2v8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
};
};
&gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio3_hog>;
lvdssel-hog {
gpio-hog;
gpios = <23 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "LVDSSEL";
};
};
&hdmi_blk_ctrl {
status = "disabled";
};
&hdmi_pvi {
status = "disabled";
};
&hdmi_tx {
status = "disabled";
};
&hdmi_tx_phy {
status = "disabled";
};
&irqsteer_hdmi {
status = "disabled";
};
&ldb_lvds_ch0 {
remote-endpoint = <&in_lvds0>;
};
&lcdif1 {
status = "disabled";
};
&lcdif2 {
status = "okay";
};
&lcdif3 {
status = "disabled";
};
&lvds_backlight {
status = "okay";
};
&lvds_bridge {
/* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */
assigned-clock-rates = <232820000>;
status = "okay";
};
&media_blk_ctrl {
/*
* currently it is not possible to let display clocks configure
* automatically, so we need to set them manually
*/
assigned-clock-rates = <500000000>, <200000000>, <0>,
/* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */
<33260000>, <0>,
/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */
<465640000>;
};

98
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-helios.dts Normal file
View File

@ -0,0 +1,98 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2024 Heiko Schocher <hs@denx.de>
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx8mp-aristainetos3a-som-v1.dtsi"
&{/} {
model = "Aristainetos3 helios carrier";
compatible = "abb,imx8mp-aristanetos3-helios",
"abb,imx8mp-aristanetos3-som",
"fsl,imx8mp";
led-controller {
compatible = "gpio-leds";
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
function-enumerator = <20>;
gpios = <&pca6416 12 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_YELLOW>;
function-enumerator = <20>;
gpios = <&pca6416 13 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-2 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
function-enumerator = <20>;
gpios = <&pca6416 14 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led-3 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
function-enumerator = <20>;
gpios = <&pca6416 15 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
};
&ethphy1 {
status = "disabled";
};
&fec {
status = "disabled";
};
&i2c1 {
eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
};
};
&i2c3 {
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "DIN0_CON",
"DIN1_CON",
"DIN2_CON",
"DIN3_CON",
"DIN4_CON",
"DIN5_CON",
"DIN6_CON",
"DIN7_CON",
"PM102_RES",
"COMx_RES",
"BPL_RES",
"PC_RES",
"LED_RED",
"LED_YELLOW",
"LED_GREEN",
"LED_BLUE";
};
rtc@68 {
compatible = "st,m41t00";
reg = <0x68>;
};
};

161
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts Normal file
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@ -0,0 +1,161 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2024 Heiko Schocher <hs@denx.de>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "imx8mp-aristainetos3a-som-v1.dtsi"
&{/} {
model = "Aristainetos3 proton2s carrier";
compatible = "abb,imx8mp-aristanetos3-proton2s",
"abb,imx8mp-aristanetos3-som",
"fsl,imx8mp";
watchdog {
/* MAX6371KA */
compatible = "linux,wdt-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_watchdog_gpio>;
always-running;
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
hw_algo = "level";
/* Reset triggers in 3..9 seconds */
hw_margin_ms = <1500>;
};
};
&ethphy1 {
status = "disabled";
};
&eqos {
max-speed = <100>;
};
&ecspi1{
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
};
&fec {
status = "disabled";
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_proton2s>;
gpio-line-names =
"", "", "", "", "", "", "", "POWER",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio6 {
gpio-line-names =
"RELAY0", "RELAY1", "RELAY2", "HEATER",
"FAN", "SPARE", "CLEAR", "FAULT",
"", "", "", "", "", "", "", "", "";
};
&i2c2 {
tlc59108@40 {
compatible = "ti,tlc59108";
reg = <0x40>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0x0>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
function-enumerator = <20>;
};
led@1 {
reg = <0x1>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
function-enumerator = <20>;
};
led@2 {
reg = <0x2>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
function-enumerator = <21>;
};
led@3 {
reg = <0x3>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
function-enumerator = <21>;
};
led@4 {
reg = <0x4>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
function-enumerator = <21>;
};
led@5 {
reg = <0x5>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
function-enumerator = <22>;
};
led@6 {
reg = <0x6>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
function-enumerator = <22>;
};
led@7 {
reg = <0x7>;
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
function-enumerator = <22>;
};
};
rtc1: rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
&uart1 {
pinctrl-0 = <&pinctrl_uart1>;
};
&uart2 {
pinctrl-0 = <&pinctrl_uart2>;
};
&uart3 {
pinctrl-0 = <&pinctrl_uart3>;
};
&uart4 {
linux,rs485-enabled-at-boot-time;
rs485-rts-active-low;
rs485-rts-delay = <0 0>;
rts-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
};
&usdhc1 {
status = "disabled";
};
&wdog1 {
status = "okay";
};

1107
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi Normal file
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29
arch/arm64/boot/dts/freescale/imx8mp-evk-imx-lvds-hdmi-common.dtsi Normal file
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@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
/dts-v1/;
/plugin/;
&{/} {
lvds-hdmi-connector {
compatible = "hdmi-connector";
label = "J2";
type = "a";
port {
lvds2hdmi_connector_in: endpoint {
remote-endpoint = <&it6263_out>;
};
};
};
};
&lcdif2 {
status = "okay";
};
&lvds_bridge {
status = "okay";
};

44
arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtso Normal file
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@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"
&it6263 {
ports {
port@0 {
reg = <0>;
dual-lvds-odd-pixels;
it6263_lvds_link1: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
port@1 {
reg = <1>;
dual-lvds-even-pixels;
it6263_lvds_link2: endpoint {
remote-endpoint = <&ldb_lvds_ch1>;
};
};
};
};
&lvds_bridge {
ports {
port@1 {
ldb_lvds_ch0: endpoint {
remote-endpoint = <&it6263_lvds_link1>;
};
};
port@2 {
ldb_lvds_ch1: endpoint {
remote-endpoint = <&it6263_lvds_link2>;
};
};
};
};

43
arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi Normal file
View File

@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
#include <dt-bindings/gpio/gpio.h>
#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi"
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
it6263: hdmi@4c {
compatible = "ite,it6263";
reg = <0x4c>;
data-mapping = "jeida-24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds_en>;
reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
ivdd-supply = <&reg_buck5>;
ovdd-supply = <&reg_vext_3v3>;
txavcc18-supply = <&reg_buck5>;
txavcc33-supply = <&reg_vext_3v3>;
pvcc1-supply = <&reg_buck5>;
pvcc2-supply = <&reg_buck5>;
avcc-supply = <&reg_vext_3v3>;
anvdd-supply = <&reg_buck5>;
apvdd-supply = <&reg_buck5>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
reg = <2>;
it6263_out: endpoint {
remote-endpoint = <&lvds2hdmi_connector_in>;
};
};
};
};
};

28
arch/arm64/boot/dts/freescale/imx8mp-evk-lvds0-imx-lvds-hdmi.dtso Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"
&it6263 {
ports {
port@0 {
reg = <0>;
it6263_lvds_link1: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
};
&lvds_bridge {
ports {
port@1 {
ldb_lvds_ch0: endpoint {
remote-endpoint = <&it6263_lvds_link1>;
};
};
};
};

44
arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtso Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"
&it6263 {
ports {
port@0 {
reg = <0>;
dual-lvds-even-pixels;
it6263_lvds_link1: endpoint {
remote-endpoint = <&ldb_lvds_ch1>;
};
};
port@1 {
reg = <1>;
dual-lvds-odd-pixels;
it6263_lvds_link2: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
};
&lvds_bridge {
ports {
port@1 {
ldb_lvds_ch0: endpoint {
remote-endpoint = <&it6263_lvds_link2>;
};
};
port@2 {
ldb_lvds_ch1: endpoint {
remote-endpoint = <&it6263_lvds_link1>;
};
};
};
};

43
arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi Normal file
View File

@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
#include <dt-bindings/gpio/gpio.h>
#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi"
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
it6263: hdmi@4c {
compatible = "ite,it6263";
reg = <0x4c>;
data-mapping = "jeida-24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds_en>;
reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
ivdd-supply = <&reg_buck5>;
ovdd-supply = <&reg_vext_3v3>;
txavcc18-supply = <&reg_buck5>;
txavcc33-supply = <&reg_vext_3v3>;
pvcc1-supply = <&reg_buck5>;
pvcc2-supply = <&reg_buck5>;
avcc-supply = <&reg_vext_3v3>;
anvdd-supply = <&reg_buck5>;
apvdd-supply = <&reg_buck5>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@2 {
reg = <2>;
it6263_out: endpoint {
remote-endpoint = <&lvds2hdmi_connector_in>;
};
};
};
};
};

28
arch/arm64/boot/dts/freescale/imx8mp-evk-lvds1-imx-lvds-hdmi.dtso Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"
&it6263 {
ports {
port@0 {
reg = <0>;
it6263_lvds_link1: endpoint {
remote-endpoint = <&ldb_lvds_ch1>;
};
};
};
};
&lvds_bridge {
ports {
port@2 {
ldb_lvds_ch1: endpoint {
remote-endpoint = <&it6263_lvds_link1>;
};
};
};
};

6
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -938,6 +938,12 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
>;
};
pinctrl_lvds_en: lvdsengrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */

8
arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
View File

@ -52,7 +52,7 @@ &lcdif2 {
&lvds_bridge {
/* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */
assigned-clock-rates = <482300000>;
assigned-clock-rates = <490000000>;
status = "okay";
ports {
@ -70,10 +70,10 @@ &media_blk_ctrl {
*/
assigned-clock-rates = <500000000>, <200000000>, <0>,
/* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */
<68900000>,
<70000000>,
<500000000>,
/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */
<964600000>;
/* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB */
<490000000>;
};
&pwm4 {

2
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
View File

@ -172,7 +172,7 @@ sound {
"Headphones", "HP_OUT",
"Builtin Speaker", "Speaker Amp OUTR",
"Speaker Amp INR", "LINE_OUT";
simple-audio-card,hp-det-gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
simple-audio-card,hp-det-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
simple-audio-card,cpu {
sound-dai = <&sai2>;

2
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
View File

@ -241,7 +241,7 @@ sound {
"Headset Mic", "MICBIAS",
"IN3R", "Headset Mic",
"DMICDAT", "Digital Mic";
simple-audio-card,hp-det-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
simple-audio-card,hp-det-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
simple-audio-card,cpu {
sound-dai = <&sai2>;

2
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
View File

@ -517,8 +517,6 @@ eeprom@a3 {
eeprom@a4 {
compatible = "zii,rave-sp-eeprom";
reg = <0xa4 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
zii,eeprom-name = "main-eeprom";
};
};

8
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
View File

@ -595,6 +595,9 @@ &usdhc2 {
};
&wdog3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
@ -932,4 +935,9 @@ MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
>;
};
};

92
arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts
View File

@ -219,6 +219,89 @@ pcal6524: gpio@22 {
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
pmic@25 {
compatible = "nxp,pca9452";
reg = <0x25>;
interrupt-parent = <&pcal6524>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <610000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <670000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <1060000>;
regulator-max-microvolt = <1140000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <1710000>;
regulator-max-microvolt = <1890000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <840000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&lpi2c3 {
@ -284,6 +367,9 @@ &usdhc2 {
};
&wdog3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
@ -465,4 +551,10 @@ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
>;
};
};

14
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
View File

@ -221,6 +221,11 @@ wm8962: audio-codec@1a {
>;
};
p3t1085: temperature-sensor@48 {
compatible = "nxp,p3t1085";
reg = <0x48>;
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
@ -454,6 +459,9 @@ &usdhc2 {
};
&wdog3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
@ -641,4 +649,10 @@ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
>;
};
};

8
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
View File

@ -627,8 +627,8 @@ pinctrl_eqos: eqosgrp {
fsl,pins = <
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
/* SION | HYS | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e
/* SION | HYS | ODE | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000191e
/* HYS | FSEL_0 | DSE no drive */
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000
@ -659,8 +659,8 @@ pinctrl_fec: fecgrp {
fsl,pins = <
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e
/* SION | HYS | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e
/* SION | HYS | ODE | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000191e
/* HYS | FSEL_0 | DSE no drive */
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000

8
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
View File

@ -597,8 +597,8 @@ pinctrl_eqos: eqosgrp {
fsl,pins = <
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
/* SION | HYS | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e
/* SION | HYS | ODE | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000191e
/* HYS | FSEL_0 | DSE no drive */
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000
@ -629,8 +629,8 @@ pinctrl_fec: fecgrp {
fsl,pins = <
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e
/* SION | HYS | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e
/* SION | HYS | ODE | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000191e
/* HYS | FSEL_0 | DSE no drive */
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000

52
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
View File

@ -22,6 +22,7 @@ / {
compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
aliases {
ethernet0 = &enetc_port0;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
@ -193,6 +194,14 @@ sound-wm8962 {
};
};
&enetc_port0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc0>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
status = "okay";
};
&flexspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi1>;
@ -338,6 +347,25 @@ &mu7 {
status = "okay";
};
&netcmix_blk_ctrl {
status = "okay";
};
&netc_blk_ctrl {
status = "okay";
};
&netc_emdio {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emdio>;
status = "okay";
ethphy0: ethernet-phy@1 {
reg = <1>;
realtek,clkout-disable;
};
};
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
@ -429,6 +457,30 @@ &wdog3 {
};
&scmi_iomuxc {
pinctrl_emdio: emdiogrp{
fsl,pins = <
IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e
IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e
>;
};
pinctrl_enetc0: enetc0grp {
fsl,pins = <
IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e
IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e
IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e
IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e
IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e
IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e
IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e
IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e
IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e
IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e
IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e
IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e
>;
};
pinctrl_flexspi1: flexspi1grp {
fsl,pins = <
IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe

93
arch/arm64/boot/dts/freescale/imx95.dtsi
View File

@ -1697,6 +1697,99 @@ sai2: sai@4c880000 {
status = "disabled";
};
netc_blk_ctrl: system-controller@4cde0000 {
compatible = "nxp,imx95-netc-blk-ctrl";
reg = <0x0 0x4cde0000 0x0 0x10000>,
<0x0 0x4cdf0000 0x0 0x10000>,
<0x0 0x4c81000c 0x0 0x18>;
reg-names = "ierb", "prb", "netcmix";
#address-cells = <2>;
#size-cells = <2>;
ranges;
power-domains = <&scmi_devpd IMX95_PD_NETC>;
assigned-clocks = <&scmi_clk IMX95_CLK_ENET>,
<&scmi_clk IMX95_CLK_ENETREF>;
assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>,
<&scmi_clk IMX95_CLK_SYSPLL1_PFD0>;
assigned-clock-rates = <666666666>, <250000000>;
clocks = <&scmi_clk IMX95_CLK_ENET>;
clock-names = "ipg";
status = "disabled";
netc_bus0: pcie@4ca00000 {
compatible = "pci-host-ecam-generic";
reg = <0x0 0x4ca00000 0x0 0x100000>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0x0>;
msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF
<0x10 &its 0x61 0x1>, //ENETC0 VF0
<0x20 &its 0x62 0x1>, //ENETC0 VF1
<0x40 &its 0x63 0x1>, //ENETC1 PF
<0x80 &its 0x64 0x1>, //ENETC2 PF
<0x90 &its 0x65 0x1>, //ENETC2 VF0
<0xa0 &its 0x66 0x1>, //ENETC2 VF1
<0xc0 &its 0x67 0x1>; //NETC Timer
/* ENETC0~2 and Timer BAR0 - non-prefetchable memory */
ranges = <0x82000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0xe0000
/* Timer BAR2 - prefetchable memory */
0xc2000000 0x0 0x4cd00000 0x0 0x4cd00000 0x0 0x10000
/* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */
0x82000000 0x0 0x4cd20000 0x0 0x4cd20000 0x0 0x60000
/* ENETC0~2: VF0-1 BAR2 - prefetchable memory */
0xc2000000 0x0 0x4cd80000 0x0 0x4cd80000 0x0 0x60000>;
enetc_port0: ethernet@0,0 {
compatible = "pci1131,e101";
reg = <0x000000 0 0 0 0>;
clocks = <&scmi_clk IMX95_CLK_ENETREF>;
clock-names = "ref";
status = "disabled";
};
enetc_port1: ethernet@8,0 {
compatible = "pci1131,e101";
reg = <0x004000 0 0 0 0>;
clocks = <&scmi_clk IMX95_CLK_ENETREF>;
clock-names = "ref";
status = "disabled";
};
enetc_port2: ethernet@10,0 {
compatible = "pci1131,e101";
reg = <0x008000 0 0 0 0>;
status = "disabled";
};
netc_timer: ethernet@18,0 {
reg = <0x00c000 0 0 0 0>;
status = "disabled";
};
};
netc_bus1: pcie@4cb00000 {
compatible = "pci-host-ecam-generic";
reg = <0x0 0x4cb00000 0x0 0x100000>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x1 0x1>;
/* EMDIO BAR0 - non-prefetchable memory */
ranges = <0x82000000 0x0 0x4cce0000 0x0 0x4cce0000 0x0 0x20000
/* EMDIO BAR2 - prefetchable memory */
0xc2000000 0x0 0x4cd10000 0x0 0x4cd10000 0x0 0x10000>;
netc_emdio: mdio@0,0 {
compatible = "pci1131,ee00";
reg = <0x010000 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};
ddr-pmu@4e090dc0 {
compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";
reg = <0x0 0x4e090dc0 0x0 0x200>;