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arm64: dts: qcom: sm8750: Add UART15

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Add uart15 node for the UART bus present on the sm8750 SoC.

Signed-off-by: Teguh Sobirin <teguh@sobir.in>
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260605-sm8750-uart15-v1-1-93e660722e61@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Teguh Sobirin 2026-06-05 17:49:39 -05:00 committed by Bjorn Andersson
parent 4614628bea
commit 50c0854e27
1 changed files with 30 additions and 0 deletions
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30
arch/arm64/boot/dts/qcom/sm8750.dtsi
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@ -1218,6 +1218,28 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
status = "disabled";
};
uart15: serial@89c000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x0089c000 0x0 0x4000>;
interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config";
pinctrl-0 = <&qup_uart15_default>;
pinctrl-names = "default";
status = "disabled";
};
};
i2c_master_hub_0: geniqup@9c0000 {
@ -4060,6 +4082,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state {
bias-pull-down;
};
qup_uart15_default: qup-uart15-default-state {
/* TX, RX */
pins = "gpio30", "gpio31";
function = "qup2_se7";
drive-strength = <2>;
bias-pull-up;
};
sdc2_sleep: sdc2-sleep-state {
clk-pins {
pins = "sdc2_clk";