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media: i2c: ov01a10: Convert to new CCI register access helpers
Use the new comon CCI register access helpers to replace the private register access helpers in the ov01a10 driver. Signed-off-by: Hans de Goede <hansg@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
This commit is contained in:
Hans de Goede
Hans Verkuil
parent
ea444f30f6
commit
50b52b6d42
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@ -383,6 +383,7 @@ config VIDEO_OS05B10
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config VIDEO_OV01A10
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tristate "OmniVision OV01A10 sensor support"
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select V4L2_CCI_I2C
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help
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This is a Video4Linux2 sensor driver for the OmniVision
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OV01A10 camera.
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@ -10,7 +10,9 @@
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <media/v4l2-cci.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-fwnode.h>
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@ -19,10 +21,10 @@
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#define OV01A10_SCLK 80000000LL
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#define OV01A10_DATA_LANES 1
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#define OV01A10_REG_CHIP_ID 0x300a
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#define OV01A10_REG_CHIP_ID CCI_REG24(0x300a)
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#define OV01A10_CHIP_ID 0x560141
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#define OV01A10_REG_MODE_SELECT 0x0100
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#define OV01A10_REG_MODE_SELECT CCI_REG8(0x0100)
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#define OV01A10_MODE_STANDBY 0x00
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#define OV01A10_MODE_STREAMING 0x01
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@ -33,47 +35,47 @@
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#define OV01A10_ACITVE_HEIGHT 800
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/* vertical and horizontal timings */
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#define OV01A10_REG_VTS 0x380e
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#define OV01A10_REG_VTS CCI_REG16(0x380e)
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#define OV01A10_VTS_DEF 0x0700
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#define OV01A10_VTS_MIN 0x0380
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#define OV01A10_VTS_MAX 0xffff
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#define OV01A10_HTS_DEF 1488
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/* exposure controls */
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#define OV01A10_REG_EXPOSURE 0x3501
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#define OV01A10_REG_EXPOSURE CCI_REG16(0x3501)
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#define OV01A10_EXPOSURE_MIN 4
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#define OV01A10_EXPOSURE_MAX_MARGIN 8
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#define OV01A10_EXPOSURE_STEP 1
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/* analog gain controls */
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#define OV01A10_REG_ANALOG_GAIN 0x3508
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#define OV01A10_REG_ANALOG_GAIN CCI_REG16(0x3508)
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#define OV01A10_ANAL_GAIN_MIN 0x100
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#define OV01A10_ANAL_GAIN_MAX 0x3fff
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#define OV01A10_ANAL_GAIN_STEP 1
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/* digital gain controls */
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#define OV01A10_REG_DIGITAL_GAIN_B 0x350a
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#define OV01A10_REG_DIGITAL_GAIN_GB 0x3510
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#define OV01A10_REG_DIGITAL_GAIN_GR 0x3513
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#define OV01A10_REG_DIGITAL_GAIN_R 0x3516
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#define OV01A10_REG_DIGITAL_GAIN_B CCI_REG24(0x350a)
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#define OV01A10_REG_DIGITAL_GAIN_GB CCI_REG24(0x3510)
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#define OV01A10_REG_DIGITAL_GAIN_GR CCI_REG24(0x3513)
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#define OV01A10_REG_DIGITAL_GAIN_R CCI_REG24(0x3516)
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#define OV01A10_DGTL_GAIN_MIN 0
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#define OV01A10_DGTL_GAIN_MAX 0x3ffff
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#define OV01A10_DGTL_GAIN_STEP 1
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#define OV01A10_DGTL_GAIN_DEFAULT 1024
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/* test pattern control */
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#define OV01A10_REG_TEST_PATTERN 0x4503
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#define OV01A10_REG_TEST_PATTERN CCI_REG8(0x4503)
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#define OV01A10_TEST_PATTERN_ENABLE BIT(7)
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#define OV01A10_LINK_FREQ_400MHZ_INDEX 0
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/* flip and mirror control */
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#define OV01A10_REG_FORMAT1 0x3820
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#define OV01A10_REG_FORMAT1 CCI_REG8(0x3820)
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#define OV01A10_VFLIP_MASK BIT(4)
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#define OV01A10_HFLIP_MASK BIT(3)
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/* window offset */
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#define OV01A10_REG_X_WIN 0x3811
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#define OV01A10_REG_Y_WIN 0x3813
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#define OV01A10_REG_X_WIN CCI_REG16(0x3810)
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#define OV01A10_REG_Y_WIN CCI_REG16(0x3812)
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/*
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* The native ov01a10 bayer-pattern is GBRG, but there was a driver bug enabling
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@ -84,14 +86,9 @@
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*/
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#define OV01A10_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
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struct ov01a10_reg {
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u16 address;
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u8 val;
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};
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struct ov01a10_reg_list {
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u32 num_of_regs;
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const struct ov01a10_reg *regs;
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const struct reg_sequence *regs;
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};
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struct ov01a10_link_freq_config {
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@ -109,7 +106,7 @@ struct ov01a10_mode {
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const struct ov01a10_reg_list reg_list;
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};
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static const struct ov01a10_reg mipi_data_rate_720mbps[] = {
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static const struct reg_sequence mipi_data_rate_720mbps[] = {
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{0x0103, 0x01},
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{0x0302, 0x00},
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{0x0303, 0x06},
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@ -125,7 +122,7 @@ static const struct ov01a10_reg mipi_data_rate_720mbps[] = {
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{0x0325, 0x68},
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};
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static const struct ov01a10_reg sensor_1280x800_setting[] = {
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static const struct reg_sequence sensor_1280x800_setting[] = {
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{0x3002, 0xa1},
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{0x301e, 0xf0},
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{0x3022, 0x01},
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@ -282,6 +279,7 @@ static const struct ov01a10_mode supported_modes[] = {
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};
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struct ov01a10 {
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struct regmap *regmap;
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struct v4l2_subdev sd;
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struct media_pad pad;
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struct v4l2_ctrl_handler ctrl_handler;
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@ -301,104 +299,15 @@ static inline struct ov01a10 *to_ov01a10(struct v4l2_subdev *subdev)
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return container_of(subdev, struct ov01a10, sd);
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}
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static int ov01a10_read_reg(struct ov01a10 *ov01a10, u16 reg, u16 len, u32 *val)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
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struct i2c_msg msgs[2];
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u8 addr_buf[2];
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u8 data_buf[4] = {0};
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int ret = 0;
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if (len > sizeof(data_buf))
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return -EINVAL;
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put_unaligned_be16(reg, addr_buf);
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msgs[0].addr = client->addr;
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msgs[0].flags = 0;
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msgs[0].len = sizeof(addr_buf);
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msgs[0].buf = addr_buf;
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msgs[1].addr = client->addr;
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msgs[1].flags = I2C_M_RD;
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msgs[1].len = len;
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msgs[1].buf = &data_buf[sizeof(data_buf) - len];
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ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
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if (ret != ARRAY_SIZE(msgs))
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return ret < 0 ? ret : -EIO;
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*val = get_unaligned_be32(data_buf);
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return 0;
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}
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static int ov01a10_write_reg(struct ov01a10 *ov01a10, u16 reg, u16 len, u32 val)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
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u8 buf[6];
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int ret = 0;
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if (len > 4)
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return -EINVAL;
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put_unaligned_be16(reg, buf);
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put_unaligned_be32(val << 8 * (4 - len), buf + 2);
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ret = i2c_master_send(client, buf, len + 2);
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if (ret != len + 2)
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return ret < 0 ? ret : -EIO;
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return 0;
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}
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static int ov01a10_write_reg_list(struct ov01a10 *ov01a10,
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const struct ov01a10_reg_list *r_list)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
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unsigned int i;
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int ret = 0;
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for (i = 0; i < r_list->num_of_regs; i++) {
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ret = ov01a10_write_reg(ov01a10, r_list->regs[i].address, 1,
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r_list->regs[i].val);
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if (ret) {
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dev_err_ratelimited(&client->dev,
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"write reg 0x%4.4x err = %d\n",
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r_list->regs[i].address, ret);
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return ret;
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}
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}
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return 0;
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}
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static int ov01a10_update_digital_gain(struct ov01a10 *ov01a10, u32 d_gain)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
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u32 real = d_gain << 6;
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int ret = 0;
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ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_B, 3, real);
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if (ret) {
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dev_err(&client->dev, "failed to set DIGITAL_GAIN_B\n");
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return ret;
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}
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ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_GB, 3, real);
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if (ret) {
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dev_err(&client->dev, "failed to set DIGITAL_GAIN_GB\n");
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return ret;
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}
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ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_GR, 3, real);
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if (ret) {
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dev_err(&client->dev, "failed to set DIGITAL_GAIN_GR\n");
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return ret;
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}
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ret = ov01a10_write_reg(ov01a10, OV01A10_REG_DIGITAL_GAIN_R, 3, real);
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if (ret)
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dev_err(&client->dev, "failed to set DIGITAL_GAIN_R\n");
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cci_write(ov01a10->regmap, OV01A10_REG_DIGITAL_GAIN_B, real, &ret);
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cci_write(ov01a10->regmap, OV01A10_REG_DIGITAL_GAIN_GB, real, &ret);
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cci_write(ov01a10->regmap, OV01A10_REG_DIGITAL_GAIN_GR, real, &ret);
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cci_write(ov01a10->regmap, OV01A10_REG_DIGITAL_GAIN_R, real, &ret);
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return ret;
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}
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@ -408,48 +317,39 @@ static int ov01a10_test_pattern(struct ov01a10 *ov01a10, u32 pattern)
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if (pattern)
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pattern |= OV01A10_TEST_PATTERN_ENABLE;
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return ov01a10_write_reg(ov01a10, OV01A10_REG_TEST_PATTERN, 1, pattern);
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return cci_write(ov01a10->regmap, OV01A10_REG_TEST_PATTERN, pattern,
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NULL);
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}
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/* for vflip and hflip, use 0x9 as window offset to keep the bayer */
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static int ov01a10_set_hflip(struct ov01a10 *ov01a10, u32 hflip)
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{
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int ret;
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u32 val, offset;
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int ret = 0;
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offset = hflip ? 0x8 : 0x9;
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ret = ov01a10_write_reg(ov01a10, OV01A10_REG_X_WIN, 1, offset);
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if (ret)
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return ret;
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val = hflip ? 0 : FIELD_PREP(OV01A10_HFLIP_MASK, 0x1);
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ret = ov01a10_read_reg(ov01a10, OV01A10_REG_FORMAT1, 1, &val);
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if (ret)
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return ret;
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cci_write(ov01a10->regmap, OV01A10_REG_X_WIN, offset, &ret);
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cci_update_bits(ov01a10->regmap, OV01A10_REG_FORMAT1,
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OV01A10_HFLIP_MASK, val, &ret);
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val = hflip ? val & ~OV01A10_HFLIP_MASK :
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val | FIELD_PREP(OV01A10_HFLIP_MASK, 0x1);
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return ov01a10_write_reg(ov01a10, OV01A10_REG_FORMAT1, 1, val);
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return ret;
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}
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static int ov01a10_set_vflip(struct ov01a10 *ov01a10, u32 vflip)
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{
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int ret;
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u32 val, offset;
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int ret = 0;
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offset = vflip ? 0x9 : 0x8;
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ret = ov01a10_write_reg(ov01a10, OV01A10_REG_Y_WIN, 1, offset);
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if (ret)
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return ret;
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val = vflip ? FIELD_PREP(OV01A10_VFLIP_MASK, 0x1) : 0;
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ret = ov01a10_read_reg(ov01a10, OV01A10_REG_FORMAT1, 1, &val);
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if (ret)
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return ret;
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cci_write(ov01a10->regmap, OV01A10_REG_Y_WIN, offset, &ret);
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cci_update_bits(ov01a10->regmap, OV01A10_REG_FORMAT1,
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OV01A10_VFLIP_MASK, val, &ret);
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val = vflip ? val | FIELD_PREP(OV01A10_VFLIP_MASK, 0x1) :
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val & ~OV01A10_VFLIP_MASK;
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return ov01a10_write_reg(ov01a10, OV01A10_REG_FORMAT1, 1, val);
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return ret;
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}
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static int ov01a10_set_ctrl(struct v4l2_ctrl *ctrl)
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@ -474,8 +374,8 @@ static int ov01a10_set_ctrl(struct v4l2_ctrl *ctrl)
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switch (ctrl->id) {
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case V4L2_CID_ANALOGUE_GAIN:
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ret = ov01a10_write_reg(ov01a10, OV01A10_REG_ANALOG_GAIN, 2,
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ctrl->val);
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ret = cci_write(ov01a10->regmap, OV01A10_REG_ANALOG_GAIN,
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ctrl->val, NULL);
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break;
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case V4L2_CID_DIGITAL_GAIN:
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@ -483,13 +383,13 @@ static int ov01a10_set_ctrl(struct v4l2_ctrl *ctrl)
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break;
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case V4L2_CID_EXPOSURE:
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ret = ov01a10_write_reg(ov01a10, OV01A10_REG_EXPOSURE, 2,
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ctrl->val);
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ret = cci_write(ov01a10->regmap, OV01A10_REG_EXPOSURE,
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ctrl->val, NULL);
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break;
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case V4L2_CID_VBLANK:
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ret = ov01a10_write_reg(ov01a10, OV01A10_REG_VTS, 2,
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ov01a10->cur_mode->height + ctrl->val);
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ret = cci_write(ov01a10->regmap, OV01A10_REG_VTS,
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ov01a10->cur_mode->height + ctrl->val, NULL);
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break;
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case V4L2_CID_TEST_PATTERN:
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@ -630,14 +530,16 @@ static int ov01a10_start_streaming(struct ov01a10 *ov01a10)
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link_freq_index = ov01a10->cur_mode->link_freq_index;
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reg_list = &link_freq_configs[link_freq_index].reg_list;
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ret = ov01a10_write_reg_list(ov01a10, reg_list);
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ret = regmap_multi_reg_write(ov01a10->regmap, reg_list->regs,
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reg_list->num_of_regs);
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if (ret) {
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dev_err(&client->dev, "failed to set plls\n");
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return ret;
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}
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reg_list = &ov01a10->cur_mode->reg_list;
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ret = ov01a10_write_reg_list(ov01a10, reg_list);
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ret = regmap_multi_reg_write(ov01a10->regmap, reg_list->regs,
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reg_list->num_of_regs);
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if (ret) {
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dev_err(&client->dev, "failed to set mode\n");
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return ret;
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@ -647,23 +549,14 @@ static int ov01a10_start_streaming(struct ov01a10 *ov01a10)
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if (ret)
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return ret;
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ret = ov01a10_write_reg(ov01a10, OV01A10_REG_MODE_SELECT, 1,
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OV01A10_MODE_STREAMING);
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if (ret)
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dev_err(&client->dev, "failed to start streaming\n");
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return ret;
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return cci_write(ov01a10->regmap, OV01A10_REG_MODE_SELECT,
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OV01A10_MODE_STREAMING, NULL);
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}
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static void ov01a10_stop_streaming(struct ov01a10 *ov01a10)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
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int ret = 0;
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ret = ov01a10_write_reg(ov01a10, OV01A10_REG_MODE_SELECT, 1,
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OV01A10_MODE_STANDBY);
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if (ret)
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dev_err(&client->dev, "failed to stop streaming\n");
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cci_write(ov01a10->regmap, OV01A10_REG_MODE_SELECT,
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OV01A10_MODE_STANDBY, NULL);
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}
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static int ov01a10_set_stream(struct v4l2_subdev *sd, int enable)
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@ -841,14 +734,14 @@ static int ov01a10_identify_module(struct ov01a10 *ov01a10)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&ov01a10->sd);
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int ret;
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u32 val;
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u64 val;
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|
||||
ret = ov01a10_read_reg(ov01a10, OV01A10_REG_CHIP_ID, 3, &val);
|
||||
ret = cci_read(ov01a10->regmap, OV01A10_REG_CHIP_ID, &val, NULL);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (val != OV01A10_CHIP_ID) {
|
||||
dev_err(&client->dev, "chip id mismatch: %x!=%x\n",
|
||||
dev_err(&client->dev, "chip id mismatch: %x!=%llx\n",
|
||||
OV01A10_CHIP_ID, val);
|
||||
return -EIO;
|
||||
}
|
||||
|
|
@ -879,6 +772,10 @@ static int ov01a10_probe(struct i2c_client *client)
|
|||
if (!ov01a10)
|
||||
return -ENOMEM;
|
||||
|
||||
ov01a10->regmap = devm_cci_regmap_init_i2c(client, 16);
|
||||
if (IS_ERR(ov01a10->regmap))
|
||||
return PTR_ERR(ov01a10->regmap);
|
||||
|
||||
v4l2_i2c_subdev_init(&ov01a10->sd, client, &ov01a10_subdev_ops);
|
||||
ov01a10->sd.internal_ops = &ov01a10_internal_ops;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user