drm/i915/cx0: Add a fuzzy check for DP/HDMI clock rates during programming

Since the clock rate is derived from the PLL divider values it can have
a +-1kHz difference wrt. the reference rates in the comparison

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-11-mika.kahola@intel.com
This commit is contained in:
Mika Kahola 2026-01-19 09:37:51 +00:00
parent 6af62d1231
commit 50ad932880
2 changed files with 16 additions and 11 deletions

View File

@ -3012,6 +3012,12 @@ static void intel_c20_pll_program(struct intel_display *display,
MB_WRITE_COMMITTED);
}
static bool is_mplla_clock_rate(int clock)
{
return intel_dpll_clock_matches(clock, 1000000) ||
intel_dpll_clock_matches(clock, 2000000);
}
static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
const struct intel_cx0pll_state *pll_state,
int port_clock,
@ -3037,7 +3043,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
/* TODO: HDMI FRL */
/* DP2.0 10G and 20G rates enable MPLLA*/
if (port_clock == 1000000 || port_clock == 2000000)
if (is_mplla_clock_rate(port_clock))
val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
else
val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;

View File

@ -56,6 +56,7 @@
#include "intel_display_types.h"
#include "intel_display_utils.h"
#include "intel_dp.h"
#include "intel_dpll.h"
#include "intel_gmbus.h"
#include "intel_hdcp.h"
#include "intel_hdcp_regs.h"
@ -70,16 +71,14 @@
bool intel_hdmi_is_frl(u32 clock)
{
switch (clock) {
case 300000: /* 3 Gbps */
case 600000: /* 6 Gbps */
case 800000: /* 8 Gbps */
case 1000000: /* 10 Gbps */
case 1200000: /* 12 Gbps */
return true;
default:
return false;
}
u32 rates[] = { 300000, 600000, 800000, 1000000, 1200000 };
int i;
for (i = 0; i < ARRAY_SIZE(rates); i++)
if (intel_dpll_clock_matches(clock, rates[i]))
return true;
return false;
}
static void