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dt-bindings: xilinx: Remove EDK/Ethernet references
The latest EDK version was 14.7 released in 2013 that's why remove description for it. Also remove generic description for Ethernet which doesn't bring any value. Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
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d) Xilinx IP cores
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The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
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in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
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of standard device types (network, serial, etc.) and miscellaneous
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devices (gpio, LCD, spi, etc). Also, since these devices are
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implemented within the fpga fabric every instance of the device can be
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synthesised with different options that change the behaviour.
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Each IP-core has a set of parameters which the FPGA designer can use to
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control how the core is synthesized. Historically, the EDK tool would
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extract the device parameters relevant to device drivers and copy them
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into an 'xparameters.h' in the form of #define symbols. This tells the
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device drivers how the IP cores are configured, but it requires the kernel
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to be recompiled every time the FPGA bitstream is resynthesized.
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The new approach is to export the parameters into the device tree and
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generate a new device tree each time the FPGA bitstream changes. The
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parameters which used to be exported as #defines will now become
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properties of the device node. In general, device nodes for IP-cores
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will take the following form:
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(name): (generic-name)@(base-address) {
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compatible = "xlnx,(ip-core-name)-(HW_VER)"
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[, (list of compatible devices), ...];
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reg = <(baseaddr) (size)>;
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interrupt-parent = <&interrupt-controller-phandle>;
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interrupts = < ... >;
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xlnx,(parameter1) = "(string-value)";
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xlnx,(parameter2) = <(int-value)>;
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};
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(generic-name): an open firmware-style name that describes the
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generic class of device. Preferably, this is one word, such
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as 'serial' or 'ethernet'.
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(ip-core-name): the name of the ip block (given after the BEGIN
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directive in system.mhs). Should be in lowercase
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and all underscores '_' converted to dashes '-'.
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(name): is derived from the "PARAMETER INSTANCE" value.
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(parameter#): C_* parameters from system.mhs. The C_ prefix is
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dropped from the parameter name, the name is converted
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to lowercase and all underscore '_' characters are
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converted to dashes '-'.
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(baseaddr): the baseaddr parameter value (often named C_BASEADDR).
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(HW_VER): from the HW_VER parameter.
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(size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
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Typically, the compatible list will include the exact IP core version
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followed by an older IP core version which implements the same
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interface or any other device with the same interface.
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'reg' and 'interrupts' are all optional properties.
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For example, the following block from system.mhs:
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BEGIN opb_uartlite
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PARAMETER INSTANCE = opb_uartlite_0
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BAUDRATE = 115200
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PARAMETER C_DATA_BITS = 8
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PARAMETER C_ODD_PARITY = 0
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PARAMETER C_USE_PARITY = 0
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PARAMETER C_CLK_FREQ = 50000000
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PARAMETER C_BASEADDR = 0xEC100000
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PARAMETER C_HIGHADDR = 0xEC10FFFF
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BUS_INTERFACE SOPB = opb_7
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PORT OPB_Clk = CLK_50MHz
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PORT Interrupt = opb_uartlite_0_Interrupt
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PORT RX = opb_uartlite_0_RX
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PORT TX = opb_uartlite_0_TX
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PORT OPB_Rst = sys_bus_reset_0
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END
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becomes the following device tree node:
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opb_uartlite_0: serial@ec100000 {
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device_type = "serial";
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compatible = "xlnx,opb-uartlite-1.00.b";
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reg = <ec100000 10000>;
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interrupt-parent = <&opb_intc_0>;
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interrupts = <1 0>; // got this from the opb_intc parameters
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current-speed = <d#115200>; // standard serial device prop
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clock-frequency = <d#50000000>; // standard serial device prop
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xlnx,data-bits = <8>;
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xlnx,odd-parity = <0>;
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xlnx,use-parity = <0>;
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};
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That covers the general approach to binding xilinx IP cores into the
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device tree. The following are bindings for specific devices:
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Bindings for specific devices:
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i) Xilinx ML300 Framebuffer
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@ -102,13 +13,6 @@
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Default is <d#1024 d#480>.
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- rotate-display (empty) : rotate display 180 degrees.
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iii) Xilinx EMAC and Xilinx TEMAC
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Xilinx Ethernet devices. In addition to general xilinx properties
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listed above, nodes for these devices should include a phy-handle
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property, and may include other common network device properties
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like local-mac-address.
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v) Xilinx hwicap
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Xilinx hwicap devices provide access to the configuration logic
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