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ASoC: rt5650: enhance spk protection function
This patch adjusts several default settings to ensure the speaker protection function can be enabled safely. Signed-off-by: Shuming Fan <shumingf@realtek.com> Link: https://patch.msgid.link/20260615091012.718168-1-shumingf@realtek.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -83,6 +83,8 @@ static const struct reg_sequence rt5650_init_list[] = {
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{RT5645_PWR_ANLG1, 0x02},
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{RT5645_IL_CMD3, 0x6728},
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{RT5645_PR_BASE + 0x3a, 0x0000},
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{RT5645_CLSD_OUT_CTRL1, 0x4059},
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{RT5645_GEN_CTRL3, 0x0200},
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};
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static const struct reg_default rt5645_reg[] = {
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@ -1855,13 +1857,9 @@ static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
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RT5645_PWR_CLS_D_L,
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RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
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RT5645_PWR_CLS_D_L);
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snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
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RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);
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break;
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case SND_SOC_DAPM_PRE_PMD:
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snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
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RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);
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snd_soc_component_write(component, RT5645_EQ_CTRL2, 0);
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snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
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RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
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@ -118,6 +118,7 @@
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#define RT5645_A_JD_CTRL1 0x94
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#define RT5645_VAD_CTRL4 0x9d
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#define RT5645_CLSD_OUT_CTRL 0xa0
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#define RT5645_CLSD_OUT_CTRL1 0xa1
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/* Function - Digital */
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#define RT5645_ADC_EQ_CTRL1 0xae
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#define RT5645_ADC_EQ_CTRL2 0xaf
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