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wifi: rtw89: add support for HW encryption in unicast management frames
Add hardware encryption support for unicast management frames for 8922AE and 8852CE. Other chips will continue to use software encryption for unicast management frames. Signed-off-by: Kuan-Chung Chen <damon.chen@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Link: https://patch.msgid.link/20240731070506.46100-5-pkshih@realtek.com
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@ -384,20 +384,24 @@ int rtw89_cam_sec_key_add(struct rtw89_dev *rtwdev,
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break;
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case WLAN_CIPHER_SUITE_CCMP:
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hw_key_type = RTW89_SEC_KEY_TYPE_CCMP128;
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key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
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if (!chip->hw_mgmt_tx_encrypt)
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key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
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break;
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case WLAN_CIPHER_SUITE_CCMP_256:
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hw_key_type = RTW89_SEC_KEY_TYPE_CCMP256;
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key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
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if (!chip->hw_mgmt_tx_encrypt)
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key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
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ext_key = true;
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break;
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case WLAN_CIPHER_SUITE_GCMP:
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hw_key_type = RTW89_SEC_KEY_TYPE_GCMP128;
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key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
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if (!chip->hw_mgmt_tx_encrypt)
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key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
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break;
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case WLAN_CIPHER_SUITE_GCMP_256:
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hw_key_type = RTW89_SEC_KEY_TYPE_GCMP256;
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key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
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if (!chip->hw_mgmt_tx_encrypt)
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key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
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ext_key = true;
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break;
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case WLAN_CIPHER_SUITE_AES_CMAC:
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@ -602,15 +602,28 @@ static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev,
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return rtwsta->mac_id;
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}
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static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
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struct rtw89_tx_desc_info *desc_info,
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struct sk_buff *skb)
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{
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struct ieee80211_hdr *hdr = (void *)skb->data;
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__le16 fc = hdr->frame_control;
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desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
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desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
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}
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static void
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rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
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struct rtw89_core_tx_request *tx_req)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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struct ieee80211_vif *vif = tx_req->vif;
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struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
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struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
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const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
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rtwvif->chanctx_idx);
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struct sk_buff *skb = tx_req->skb;
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u8 qsel, ch_dma;
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qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT;
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@ -629,6 +642,11 @@ rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
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desc_info->dis_data_fb = true;
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desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan);
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if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) {
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rtw89_core_tx_update_sec_key(rtwdev, tx_req);
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rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
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}
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rtw89_debug(rtwdev, RTW89_DBG_TXRX,
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"tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n",
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desc_info->data_rate, chan->channel, chan->band_type,
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@ -862,17 +880,6 @@ rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,
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return PACKET_MAX;
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}
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static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
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struct rtw89_tx_desc_info *desc_info,
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struct sk_buff *skb)
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{
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struct ieee80211_hdr *hdr = (void *)skb->data;
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__le16 fc = hdr->frame_control;
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desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
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desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
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}
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static void
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rtw89_core_tx_wake(struct rtw89_dev *rtwdev,
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struct rtw89_core_tx_request *tx_req)
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@ -4183,6 +4183,7 @@ struct rtw89_chip_info {
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bool ul_tb_waveform_ctrl;
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bool ul_tb_pwr_diff;
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bool hw_sec_hdr;
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bool hw_mgmt_tx_encrypt;
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u8 rf_path_num;
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u8 tx_nss;
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u8 rx_nss;
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@ -2032,11 +2032,16 @@ int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow)
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void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC;
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if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
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return;
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/* 8852C enable B_AX_UC_MGNT_DEC by default */
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if (chip->chip_id == RTL8852C)
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msk32 = B_AX_BMC_MGNT_DEC;
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if (enable)
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rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
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else
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@ -2261,6 +2266,8 @@ static int sec_eng_init_ax(struct rtw89_dev *rtwdev)
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/* init TX encryption */
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val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC);
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val |= (B_AX_MC_DEC | B_AX_BC_DEC);
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if (chip->chip_id == RTL8852C)
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val |= B_AX_UC_MGNT_DEC;
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if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B ||
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chip->chip_id == RTL8851B)
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val &= ~B_AX_TX_PARTIAL_MODE;
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@ -2473,6 +2473,7 @@ const struct rtw89_chip_info rtw8851b_chip_info = {
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.ul_tb_waveform_ctrl = true,
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.ul_tb_pwr_diff = false,
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.hw_sec_hdr = false,
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.hw_mgmt_tx_encrypt = false,
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.rf_path_num = 1,
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.tx_nss = 1,
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.rx_nss = 1,
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@ -2188,6 +2188,7 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
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.ul_tb_waveform_ctrl = false,
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.ul_tb_pwr_diff = false,
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.hw_sec_hdr = false,
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.hw_mgmt_tx_encrypt = false,
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.rf_path_num = 2,
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.tx_nss = 2,
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.rx_nss = 2,
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@ -828,6 +828,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = {
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.ul_tb_waveform_ctrl = true,
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.ul_tb_pwr_diff = false,
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.hw_sec_hdr = false,
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.hw_mgmt_tx_encrypt = false,
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.rf_path_num = 2,
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.tx_nss = 2,
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.rx_nss = 2,
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@ -761,6 +761,7 @@ const struct rtw89_chip_info rtw8852bt_chip_info = {
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.ul_tb_waveform_ctrl = true,
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.ul_tb_pwr_diff = false,
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.hw_sec_hdr = false,
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.hw_mgmt_tx_encrypt = false,
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.rf_path_num = 2,
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.tx_nss = 2,
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.rx_nss = 2,
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@ -2969,6 +2969,7 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
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.ul_tb_waveform_ctrl = false,
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.ul_tb_pwr_diff = true,
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.hw_sec_hdr = true,
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.hw_mgmt_tx_encrypt = true,
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.rf_path_num = 2,
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.tx_nss = 2,
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.rx_nss = 2,
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@ -2572,6 +2572,7 @@ const struct rtw89_chip_info rtw8922a_chip_info = {
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.ul_tb_waveform_ctrl = false,
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.ul_tb_pwr_diff = false,
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.hw_sec_hdr = true,
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.hw_mgmt_tx_encrypt = true,
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.rf_path_num = 2,
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.tx_nss = 2,
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.rx_nss = 2,
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