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arm64: dts: broadcom: bcm2712: Add PCIe DT nodes

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Add PCIe devicetree nodes, plus needed reset and mip MSI-X
controllers.

Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
Link: https://lore.kernel.org/r/20250120130119.671119-11-svarbanov@suse.de
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
This commit is contained in:
Stanimir Varbanov 2025-01-20 15:01:18 +02:00 committed by Florian Fainelli
parent 0af2f6be1b
commit 5050168029
1 changed files with 147 additions and 0 deletions
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147
arch/arm64/boot/dts/broadcom/bcm2712.dtsi
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@ -192,6 +192,12 @@ soc: soc@107c000000 {
#address-cells = <1>;
#size-cells = <1>;
pcie_rescal: reset-controller@119500 {
compatible = "brcm,bcm7216-pcie-sata-rescal";
reg = <0x00119500 0x10>;
#reset-cells = <0>;
};
sdio1: mmc@fff000 {
compatible = "brcm,bcm2712-sdhci",
"brcm,sdhci-brcmstb";
@ -204,6 +210,12 @@ sdio1: mmc@fff000 {
mmc-ddr-3_3v;
};
bcm_reset: reset-controller@1504318 {
compatible = "brcm,brcmstb-reset";
reg = <0x01504318 0x30>;
#reset-cells = <1>;
};
system_timer: timer@7c003000 {
compatible = "brcm,bcm2835-system-timer";
reg = <0x7c003000 0x1000>;
@ -426,6 +438,141 @@ axi: axi {
vc4: gpu {
compatible = "brcm,bcm2712-vc6";
};
pcie0: pcie@1000100000 {
compatible = "brcm,bcm2712-pcie";
reg = <0x10 0x00100000 0x00 0x9310>;
device_type = "pci";
linux,pci-domain = <0>;
max-link-speed = <2>;
num-lanes = <1>;
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
interrupt-parent = <&gicv2>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "msi";
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
resets = <&pcie_rescal>, <&bcm_reset 42>;
reset-names = "rescal", "bridge";
msi-controller;
msi-parent = <&pcie0>;
ranges =
/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
<0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>,
/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
<0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>;
dma-ranges =
/* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
<0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>;
status = "disabled";
};
pcie1: pcie@1000110000 {
compatible = "brcm,bcm2712-pcie";
reg = <0x10 0x00110000 0x00 0x9310>;
device_type = "pci";
linux,pci-domain = <1>;
max-link-speed = <2>;
num-lanes = <1>;
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
interrupt-parent = <&gicv2>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "msi";
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
resets = <&pcie_rescal>, <&bcm_reset 43>;
reset-names = "rescal", "bridge";
msi-controller;
msi-parent = <&mip1>;
ranges =
/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
<0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>,
/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
<0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>;
dma-ranges =
/* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */
<0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
/* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */
<0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>;
status = "disabled";
};
pcie2: pcie@1000120000 {
compatible = "brcm,bcm2712-pcie";
reg = <0x10 0x00120000 0x00 0x9310>;
device_type = "pci";
linux,pci-domain = <2>;
max-link-speed = <2>;
num-lanes = <4>;
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
interrupt-parent = <&gicv2>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "msi";
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
resets = <&pcie_rescal>, <&bcm_reset 44>;
reset-names = "rescal", "bridge";
msi-controller;
msi-parent = <&mip0>;
ranges =
/* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
<0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>,
/* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
<0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>;
dma-ranges =
/* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
<0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>,
/* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
<0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
/* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */
<0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>;
status = "disabled";
};
mip0: msi-controller@1000130000 {
compatible = "brcm,bcm2712-mip";
reg = <0x10 0x00130000 0x00 0xc0>,
<0xff 0xfffff000 0x00 0x1000>;
msi-controller;
msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
brcm,msi-offset = <0>;
};
mip1: msi-controller@1000131000 {
compatible = "brcm,bcm2712-mip";
reg = <0x10 0x00131000 0x00 0xc0>,
<0xff 0xfffff000 0x00 0x1000>;
msi-controller;
msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>;
brcm,msi-offset = <8>;
};
};
timer {