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drm/amd/pm/powerplay/smumgr: Fix PCIeBootLinkLevel value on Iceland

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Previously this was initialized with zero which represented PCIe Gen
1.0 instead of using the
maximum value from the speed table which is the behaviour of all other
smumgr implementations.

Fixes: 18aafc59b1 ("drm/amd/powerplay: implement fw related smu interface for iceland.")
Signed-off-by: John Smith <itistotalbotnet@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 92b0a6ae66)
This commit is contained in:
John Smith 2025-10-21 11:09:09 +02:00 committed by Alex Deucher
parent 07a13f913c
commit 501672e3c1
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c
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@ -2028,7 +2028,7 @@ static int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
table->VoltageResponseTime = 0;
table->PhaseResponseTime = 0;
table->MemoryThermThrottleEnable = 1;
table->PCIeBootLinkLevel = 0;
table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
table->PCIeGenInterval = 1;
result = iceland_populate_smc_svi2_config(hwmgr, table);