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clk: renesas: rcar-gen3: Increase Z clock accuracy

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Improve accuracy in the .determine_rate() callback for Z and Z2 clocks
by using rounded divisions.  This is similar to the calculation of rates
and multipliers in the .recalc_rate() resp. set_rate() callbacks.

Sample impact for a few requested clock rates:
  - R-Car H3:
      - Z 500 MHz:	468 MHz => 515 MHz
      - Z2 1000 MHz:	973 MHz => 1011 MHz
  - R-Car M3-W:
      - Z 500 MHz:	422 MHz => 516 MHz
      - Z2 800 MHz:	750 MHz => 788 MHz

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20210326120100.1577596-6-geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2021-03-26 13:00:58 +01:00
parent 67a1b9b651
commit 50086045bd
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/renesas/rcar-gen3-cpg.c
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@ -83,10 +83,10 @@ static int cpg_z_clk_determine_rate(struct clk_hw *hw,
if (max_mult < min_mult)
return -EINVAL;
mult = div64_ul(req->rate * 32ULL, prate);
mult = DIV_ROUND_CLOSEST_ULL(req->rate * 32ULL, prate);
mult = clamp(mult, min_mult, max_mult);
req->rate = div_u64((u64)prate * mult, 32);
req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
return 0;
}