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drm/xe: Move engines' non-LRC programming RTP table off the stack
The 'engine_sr' RTP table was allocated on the stack because it wasn't truly constant and needed to calculate the proper value for RING_CMD_CCTL at runtime based on other stack variables. Using the FIELD_SET_FUNC action allows us to make the table itself truly constant and move it off the stack; the RING_CMD_CCTL value is now calculated during RTP table processing. v2: - Made table static Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patch.msgid.link/20260617-rtp_with_dynamic_vals-v2-4-3f4cb34c2ea1@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
This commit is contained in:
Matt Roper
parent
431a233c17
commit
4ff7902a64
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@ -387,86 +387,92 @@ void xe_hw_engine_setup_reg_lrc(struct xe_hw_engine *hwe)
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xe_tuning_process_lrc(hwe);
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}
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/*
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* RING_CMD_CCTL specifies the default MOCS entry that will be
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* used by the command streamer when executing commands that
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* don't have a way to explicitly specify a MOCS setting.
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* The default should usually reference whichever MOCS entry
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* corresponds to uncached behavior, although use of a WB cached
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* entry is recommended by the spec in certain circumstances on
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* specific platforms.
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* Bspec: 72161
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*/
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static u32 ring_cmd_cctl_val(struct xe_gt *gt, struct xe_hw_engine *hwe)
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{
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struct xe_device *xe = gt_to_xe(gt);
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u8 mocs_read_idx = gt->mocs.uc_index;
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if (hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&
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(GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC))
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mocs_read_idx = gt->mocs.wb_index;
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return REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, gt->mocs.uc_index) |
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REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
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}
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static const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
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{ XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
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XE_RTP_RULES(FUNC(xe_rtp_match_always)),
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XE_RTP_ACTIONS(FIELD_SET_FUNC(RING_CMD_CCTL(0),
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CMD_CCTL_WRITE_OVERRIDE_MASK |
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CMD_CCTL_READ_OVERRIDE_MASK,
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ring_cmd_cctl_val,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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{ XE_RTP_NAME("Disable HW status page updates for interrupts"),
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XE_RTP_RULES(FUNC(xe_rtp_match_always)),
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XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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{ XE_RTP_NAME("Disable engine 'legacy' mode"),
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XE_RTP_RULES(FUNC(xe_rtp_match_always)),
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XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_DISABLE_LEGACY_MODE,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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/*
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* To allow the GSC engine to go idle on MTL we need to enable
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* idle messaging and set the hysteresis value (we use 0xA=5us
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* as recommended in spec). On platforms after MTL this is
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* enabled by default.
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*/
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{ XE_RTP_NAME("MTL GSCCS IDLE MSG enable"),
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XE_RTP_RULES(MEDIA_VERSION(1300), ENGINE_CLASS(OTHER)),
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XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0),
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IDLE_MSG_DISABLE,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)),
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FIELD_SET(RING_PWRCTX_MAXCNT(0),
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IDLE_WAIT_TIME,
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0xA,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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/* Enable Priority Mem Read */
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{ XE_RTP_NAME("Priority_Mem_Read"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
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XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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{ XE_RTP_NAME("Enable CCS Engine(s)"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED),
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FUNC(xe_rtp_match_first_render_or_compute)),
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XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE))
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},
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/* Use Fixed slice CCS mode */
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{ XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"),
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XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)),
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XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
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RCU_MODE_FIXED_SLICE_CCS_MODE))
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},
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{ XE_RTP_NAME("Enable MSI-X interrupt support"),
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XE_RTP_RULES(FUNC(xe_rtp_match_has_msix)),
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XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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);
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static void
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hw_engine_setup_default_state(struct xe_hw_engine *hwe)
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{
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struct xe_gt *gt = hwe->gt;
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struct xe_device *xe = gt_to_xe(gt);
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/*
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* RING_CMD_CCTL specifies the default MOCS entry that will be
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* used by the command streamer when executing commands that
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* don't have a way to explicitly specify a MOCS setting.
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* The default should usually reference whichever MOCS entry
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* corresponds to uncached behavior, although use of a WB cached
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* entry is recommended by the spec in certain circumstances on
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* specific platforms.
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* Bspec: 72161
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*/
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const u8 mocs_write_idx = gt->mocs.uc_index;
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const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&
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(GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ?
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gt->mocs.wb_index : gt->mocs.uc_index;
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u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
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REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
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struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe);
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const struct xe_rtp_table_sr engine_sr = XE_RTP_TABLE_SR(
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{ XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"),
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XE_RTP_RULES(FUNC(xe_rtp_match_always)),
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XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0),
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CMD_CCTL_WRITE_OVERRIDE_MASK |
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CMD_CCTL_READ_OVERRIDE_MASK,
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ring_cmd_cctl_val,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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{ XE_RTP_NAME("Disable HW status page updates for interrupts"),
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XE_RTP_RULES(FUNC(xe_rtp_match_always)),
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XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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{ XE_RTP_NAME("Disable engine 'legacy' mode"),
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XE_RTP_RULES(FUNC(xe_rtp_match_always)),
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XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_DISABLE_LEGACY_MODE,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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/*
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* To allow the GSC engine to go idle on MTL we need to enable
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* idle messaging and set the hysteresis value (we use 0xA=5us
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* as recommended in spec). On platforms after MTL this is
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* enabled by default.
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*/
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{ XE_RTP_NAME("MTL GSCCS IDLE MSG enable"),
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XE_RTP_RULES(MEDIA_VERSION(1300), ENGINE_CLASS(OTHER)),
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XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0),
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IDLE_MSG_DISABLE,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)),
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FIELD_SET(RING_PWRCTX_MAXCNT(0),
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IDLE_WAIT_TIME,
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0xA,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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/* Enable Priority Mem Read */
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{ XE_RTP_NAME("Priority_Mem_Read"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
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XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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{ XE_RTP_NAME("Enable CCS Engine(s)"),
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XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED),
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FUNC(xe_rtp_match_first_render_or_compute)),
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XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE))
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},
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/* Use Fixed slice CCS mode */
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{ XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"),
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XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)),
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XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE,
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RCU_MODE_FIXED_SLICE_CCS_MODE))
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},
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{ XE_RTP_NAME("Enable MSI-X interrupt support"),
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XE_RTP_RULES(FUNC(xe_rtp_match_has_msix)),
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XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE,
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XE_RTP_ACTION_FLAG(ENGINE_BASE)))
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},
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);
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xe_rtp_process_to_sr(&ctx, &engine_sr, &hwe->reg_sr, false);
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}
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