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mmc: sdhci-uhs2: add related functions to initialize the interface
UHS-II interface (related registers) will be initialized here. The operations include mmc's uhs2_set_reg operations, mmc's uhs2_detect_init operations, uhs2_[enable|disable]_clk operations. After detected the UHS-II interface, the host's UHS-II capabilities will be set up here and interrupts will also be enabled. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Message-ID: <20241018105333.4569-11-victorshihgli@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Victor Shih
Ulf Hansson
parent
10c8298a05
commit
4f412f7918
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@ -26,6 +26,9 @@
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pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
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#define UHS2_RESET_TIMEOUT_100MS 100000
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#define UHS2_CHECK_DORMANT_TIMEOUT_100MS 100000
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#define UHS2_INTERFACE_DETECT_TIMEOUT_100MS 100000
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#define UHS2_LANE_SYNC_TIMEOUT_150MS 150000
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void sdhci_uhs2_dump_regs(struct sdhci_host *host)
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{
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@ -303,6 +306,186 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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return 0;
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}
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static int sdhci_uhs2_interface_detect(struct sdhci_host *host)
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{
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u32 val;
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if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT),
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100, UHS2_INTERFACE_DETECT_TIMEOUT_100MS, true,
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host, SDHCI_PRESENT_STATE)) {
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pr_warn("%s: not detect UHS2 interface in 100ms.\n", mmc_hostname(host->mmc));
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sdhci_dumpregs(host);
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return -EIO;
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}
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/* Enable UHS2 error interrupts */
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sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK);
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if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC),
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100, UHS2_LANE_SYNC_TIMEOUT_150MS, true, host, SDHCI_PRESENT_STATE)) {
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pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc));
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sdhci_dumpregs(host);
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return -EIO;
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}
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DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n",
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mmc_hostname(host->mmc));
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return 0;
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}
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static int sdhci_uhs2_init(struct sdhci_host *host)
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{
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u16 caps_ptr = 0;
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u32 caps_gen = 0;
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u32 caps_phy = 0;
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u32 caps_tran[2] = {0, 0};
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struct mmc_host *mmc = host->mmc;
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caps_ptr = sdhci_readw(host, SDHCI_UHS2_CAPS_PTR);
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if (caps_ptr < 0x100 || caps_ptr > 0x1FF) {
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pr_err("%s: SDHCI_UHS2_CAPS_PTR(%d) is wrong.\n",
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mmc_hostname(mmc), caps_ptr);
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return -ENODEV;
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}
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caps_gen = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_OFFSET);
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caps_phy = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_PHY_OFFSET);
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caps_tran[0] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_OFFSET);
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caps_tran[1] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_1_OFFSET);
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/* General Caps */
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mmc->uhs2_caps.dap = caps_gen & SDHCI_UHS2_CAPS_DAP_MASK;
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mmc->uhs2_caps.gap = FIELD_GET(SDHCI_UHS2_CAPS_GAP_MASK, caps_gen);
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mmc->uhs2_caps.n_lanes = FIELD_GET(SDHCI_UHS2_CAPS_LANE_MASK, caps_gen);
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mmc->uhs2_caps.addr64 = (caps_gen & SDHCI_UHS2_CAPS_ADDR_64) ? 1 : 0;
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mmc->uhs2_caps.card_type = FIELD_GET(SDHCI_UHS2_CAPS_DEV_TYPE_MASK, caps_gen);
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/* PHY Caps */
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mmc->uhs2_caps.phy_rev = caps_phy & SDHCI_UHS2_CAPS_PHY_REV_MASK;
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mmc->uhs2_caps.speed_range = FIELD_GET(SDHCI_UHS2_CAPS_PHY_RANGE_MASK, caps_phy);
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mmc->uhs2_caps.n_lss_sync = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MASK, caps_phy);
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mmc->uhs2_caps.n_lss_dir = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK, caps_phy);
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if (mmc->uhs2_caps.n_lss_sync == 0)
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mmc->uhs2_caps.n_lss_sync = 16 << 2;
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else
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mmc->uhs2_caps.n_lss_sync <<= 2;
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if (mmc->uhs2_caps.n_lss_dir == 0)
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mmc->uhs2_caps.n_lss_dir = 16 << 3;
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else
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mmc->uhs2_caps.n_lss_dir <<= 3;
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/* LINK/TRAN Caps */
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mmc->uhs2_caps.link_rev = caps_tran[0] & SDHCI_UHS2_CAPS_TRAN_LINK_REV_MASK;
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mmc->uhs2_caps.n_fcu = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK, caps_tran[0]);
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if (mmc->uhs2_caps.n_fcu == 0)
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mmc->uhs2_caps.n_fcu = 256;
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mmc->uhs2_caps.host_type = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MASK, caps_tran[0]);
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mmc->uhs2_caps.maxblk_len = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK, caps_tran[0]);
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mmc->uhs2_caps.n_data_gap = caps_tran[1] & SDHCI_UHS2_CAPS_TRAN_1_N_DATA_GAP_MASK;
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return 0;
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}
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static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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DBG("Begin do uhs2 detect init.\n");
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if (sdhci_uhs2_interface_detect(host)) {
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pr_warn("%s: cannot detect UHS2 interface.\n", mmc_hostname(host->mmc));
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return -EIO;
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}
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if (sdhci_uhs2_init(host)) {
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pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc));
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return -EIO;
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}
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/* Init complete, do soft reset and enable UHS2 error irqs. */
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sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD);
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sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK);
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/*
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* N.B SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared
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* by SDHCI_UHS2_SW_RESET_SD
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*/
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sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
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sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
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return 0;
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}
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static int sdhci_uhs2_disable_clk(struct mmc_host *mmc)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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clk &= ~SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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return 0;
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}
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static int sdhci_uhs2_enable_clk(struct mmc_host *mmc)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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int timeout_us = 20000; /* 20ms */
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u32 val;
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clk |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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if (read_poll_timeout(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE),
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10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) {
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pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc));
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sdhci_dumpregs(host);
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return -EIO;
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}
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return 0;
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}
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static void sdhci_uhs2_set_config(struct sdhci_host *host)
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{
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u32 value;
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u16 sdhci_uhs2_set_ptr = sdhci_readw(host, SDHCI_UHS2_SETTINGS_PTR);
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u16 sdhci_uhs2_gen_set_reg = sdhci_uhs2_set_ptr;
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u16 sdhci_uhs2_phy_set_reg = sdhci_uhs2_set_ptr + 4;
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u16 sdhci_uhs2_tran_set_reg = sdhci_uhs2_set_ptr + 8;
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u16 sdhci_uhs2_tran_set_1_reg = sdhci_uhs2_set_ptr + 12;
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/* Set Gen Settings */
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value = FIELD_PREP(SDHCI_UHS2_GEN_SETTINGS_N_LANES_MASK, host->mmc->uhs2_caps.n_lanes_set);
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sdhci_writel(host, value, sdhci_uhs2_gen_set_reg);
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/* Set PHY Settings */
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value = FIELD_PREP(SDHCI_UHS2_PHY_N_LSS_DIR_MASK, host->mmc->uhs2_caps.n_lss_dir_set) |
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FIELD_PREP(SDHCI_UHS2_PHY_N_LSS_SYN_MASK, host->mmc->uhs2_caps.n_lss_sync_set);
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if (host->mmc->ios.timing == MMC_TIMING_UHS2_SPEED_B ||
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host->mmc->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD)
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value |= SDHCI_UHS2_PHY_SET_SPEED_B;
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sdhci_writel(host, value, sdhci_uhs2_phy_set_reg);
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/* Set LINK-TRAN Settings */
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value = FIELD_PREP(SDHCI_UHS2_TRAN_RETRY_CNT_MASK, host->mmc->uhs2_caps.max_retry_set) |
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FIELD_PREP(SDHCI_UHS2_TRAN_N_FCU_MASK, host->mmc->uhs2_caps.n_fcu_set);
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sdhci_writel(host, value, sdhci_uhs2_tran_set_reg);
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sdhci_writel(host, host->mmc->uhs2_caps.n_data_gap_set, sdhci_uhs2_tran_set_1_reg);
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}
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static int sdhci_uhs2_check_dormant(struct sdhci_host *host)
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{
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u32 val;
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if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_IN_DORMANT_STATE),
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100, UHS2_CHECK_DORMANT_TIMEOUT_100MS, true, host,
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SDHCI_PRESENT_STATE)) {
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pr_warn("%s: UHS2 IN_DORMANT fail in 100ms.\n", mmc_hostname(host->mmc));
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sdhci_dumpregs(host);
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return -EIO;
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}
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return 0;
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}
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static int sdhci_uhs2_control(struct mmc_host *mmc, enum sd_uhs2_operation op)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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@ -312,6 +495,27 @@ static int sdhci_uhs2_control(struct mmc_host *mmc, enum sd_uhs2_operation op)
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DBG("Begin uhs2 control, act %d.\n", op);
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switch (op) {
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case UHS2_PHY_INIT:
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err = sdhci_uhs2_do_detect_init(mmc);
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break;
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case UHS2_SET_CONFIG:
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sdhci_uhs2_set_config(host);
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break;
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case UHS2_ENABLE_INT:
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sdhci_uhs2_clear_set_irqs(host, 0, SDHCI_INT_CARD_INT);
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break;
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case UHS2_DISABLE_INT:
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sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_CARD_INT, 0);
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break;
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case UHS2_CHECK_DORMANT:
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err = sdhci_uhs2_check_dormant(host);
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break;
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case UHS2_DISABLE_CLK:
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err = sdhci_uhs2_disable_clk(mmc);
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break;
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case UHS2_ENABLE_CLK:
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err = sdhci_uhs2_enable_clk(mmc);
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break;
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case UHS2_SET_IOS:
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err = sdhci_uhs2_set_ios(mmc, ios);
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break;
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