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ASoC: tlv320adcx140: Add a new kcontrol
Add a new kcontrol for phase calib Signed-off-by: Kevin Lu <luminlong@139.com> Link: https://lore.kernel.org/r/20220815112715.21617-1-luminlong@139.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -31,6 +31,7 @@ struct adcx140_priv {
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struct device *dev;
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struct device *dev;
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bool micbias_vg;
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bool micbias_vg;
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bool phase_calib_on;
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unsigned int dai_fmt;
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unsigned int dai_fmt;
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unsigned int slot_width;
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unsigned int slot_width;
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@ -592,6 +593,52 @@ static const struct snd_soc_dapm_route adcx140_audio_map[] = {
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{"MIC4M Input Mux", "Digital", "MIC4M"},
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{"MIC4M Input Mux", "Digital", "MIC4M"},
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};
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};
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#define ADCX140_PHASE_CALIB_SWITCH(xname) {\
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.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
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.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
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.info = adcx140_phase_calib_info, \
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.get = adcx140_phase_calib_get, \
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.put = adcx140_phase_calib_put}
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static int adcx140_phase_calib_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *uinfo)
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{
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uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
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uinfo->count = 1;
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uinfo->value.integer.min = 0;
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uinfo->value.integer.max = 1;
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return 0;
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}
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static int adcx140_phase_calib_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *value)
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{
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struct snd_soc_component *codec =
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snd_soc_kcontrol_component(kcontrol);
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struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(codec);
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value->value.integer.value[0] = adcx140->phase_calib_on ? 1 : 0;
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return 0;
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}
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static int adcx140_phase_calib_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *value)
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{
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struct snd_soc_component *codec
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= snd_soc_kcontrol_component(kcontrol);
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struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(codec);
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bool v = value->value.integer.value[0] ? true : false;
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if (adcx140->phase_calib_on != v) {
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adcx140->phase_calib_on = v;
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return 1;
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}
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return 0;
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}
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static const struct snd_kcontrol_new adcx140_snd_controls[] = {
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static const struct snd_kcontrol_new adcx140_snd_controls[] = {
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SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
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SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
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adc_tlv),
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adc_tlv),
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@ -628,6 +675,7 @@ static const struct snd_kcontrol_new adcx140_snd_controls[] = {
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0, 0xff, 0, dig_vol_tlv),
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0, 0xff, 0, dig_vol_tlv),
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SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2,
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SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2,
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0, 0xff, 0, dig_vol_tlv),
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0, 0xff, 0, dig_vol_tlv),
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ADCX140_PHASE_CALIB_SWITCH("Phase Calibration Switch"),
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};
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};
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static int adcx140_reset(struct adcx140_priv *adcx140)
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static int adcx140_reset(struct adcx140_priv *adcx140)
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@ -653,6 +701,8 @@ static int adcx140_reset(struct adcx140_priv *adcx140)
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static void adcx140_pwr_ctrl(struct adcx140_priv *adcx140, bool power_state)
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static void adcx140_pwr_ctrl(struct adcx140_priv *adcx140, bool power_state)
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{
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{
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int pwr_ctrl = 0;
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int pwr_ctrl = 0;
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int ret = 0;
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struct snd_soc_component *component = adcx140->component;
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if (power_state)
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if (power_state)
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pwr_ctrl = ADCX140_PWR_CFG_ADC_PDZ | ADCX140_PWR_CFG_PLL_PDZ;
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pwr_ctrl = ADCX140_PWR_CFG_ADC_PDZ | ADCX140_PWR_CFG_PLL_PDZ;
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@ -660,6 +710,14 @@ static void adcx140_pwr_ctrl(struct adcx140_priv *adcx140, bool power_state)
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if (adcx140->micbias_vg && power_state)
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if (adcx140->micbias_vg && power_state)
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pwr_ctrl |= ADCX140_PWR_CFG_BIAS_PDZ;
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pwr_ctrl |= ADCX140_PWR_CFG_BIAS_PDZ;
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if (pwr_ctrl) {
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ret = regmap_write(adcx140->regmap, ADCX140_PHASE_CALIB,
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adcx140->phase_calib_on ? 0x00 : 0x40);
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if (ret)
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dev_err(component->dev, "%s: register write error %d\n",
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__func__, ret);
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}
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regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG,
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regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG,
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ADCX140_PWR_CTRL_MSK, pwr_ctrl);
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ADCX140_PWR_CTRL_MSK, pwr_ctrl);
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}
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}
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@ -1095,6 +1153,7 @@ static int adcx140_i2c_probe(struct i2c_client *i2c)
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if (!adcx140)
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if (!adcx140)
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return -ENOMEM;
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return -ENOMEM;
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adcx140->phase_calib_on = false;
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adcx140->dev = &i2c->dev;
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adcx140->dev = &i2c->dev;
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adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev,
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adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev,
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@ -90,6 +90,7 @@
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#define ADCX140_PWR_CFG 0x75
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#define ADCX140_PWR_CFG 0x75
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#define ADCX140_DEV_STS0 0x76
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#define ADCX140_DEV_STS0 0x76
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#define ADCX140_DEV_STS1 0x77
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#define ADCX140_DEV_STS1 0x77
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#define ADCX140_PHASE_CALIB 0X7b
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#define ADCX140_RESET BIT(0)
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#define ADCX140_RESET BIT(0)
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