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ARM: dts: sunxi: Fix OPP arrays

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Even though it translates to the same thing down to the binary level, we
should have an array of 2 number cells to describe each OPP, which in
turns create a validation warning.

Let's fix this.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20210901091852.479202-42-maxime@cerno.tech
This commit is contained in:
Maxime Ripard 2021-09-01 11:18:41 +02:00
parent f7717f2874
commit 4e0d439dbb
No known key found for this signature in database
GPG Key ID: E3EF0D6F671851C5
6 changed files with 61 additions and 71 deletions
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11
arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
View File

@ -91,12 +91,11 @@ &cpu0 {
/*
* The A10-Lime is known to be unstable when running at 1008 MHz
*/
operating-points = <
/* kHz uV */
912000 1350000
864000 1300000
624000 1250000
>;
operating-points =
/* kHz uV */
<912000 1350000>,
<864000 1300000>,
<624000 1250000>;
};
&de {

11
arch/arm/boot/dts/sun4i-a10.dtsi
View File

@ -115,13 +115,12 @@ cpu0: cpu@0 {
reg = <0x0>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
operating-points =
/* kHz uV */
1008000 1400000
912000 1350000
864000 1300000
624000 1250000
>;
<1008000 1400000>,
<912000 1350000>,
<864000 1300000>,
<624000 1250000>;
#cooling-cells = <2>;
};
};

15
arch/arm/boot/dts/sun5i-a13.dtsi
View File

@ -102,15 +102,14 @@ &ccu {
&cpu0 {
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
operating-points =
/* kHz uV */
1008000 1400000
912000 1350000
864000 1300000
624000 1200000
576000 1200000
432000 1200000
>;
<1008000 1400000>,
<912000 1350000>,
<864000 1300000>,
<624000 1200000>,
<576000 1200000>,
<432000 1200000>;
#cooling-cells = <2>;
};

44
arch/arm/boot/dts/sun6i-a31.dtsi
View File

@ -105,13 +105,12 @@ cpu0: cpu@0 {
reg = <0>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
operating-points =
/* kHz uV */
1008000 1200000
864000 1200000
720000 1100000
480000 1000000
>;
<1008000 1200000>,
<864000 1200000>,
<720000 1100000>,
<480000 1000000>;
#cooling-cells = <2>;
};
@ -121,13 +120,12 @@ cpu1: cpu@1 {
reg = <1>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
operating-points =
/* kHz uV */
1008000 1200000
864000 1200000
720000 1100000
480000 1000000
>;
<1008000 1200000>,
<864000 1200000>,
<720000 1100000>,
<480000 1000000>;
#cooling-cells = <2>;
};
@ -137,13 +135,12 @@ cpu2: cpu@2 {
reg = <2>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
operating-points =
/* kHz uV */
1008000 1200000
864000 1200000
720000 1100000
480000 1000000
>;
<1008000 1200000>,
<864000 1200000>,
<720000 1100000>,
<480000 1000000>;
#cooling-cells = <2>;
};
@ -153,13 +150,12 @@ cpu3: cpu@3 {
reg = <3>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
operating-points =
/* kHz uV */
1008000 1200000
864000 1200000
720000 1100000
480000 1000000
>;
<1008000 1200000>,
<864000 1200000>,
<720000 1100000>,
<480000 1000000>;
#cooling-cells = <2>;
};
};

17
arch/arm/boot/dts/sun7i-a20-bananapi.dts
View File

@ -104,16 +104,15 @@ &codec {
&cpu0 {
cpu-supply = <&reg_dcdc2>;
operating-points = <
operating-points =
/* kHz uV */
960000 1400000
912000 1400000
864000 1350000
720000 1250000
528000 1150000
312000 1100000
144000 1050000
>;
<960000 1400000>,
<912000 1400000>,
<864000 1350000>,
<720000 1250000>,
<528000 1150000>,
<312000 1100000>,
<144000 1050000>;
};
&de {

34
arch/arm/boot/dts/sun7i-a20.dtsi
View File

@ -106,16 +106,15 @@ cpu0: cpu@0 {
reg = <0>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
operating-points =
/* kHz uV */
960000 1400000
912000 1400000
864000 1300000
720000 1200000
528000 1100000
312000 1000000
144000 1000000
>;
<960000 1400000>,
<912000 1400000>,
<864000 1300000>,
<720000 1200000>,
<528000 1100000>,
<312000 1000000>,
<144000 1000000>;
#cooling-cells = <2>;
};
@ -125,16 +124,15 @@ cpu1: cpu@1 {
reg = <1>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
operating-points =
/* kHz uV */
960000 1400000
912000 1400000
864000 1300000
720000 1200000
528000 1100000
312000 1000000
144000 1000000
>;
<960000 1400000>,
<912000 1400000>,
<864000 1300000>,
<720000 1200000>,
<528000 1100000>,
<312000 1000000>,
<144000 1000000>;
#cooling-cells = <2>;
};
};