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dt-bindings: net: micrel: Convert to DT schema
Convert the devicetree bindings for the Micrel PHYs and switches to DT schema. Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260116130948.79558-2-eichest@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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Micrel PHY properties.
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These properties cover the base properties Micrel PHYs.
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Optional properties:
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- micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
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Configure the LED mode with single value. The list of PHYs and the
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bits that are currently supported:
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KSZ8001: register 0x1e, bits 15..14
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KSZ8041: register 0x1e, bits 15..14
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KSZ8021: register 0x1f, bits 5..4
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KSZ8031: register 0x1f, bits 5..4
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KSZ8051: register 0x1f, bits 5..4
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KSZ8081: register 0x1f, bits 5..4
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KSZ8091: register 0x1f, bits 5..4
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LAN8814: register EP5.0, bit 6
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See the respective PHY datasheet for the mode values.
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- micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
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bit selects 25 MHz mode
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Setting the RMII Reference Clock Select bit enables 25 MHz rather
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than 50 MHz clock mode.
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Note that this option is only needed for certain PHY revisions with a
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non-standard, inverted function of this configuration bit.
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Specifically, a clock reference ("rmii-ref" below) is always needed to
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actually select a mode.
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- clocks, clock-names: contains clocks according to the common clock bindings.
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supported clocks:
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- KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
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input clock. Used to determine the XI input clock.
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- micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
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Some PHYs, such as the KSZ8041FTL variant, support fiber mode, enabled
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by the FXEN boot strapping pin. It can't be determined from the PHY
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registers whether the PHY is in fiber mode, so this boolean device tree
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property can be used to describe it.
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In fiber mode, auto-negotiation is disabled and the PHY can only work in
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100base-fx (full and half duplex) modes.
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- coma-mode-gpios: If present the given gpio will be deasserted when the
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PHY is probed.
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Some PHYs have a COMA mode input pin which puts the PHY into
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isolate and power-down mode. On some boards this input is connected
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to a GPIO of the SoC.
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Supported on the LAN8814.
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131
Documentation/devicetree/bindings/net/micrel.yaml
Normal file
131
Documentation/devicetree/bindings/net/micrel.yaml
Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/micrel.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Micrel KSZ series PHYs and switches
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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- Stefan Eichenberger <eichest@gmail.com>
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description:
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The Micrel KSZ series contains different network phys and switches.
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properties:
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compatible:
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enum:
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- ethernet-phy-id000e.7237 # KSZ8873MLL
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- ethernet-phy-id0022.1430 # KSZ886X
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- ethernet-phy-id0022.1435 # KSZ8863
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- ethernet-phy-id0022.1510 # KSZ8041
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- ethernet-phy-id0022.1537 # KSZ8041RNLI
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- ethernet-phy-id0022.1550 # KSZ8051
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- ethernet-phy-id0022.1555 # KSZ8021
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- ethernet-phy-id0022.1556 # KSZ8031
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- ethernet-phy-id0022.1560 # KSZ8081, KSZ8091
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- ethernet-phy-id0022.1570 # KSZ8061
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- ethernet-phy-id0022.161a # KSZ8001
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- ethernet-phy-id0022.1720 # KS8737
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micrel,fiber-mode:
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type: boolean
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description: |
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If present the PHY is configured to operate in fiber mode.
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The KSZ8041FTL variant supports fiber mode, enabled by the FXEN
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boot strapping pin. It can't be determined from the PHY registers
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whether the PHY is in fiber mode, so this boolean device tree
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property can be used to describe it.
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In fiber mode, auto-negotiation is disabled and the PHY can only
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work in 100base-fx (full and half duplex) modes.
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micrel,led-mode:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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LED mode value to set for PHYs with configurable LEDs.
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Configure the LED mode with single value. The list of PHYs and the
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bits that are currently supported:
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KSZ8001: register 0x1e, bits 15..14
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KSZ8041: register 0x1e, bits 15..14
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KSZ8021: register 0x1f, bits 5..4
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KSZ8031: register 0x1f, bits 5..4
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KSZ8051: register 0x1f, bits 5..4
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KSZ8081: register 0x1f, bits 5..4
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KSZ8091: register 0x1f, bits 5..4
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See the respective PHY datasheet for the mode values.
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minimum: 0
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maximum: 3
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allOf:
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- $ref: ethernet-phy.yaml#
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- if:
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not:
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properties:
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compatible:
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contains:
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const: ethernet-phy-id0022.1510
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then:
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properties:
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micrel,fiber-mode: false
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- if:
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not:
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properties:
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compatible:
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contains:
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enum:
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- ethernet-phy-id0022.1510
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- ethernet-phy-id0022.1555
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- ethernet-phy-id0022.1556
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- ethernet-phy-id0022.1550
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- ethernet-phy-id0022.1560
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- ethernet-phy-id0022.161a
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then:
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properties:
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micrel,led-mode: false
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- if:
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properties:
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compatible:
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contains:
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enum:
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- ethernet-phy-id0022.1555
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- ethernet-phy-id0022.1556
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- ethernet-phy-id0022.1560
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then:
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properties:
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clock-names:
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const: rmii-ref
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description:
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The RMII reference input clock. Used to determine the XI input
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clock.
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micrel,rmii-reference-clock-select-25-mhz:
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type: boolean
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description: |
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RMII Reference Clock Select bit selects 25 MHz mode
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Setting the RMII Reference Clock Select bit enables 25 MHz rather
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than 50 MHz clock mode.
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dependentRequired:
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micrel,rmii-reference-clock-select-25-mhz: [ clock-names ]
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unevaluatedProperties: false
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examples:
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- |
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-phy@5 {
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compatible = "ethernet-phy-id0022.1510";
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reg = <5>;
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micrel,led-mode = <2>;
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micrel,fiber-mode;
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};
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};
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