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drm/amd/powerplay: move dpm feature support checking to smu_cmn.c

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Considering it is shared by all ASICs and smu_cmn.c should be
the right place.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2020-07-07 10:18:02 +08:00 committed by Alex Deucher
parent d23c3ccc21
commit 4d942ae349
7 changed files with 35 additions and 33 deletions
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21
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
View File

@ -582,27 +582,6 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
enable);
}
int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)
{
struct smu_feature *feature = &smu->smu_feature;
int feature_id;
int ret = 0;
feature_id = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_FEATURE,
mask);
if (feature_id < 0)
return 0;
WARN_ON(feature_id > feature->feature_num);
mutex_lock(&feature->mutex);
ret = test_bit(feature_id, feature->supported);
mutex_unlock(&feature->mutex);
return ret;
}
static int smu_set_funcs(struct amdgpu_device *adev)
{
struct smu_context *smu = &adev->smu;

2
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
View File

@ -732,8 +732,6 @@ extern int smu_feature_is_enabled(struct smu_context *smu,
enum smu_feature_mask mask);
extern int smu_feature_set_enabled(struct smu_context *smu,
enum smu_feature_mask mask, bool enable);
extern int smu_feature_is_supported(struct smu_context *smu,
enum smu_feature_mask mask);
int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,
void *table_data, bool drv2smu);

8
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
View File

@ -1266,8 +1266,8 @@ static int navi10_display_config_changed(struct smu_context *smu)
int ret = 0;
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
smu->display_config->num_display,
NULL);
@ -1544,13 +1544,13 @@ static int navi10_notify_smc_display_config(struct smu_context *smu)
min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
clock_req.clock_type = amd_pp_dcef_clock;
clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
if (!ret) {
if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_SetMinDeepSleepDcefclk,
min_clocks.dcef_clock_in_sr/100,

8
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
View File

@ -1067,8 +1067,8 @@ static int sienna_cichlid_display_config_changed(struct smu_context *smu)
int ret = 0;
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
#if 0
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
smu->display_config->num_display,
@ -1347,13 +1347,13 @@ static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
clock_req.clock_type = amd_pp_dcef_clock;
clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
if (!ret) {
if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
ret = smu_send_smc_msg_with_param(smu,
SMU_MSG_SetMinDeepSleepDcefclk,
min_clocks.dcef_clock_in_sr/100,

22
drivers/gpu/drm/amd/powerplay/smu_cmn.c
View File

@ -116,3 +116,25 @@ int smu_cmn_to_asic_specific_index(struct smu_context *smu,
return -EINVAL;
}
}
int smu_cmn_feature_is_supported(struct smu_context *smu,
enum smu_feature_mask mask)
{
struct smu_feature *feature = &smu->smu_feature;
int feature_id;
int ret = 0;
feature_id = smu_cmn_to_asic_specific_index(smu,
CMN2ASIC_MAPPING_FEATURE,
mask);
if (feature_id < 0)
return 0;
WARN_ON(feature_id > feature->feature_num);
mutex_lock(&feature->mutex);
ret = test_bit(feature_id, feature->supported);
mutex_unlock(&feature->mutex);
return ret;
}

3
drivers/gpu/drm/amd/powerplay/smu_cmn.h
View File

@ -29,4 +29,7 @@ int smu_cmn_to_asic_specific_index(struct smu_context *smu,
enum smu_cmn2asic_mapping_type type,
uint32_t index);
int smu_cmn_feature_is_supported(struct smu_context *smu,
enum smu_feature_mask mask);
#endif

4
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
View File

@ -1230,7 +1230,7 @@ smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
{
int ret = 0;
if (!smu_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
return 0;
ret = smu_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
@ -1598,7 +1598,7 @@ bool smu_v11_0_baco_is_support(struct smu_context *smu)
return false;
/* Arcturus does not support this bit mask */
if (smu_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
!smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
return false;